35757 lines
2.3 MiB
35757 lines
2.3 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAM4L On-Chip Peripherals
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; @Props: Released
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; @Author: BUJ, RAF, TPP
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; @Changelog: 2012-10-19
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: doc42023.pdf Rev. 42023B/SAM/2012-10
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; Atmel-42023-ARM-Microcontroller-ATSAM4L-Low-Power-LCD_Datasheet.pdf 42023E-SAM-2013-07
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; Atmel-42023-ARM-Microcontroller-ATSAM4L-Low-Power-LCD_Datasheet-Summary.pdf 42023ES-SAM-2013-07
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; @Core: Cortex-M4
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsam4l.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SMAP (System Manager Access Port)"
|
|
base ad:0x400A3000
|
|
width 0x09
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 4. " CE ,Chip Erase flag" "No effect,Enable"
|
|
bitfld.long 0x00 3. " FSPR ,Flash User Page Read" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CRC ,Cyclic Redundancy Code" "No effect,Enable"
|
|
bitfld.long 0x00 1. " DIS ,Disable the module" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable the module" "No effect,Enable"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 24.--26. " STAT ,State" "Idle state,Chip erase operation,CRC32 operation,Flash User Page Read,?..."
|
|
bitfld.long 0x00 10. " DBGP ,Debugger present" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PROT , The protected state" "Not set,Set"
|
|
bitfld.long 0x00 8. " EN ,Enable/disable the block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK ,Lock mode" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " FAIL , Failure flag" "No failure,Failure"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BERR ,Bus Error" "No error,Error"
|
|
bitfld.long 0x00 1. " HCR ,Hold Core reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DONE ,Operation done" "Not completed,Completed"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 4. " LCK ,Chip protected state" "No effect,Clear"
|
|
bitfld.long 0x00 3. " FAIL ,Failure flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BERR ,Bus Error" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HCR ,Hold Core reset" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DONE ,Operation done" "No effect,Clear"
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "ADDR,Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADDR ,Address Value"
|
|
line.long 0x04 "LENGTH,Length Register"
|
|
hexmask.long 0x04 2.--31. 1. " LENGTH ,Length Value"
|
|
line.long 0x08 "DATA,Data Register"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "VERSION,Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
rgroup.long 0xF0++0x07
|
|
line.long 0x00 "CIDR,Chip Identification Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "No extension,Extension"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMLESS,FLASH,ROM_FLASH,SRAM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 21.--27. 1. " ARCH ,Architecture Identifier"
|
|
bitfld.long 0x00 16.--20. " SRAMSIZ ,Internal SRAM Size" "48-KB,1-KB,2-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "None,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1024-KB,,2048-KB,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "None,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1024-KB,,2048-KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" ",ARM946ES,ARM7TDMI,Cortex-M3,ARM920T,ARM926EJS,Cortex-A5,Cortex-M4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Version of the Device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EXID,Chip Identification Extension Register"
|
|
bitfld.long 0x04 24.--26. " PACKAGE ,Package Type" "24-pin,32-pin,48-pin,64-pin,100-pin,144-pin,?..."
|
|
bitfld.long 0x04 3. " LCD ,LCD Option" "Not implemented,Implemented"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB Configuration" "Device-only,Device and Host"
|
|
bitfld.long 0x04 1. " USB ,USB Option" "Not implemented,Implemented"
|
|
elif (cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB Configuration" "Device-only,?..."
|
|
bitfld.long 0x04 1. " USB ,USB Option" "Not implemented,Implemented"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " AES ,AES Option" "Not implemented,Implemented"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "IDR,Identification Register"
|
|
bitfld.long 0x00 28.--31. " REVISION ,Revision mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CC ,JEP-106 Continuation Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 17.--23. 1. " IC ,JEP-106 Identity Code"
|
|
bitfld.long 0x00 16. " CLSS ,Class" "Not a Memory Access Port,A Memory Access Port"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " APID ,AP Identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " APIDV ,AP Identification Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0740
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension flag" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile program memory type" "ROM,Romless/flash,Embedded flash,ROM & embedded flash,SRAM emulating ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture identifier"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,192-KB,384-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
else
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,112-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
sif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,160-KB,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
else
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3S*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3N*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV70*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "MRLA,MRLB,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
else
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946E-S,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJ-S,?..."
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "Version 0,Version 1,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
endif
|
|
sif (cpuis("ATSAM4LS*")||cpuis("ATSAM4LC*"))
|
|
line.long 0x04 "EXID,Extension Register"
|
|
bitfld.long 0x04 24.--26. " PACKAGE ,Package type" "24-pin,32-pin,48-pin,64-pin,100-pin,144-pin,?..."
|
|
bitfld.long 0x04 3. " LCD ,LCD option" "Not implemented,Implemented"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,Device and host"
|
|
elif (cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,?..."
|
|
endif
|
|
bitfld.long 0x04 1. " USB ,USB option" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AES ,AES option" "Not implemented,Implemented"
|
|
else
|
|
line.long 0x04 "CHIPID_EXID,Chip ID Extension Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PM (Power Manager)"
|
|
base ad:0x400E0000
|
|
width 0x0C
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MCCTRL,Main Clock Control"
|
|
bitfld.long 0x00 0.--2. " MCSEL ,Main Clock Control" "RCSYS,OSC0,PLL,DFLL,RC80M,RCFAST,RC1M,?..."
|
|
line.long 0x04 "CPUSEL,CPU Clock Select"
|
|
bitfld.long 0x04 7. " CPUDIV ,CPU Division" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " CPUSEL ,CPU Clock Select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x0 "PBASEL,PBA Clock Select"
|
|
bitfld.long 0x0 7. " PBDIV ,PBA Division" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--2. " PBSEL ,PBA Clock Select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x4 "PBBSEL,PBB Clock Select"
|
|
bitfld.long 0x4 7. " PBDIV ,PBB Division" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--2. " PBSEL ,PBB Clock Select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x8 "PBCSEL,PBC Clock Select"
|
|
bitfld.long 0x8 7. " PBDIV ,PBC Division" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--2. " PBSEL ,PBC Clock Select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0xC "PBDSEL,PBD Clock Select"
|
|
bitfld.long 0xC 7. " PBDIV ,PBD Division" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--2. " PBSEL ,PBD Clock Select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CPUMASK,CPU Clock Mask"
|
|
bitfld.long 0x00 0. " OCD ,OCD Clock Mask" "Masked,Not masked"
|
|
line.long 0x04 "HSBMASK,HSB Clock Mask"
|
|
sif cpuis("ATSAM4LC*")
|
|
bitfld.long 0x04 9. " AESA ,AESA Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " APBD ,APBD Clock Mask" "Masked,Not masked"
|
|
else
|
|
bitfld.long 0x04 8. " APBD ,APBD Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " APBC ,APBC Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " APBB ,APBB Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " APBA ,APBA Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " CRCCU ,CRCCU Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " USBC ,USBC Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " HRAMC1 ,HRAMC1 Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FLASHCALW ,FLASHCALW Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " PDCA ,PDCA Clock Mask" "Masked,Not masked"
|
|
line.long 0x08 "PBAMASK,PBA Clock Mask"
|
|
sif cpuis("ATSAM4LC*")
|
|
bitfld.long 0x08 23. " LCDCA ,LCDCA Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " TWIM3 ,TWIM3 Clock Mask" "Masked,Not masked"
|
|
elif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x08 22. " TWIM3 ,TWIM3 Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
sif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x08 21. " TWIM2 ,TWIM2 Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " CATB ,CATB Clock Mask" "Masked,Not masked"
|
|
else
|
|
bitfld.long 0x08 19. " CATB ,CATB Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 18. " PARC ,PARC Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " TRNG ,TRNG Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " ABDACB ,ABDACB Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " GLOC ,GLOC Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " ACIFC ,ACIFC Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " DACC ,DACC Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ADCIFE ,ADCIFE Clock Mask" "Masked,Not masked"
|
|
sif !cpuis("ATSAM4LC*A")
|
|
bitfld.long 0x08 11. " USART3 ,USART3 Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 10. " USART2 ,USART2 Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " USART1 ,USART1 Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " USART0 ,USART0 Clock Mask" "Masked,Not masked"
|
|
sif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x08 7. " TWIS1 ,TWIS1 Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
sif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x08 6. " TWIM1 ,TWIM1 Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " TWIS0 ,TWIS0 Clock Mask" "Masked,Not masked"
|
|
else
|
|
bitfld.long 0x08 5. " TWIS0 ,TWIS0 Clock Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 4. " TWIM0 ,TWIM0 Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " TC1 ,TC1 Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TC0 ,TC0 Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " SPI ,SPI Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " IISC ,IISC Clock Mask" "Masked,Not masked"
|
|
line.long 0x0C "PBBMASK,PBB Clock Mask"
|
|
bitfld.long 0x0C 6. " PEVC ,PEVC Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " USBC ,USBC Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CRCCU ,CRCCU Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " PDCA ,PDCA Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " HMATRIX ,HMATRIX Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " HRAMC1 ,HRAMC1 Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " FLASHCALW ,FLASHCALW Clock Mask" "Masked,Not masked"
|
|
line.long 0x10 "PBCMASK,PBC Clock Mask"
|
|
bitfld.long 0x10 4. " GPIO ,GPIO Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x10 3. " FREQM ,FREQM Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SCIF ,SCIF Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x10 1. " CHIPID ,CHIPID Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PM ,PM Clock Mask" "Masked,Not masked"
|
|
line.long 0x14 "PBDMASK,PBD Clock Mask"
|
|
bitfld.long 0x14 5. " PICOUART ,PICOUART Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x14 4. " EIC ,EIC Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x14 3. " WDT ,WDT Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x14 2. " AST ,AST Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BSCIF ,BSCIF Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x14 0. " BPM ,BPM Clock Mask" "Masked,Not masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PBADIVMASK,Divided Clock Mask"
|
|
bitfld.long 0x00 6. " MASK[6] ,TIMER_CLOCK5 Divided Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " MASK[4] ,TIMER_CLOCK4 Divided Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASK[2] ,TIMER_CLOCK3 - CLK_USART/DIV Divided Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " MASK[0] ,TIMER_CLOCK2 Divided Clock Mask" "Masked,Not masked"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFDCTRL,Clock Failure Detector Control Register"
|
|
bitfld.long 0x00 31. " SFV ,Store Final Value" "Read/write,Read-only"
|
|
bitfld.long 0x00 0. " CFDEN ,Clock Failure Detection Enable" "Disabled,Enabled"
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "UNLOCK,PM Unlock Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Unlock Key"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR ,Unlock Address"
|
|
group.long 0xc8++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " AE_set/clr ,Access Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " WAKE_set/clr ,Wake up Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " CKRDY_set/clr ,Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CFD_set/clr ,Clock Failure Detected Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0xcc++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "Cleared,Pending"
|
|
bitfld.long 0x00 8. " WAKE ,Wake up" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CKRDY ,Clock Ready" "Cleared,Pending"
|
|
bitfld.long 0x00 0. " CFD ,Clock Failure Detected" "Cleared,Pending"
|
|
wgroup.long 0xd0++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "No effect,Clear"
|
|
bitfld.long 0x00 8. " WAKE ,Wake up" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CKRDY ,Clock Ready" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CFD ,Clock Failure Detected" "No effect,Clear"
|
|
rgroup.long 0xd4++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "No error,Error"
|
|
bitfld.long 0x00 8. " WAKE ,Wake up event flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CKRDY ,Clock Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " CFD ,Clock Failure Detected" "No failure,Failure"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "PPCR,Peripheral Power Control Register"
|
|
hexmask.long 0x00 11.--31. 1. " PPC ,Peripheral Power Control Register"
|
|
bitfld.long 0x00 10. " FWBOD18 ,Flash Wait BOD18" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FWBGREF ,Flash Wait BGREF" "Yes,No"
|
|
bitfld.long 0x00 8. " VREGRCMASK ,VREG Request Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADCIFERCMASK ,ADCIFE Request Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " PEVCRCMASK ,PEVC Request Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TWIS1RCMASK ,TWIS1 Request Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TWIS0RCMASK ,TWIS0 Request Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASTRCMASK ,AST Request Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " ACIFCRCMASK ,ACIFC Request Clock Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CATBRCMASK ,CAT Request Clock Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RSTPUN ,Reset Pullup" "Disabled,Enabled"
|
|
rgroup.long 0x180++0x07
|
|
line.long 0x00 "RCAUSE,Reset Cause"
|
|
bitfld.long 0x00 13. " BOD33 ,Brown-out 3.3V Reset" "No reset,Reset"
|
|
bitfld.long 0x00 10. " POR33 ,Power-on Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OCDRST ,OCD Reset" "No reset,Reset"
|
|
bitfld.long 0x00 6. " BKUP ,Backup reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WDT ,Watchdog Reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EXT ,External Reset Pin" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOD ,Brown-out Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " POR ,Power-on Reset" "No reset,Reset"
|
|
line.long 0x04 "WCAUSE,Wake Cause Register"
|
|
bitfld.long 0x04 17. " AST ,AST Wake Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x04 16. " EIC ,EIC Wake Cause" "No wakeup,Wakeup"
|
|
textline " "
|
|
sif cpuis("ATSAM4LC*")
|
|
bitfld.long 0x04 7. " LCDCA ,LCDCA Wake Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x04 6. " PICOUART ,PICOUART Wake Cause" "No wakeup,Wakeup"
|
|
else
|
|
bitfld.long 0x04 6. " PICOUART ,PICOUART Wake Cause" "No wakeup,Wakeup"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " BOD33_IRQ ,BOD33 IRQ Wake Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x04 4. " BOD18_IRQ ,BOD18 IRQ Wake Cause" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PSOK ,PSOK Wake Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x04 2. " USBC ,USBC Wake Cause" "No wakeup,Wakeup"
|
|
textline " "
|
|
sif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x04 1. " TWI_Slave_1 ,TWI Slave 1 Wake Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x04 0. " TWI_Slave_0 ,TWI Slave 0 Wake Cause" "No wakeup,Wakeup"
|
|
else
|
|
bitfld.long 0x04 0. " TWI_Slave_0 ,TWI Slave 0 Wake Cause" "No wakeup,Wakeup"
|
|
endif
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "AWEN,Asynchronous Wake Up Enable Register"
|
|
sif cpuis("ATSAM4LC*")
|
|
bitfld.long 0x00 7. " LCDCA ,LCDCA Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 6. " PICOUART ,PICOUART Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
else
|
|
bitfld.long 0x00 6. " PICOUART ,PICOUART Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " BOD33_IRQ ,BOD33 IRQ Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 4. " BOD18_IRQ ,BOD18 IRQ Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PSOK ,PSOK Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " USBC ,USBC Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
textline " "
|
|
sif !cpuis("ATSAM4LC*A")&&!cpuis("ATSAM4LS*A")
|
|
bitfld.long 0x00 1. " TWI_Slave_1 ,TWI Slave 1 Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 0. " TWI_Slave_0 ,TWI Slave 0 Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
else
|
|
bitfld.long 0x00 0. " TWI_Slave_0 ,TWI Slave 0 Asynchronous Wake Up" "No wakeup,Wakeup"
|
|
endif
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "FASTSLEEP,Fast Sleep Register"
|
|
bitfld.long 0x00 24. " DFLL ,DFLL" "Not set,Set"
|
|
bitfld.long 0x00 16.--20. " FASTRCOSC ,FASTRCOSC" ",RC80,RCFAST,,RC1M,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " PLL ,PLL" "Not set,Set"
|
|
bitfld.long 0x00 0. " OSC ,Oscillator" "Not set,Set"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
bitfld.long 0x00 7. " HSBPEVC ,HSB PEVC Clock Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 3. " PBD ,APBD Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBC ,APBC Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " PBB ,APBB Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PBA ,APBA Implemented" "Not implemented,Implemented"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version Number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BPM (Backup Power Manager)"
|
|
base ad:0x400F0000
|
|
width 0x0C
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " AE_set/clr ,Access Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " PSOK_set/clr ,Power Scaling OK Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "Cleared,Pending"
|
|
bitfld.long 0x00 0. " PSOK ,Power Scaling OK" "Cleared,Pending"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PSOK ,Power Scaling OK" "No effect,Clear"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 31. " AE , Access Error" "No error,Error"
|
|
bitfld.long 0x00 0. " PSOK ,Power Scaling OK" "Not ready,Ready"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "UNLOCK,Unlock Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Unlock Key"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR ,Unlock Address"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PMCON,Power Mode Control Register"
|
|
bitfld.long 0x00 24. " FASTWKUP ,Fast Wakeup mode" "Normal,Fast"
|
|
bitfld.long 0x00 16. " CK32S ,32kHz-1kHz Clock Source Selection" "OSC32K,RC32K"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SLEEP ,SLEEP mode Configuration" "CPU clock stopped,CPU/AHB clocks stopped,CPU/AHB/PB/GCLK clocks stopped,CPU/AHB/PB/GCLK/clock sources"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RET ,RETENTION Mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BKUP ,BACKUP Mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PSCREQ ,Power Scaling Change Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0.--1. " PS ,Power Scaling Configuration Value" "0,1,2,3"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "BKUPWCAUSE,Backup Wake up Cause Register"
|
|
bitfld.long 0x00 5. " PICOUART ,PICOUART Backup Wake up Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 4. " BOD18 ,BOD18 Backup Wake up Cause" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BOD33 ,BOD33 Backup Wake up Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " WDT ,WDT Backup Wake up Cause" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AST ,AST Backup Wake up Cause" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 0. " EIC ,EIC Backup Wake up Cause" "No wakeup,Wakeup"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "BKUPWEN,Backup Wake up Enable Register"
|
|
bitfld.long 0x00 5. " PICOUARTEN ,PICOUARTEN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 4. " BOD18EN ,BOD18EN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BOD33EN ,BOD33EN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " WDTEN ,WDTEN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASTEN ,ASTEN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 0. " EICEN ,EICEN Backup Wake up Enable" "No wakeup,Wakeup"
|
|
line.long 0x04 "BKUPPMUX,Backup Pin Muxing Register"
|
|
bitfld.long 0x04 8. " PC06 ,EIC[8] Alternate function" "Not selected,Selected"
|
|
bitfld.long 0x04 7. " PC05 ,EIC[7] Alternate function" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PC04 ,EIC[6] Alternate function" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " PC03 ,EIC[5] Alternate function" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PA07 ,EIC[4] Alternate function" "Not selected,Selected"
|
|
bitfld.long 0x04 3. " PA05 ,EIC[3] Alternate function" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PA04 ,EIC[2] Alternate function" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " PA06 ,EIC[1] Alternate function" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PB01 ,EIC[0] Alternate function" "Not selected,Selected"
|
|
line.long 0x08 "IORET,Input Output Retention Register"
|
|
bitfld.long 0x08 0. " RET ,Retention on I/O lines after waking up from the BACKUP mode" "Not held,Held"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version Number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BSCIF (Backup System Control Interface)"
|
|
base ad:0x400F0400
|
|
width 0x11
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " AE_set/clr ,Access Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " LPBGRDY_set/clr ,Low Power Bandgap Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " VREGOK_set/clr ,Voltage regulator OK Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " SSWRDY_set/clr ,Buck voltage regulator has stopped switching Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " BOD18SYNRDY_set/clr ,BOD18 synchronization Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " BOD33SYNRDY_set/clr ,BOD33 synchronization Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " BOD18DET_set/clr ,BOD18 event detected Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " BOD33DET_set/clr ,BOD33 event detected Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " RC32SAT_set/clr ,RC32K autocalibration saturation mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " RC32KREFE_set/clr ,RC32K reference frequency mode Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RC32KLOCK_set/clr ,RC32K lock mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " RC32KRDY_set/clr ,RC32K read/write mode Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " OSC32RDY_set/clr ,OSC32 Ready Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "Cleared,Pending"
|
|
bitfld.long 0x00 12. " LPBGRDY ,Low Power Bandgap Ready" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VREGOK ,Voltage regulator OK" "Cleared,Pending"
|
|
bitfld.long 0x00 9. " SSWRDY ,Buck voltage regulator has stopped switching" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BOD18SYNRDY ,BOD18 synchronization Ready" "Cleared,Pending"
|
|
bitfld.long 0x00 7. " BOD33SYNRDY ,BOD33 synchronization Ready" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BOD18DET ,BOD18 event detected" "Cleared,Pending"
|
|
bitfld.long 0x00 5. " BOD33DET ,BOD33 event detected" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RC32SAT ,RC32K autocalibration saturation mode" "Cleared,Pending"
|
|
bitfld.long 0x00 3. " RC32KREFE ,RC32K reference frequency mode" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RC32KLOCK ,RC32K lock mode" "Cleared,Pending"
|
|
bitfld.long 0x00 1. " RC32KRDY ,RC32K read/write mode" "Cleared,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OSC32RDY ,OSC32 Ready" "Cleared,Pending"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "No effect,Clear"
|
|
bitfld.long 0x00 12. " LPBGRDY ,Low Power Bandgap Ready" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VREGOK ,Voltage regulator OK" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SSWRDY ,Buck voltage regulator has stopped switching" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BOD18SYNRDY ,BOD18 synchronization Ready" "No effect,Clear"
|
|
bitfld.long 0x00 7. " BOD33SYNRDY ,BOD33 synchronization Ready" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BOD18DET ,BOD18 event detected" "No effect,Clear"
|
|
bitfld.long 0x00 5. " BOD33DET ,BOD33 event detected" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RC32SAT ,RC32K autocalibration saturation mode" "No effect,Clear"
|
|
bitfld.long 0x00 3. " RC32KREFE ,RC32K reference frequency mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RC32KLOCK ,RC32K lock mode" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RC32KRDY ,RC32K read/write mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OSC32RDY ,OSC32 Ready" "No effect,Clear"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PCLKSR,Power and Clocks Status Register"
|
|
bitfld.long 0x00 12. " LPBGRDY ,Low Power Bandgap Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " RC1MRDY ,RC1M oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VREGOK ,Voltage regulator OK" "0,1"
|
|
bitfld.long 0x00 9. " SSWRDY ,Buck voltage regulator has stopped switching" "Not requested to stop switching,Stopped switching"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BOD18SYNRDY ,BOD18 synchronization Ready" "Not ongoing,Ongoing"
|
|
bitfld.long 0x00 7. " BOD33SYNRDY ,BOD33 synchronization Ready" "Not ongoing,Ongoing"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BOD18DET ,BOD18 event detected" "No,Yes"
|
|
bitfld.long 0x00 5. " BOD33DET ,BOD33 event detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RC32SAT ,RC32K autocalibration saturation mode" "No saturation,Saturation"
|
|
bitfld.long 0x00 3. " RC32KREFE ,RC32K reference frequency mode" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RC32KLOCK ,RC32K lock mode" "Not obtained,Obtained"
|
|
bitfld.long 0x00 1. " RC32KRDY ,RC32K read/write mode" "Writes not completed,Writes comitted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OSC32RDY ,OSC32 Ready" "Not ready,Ready"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "UNLOCK,Unlock Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Unlock Key"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR ,Unlock Address"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "OSCCTRL32,32KHz Oscillator Control Register"
|
|
bitfld.long 0x00 16.--18. " STARTUP ,Oscillator Start-up Time" "0,1.1 ms,72.3 ms,143 ms,570 ms,1.1 s,2.3 s,4.6 s"
|
|
bitfld.long 0x00 12.--15. " SELCURR ,Current Selection" "50,75,100,125,150,175,200,225,250,275,300,325,350,375,400,425"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MODE ,Oscillator Mode" "No crystal,Crystal mode,,Crystal mode with amplitude controlled mode,Crystal and high current mode,Crystal with high current mode & amplitude controlled mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN1K ,1 KHz output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN32K ,32 KHz output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OSC32EN ,32 KHz Oscillator Enable" "Disabled,Enabled"
|
|
line.long 0x04 "RC32KCR,32 KHz RC Oscillator Control Register"
|
|
bitfld.long 0x04 7. " FCD ,Flash calibration done" "Not loaded,Loaded"
|
|
bitfld.long 0x04 5. " REF ,Reference select" "OSC32K,Generic clock"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MODE ,Mode Selection" "Open Loop,Closed Loop"
|
|
bitfld.long 0x04 3. " EN1K ,Enable 1 kHz output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN32K ,Enable 32 KHz output" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TCEN ,Temperature Compensation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,Enable as Generic clock source" "Not enabled,Enabled"
|
|
line.long 0x08 "RC32KTUNE,RC32K Tuning Register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " COARSE ,Coarse Value"
|
|
hexmask.long.byte 0x08 0.--5. 1. " FINE ,Fine value"
|
|
line.long 0x0C "BOD33CTRL,BOD33 Control Register"
|
|
bitfld.long 0x0c 31. " SFV ,BOD Control Register Store Final Value" "Not locked,Locked"
|
|
bitfld.long 0x0c 30. " FCD ,BOD Fuse Calibration Done" "Redone,Not to be redone"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " MODE ,Operation modes" "Continuous,Sampling"
|
|
bitfld.long 0x0c 8.--9. " ACTION ,Action mode" "No Action,Reset,Interrupt,No Action"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " HYST ,BOD Hysteresis" "No hysteresis,Hysteresis"
|
|
bitfld.long 0x0c 0. " EN ,BOD Enable" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BOD18CTRL,BOD18 Control Register"
|
|
bitfld.long 0x00 31. " SFV ,BOD Control Register Store Final Value" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " FCD ,BOD Fuse Calibration Done" "Redone,Not to be redone"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MODE ,Operation modes" "Continuous,Sampling"
|
|
bitfld.long 0x00 8.--9. " ACTION ,Action mode" "No Action,Reset,Interrupt,No Action"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HYST ,BOD Hysteresis" "No hysteresis,Hysteresis"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BOD33SAMPLING,BOD33 Sampling Control Register"
|
|
bitfld.long 0x00 8.--11. " PSEL ,Prescaler Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " CSSEL ,Clock Source Select" "RCSYS,32kHz clock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CEN ,Clock Enable" "Disabled/stopped-Enabled/not stable,Enabled/stable-Disabled/not stopped"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BOD18SAMPLING,BOD18 Sampling Control Register"
|
|
bitfld.long 0x00 8.--11. " PSEL ,Prescaler Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " CSSEL ,Clock Source Select" "RCSYS,32kHz clock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CEN ,Clock Enable" "Disabled/stopped-Enabled/not stable,Enabled/stable-Disabled/not stopped"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BOD33LEVEL,BOD33 Level Register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,BOD Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BOD18LEVEL,BOD18 Level Register"
|
|
bitfld.long 0x00 31. " RANGE ,BOD Threshold Range" "Standard,Low"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VAL ,BOD Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "VREGCR,Voltage Regulator Configuration Register"
|
|
bitfld.long 0x00 31. " SFV ,Store Final Value" "Read/write,Read-only"
|
|
bitfld.long 0x00 10. " SSWEVT ,Stop Switching On Event Enable" "Not controlled,Controlled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSW ,Stop Switching" "Not forced,Forced"
|
|
bitfld.long 0x00 8. " SSG ,Spread Spectrum Generator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIS ,Voltage Regulator disable" "No,Yes"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RC1MCR,1MHz RC Clock Configuration Register"
|
|
bitfld.long 0x00 8.--12. " CLKCAL ,1MHz RC Osc Calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " FCD ,Flash Calibration Done" "Redone,Only after a power-on reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKOEN ,1MHz RC Osc Clock Output Enable" "Disabled,Enabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BGCTRL,Bandgap Control Register"
|
|
bitfld.long 0x00 8. " TSEN ,Temperature Sensor Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " ADCISEL ,ADC Input Selection" "No connection,,Voltage reference,?..."
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "BGSR,Bandgap Status Register"
|
|
bitfld.long 0x00 18.--19. " VREF ,Voltage Reference Used by the System" "Both,Bandgap,Low Power Bandgap,Neither Bandgap nor LPBandgap"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LPBGRDY ,Low Power Bandgap Voltage Reference Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BGRDY ,Bandgap Voltage Reference Ready" "Not ready,Ready"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BGBUFRDY ,Bandgap Buffer Ready"
|
|
group.long 0x78++0x0F
|
|
line.long 0x0 "BR0,Backup Register 0"
|
|
line.long 0x4 "BR1,Backup Register 1"
|
|
line.long 0x8 "BR2,Backup Register 2"
|
|
line.long 0xC "BR3,Backup Register 3"
|
|
rgroup.long 0x3E4++0x1B
|
|
line.long 0x00 "BRIFBVERSION,Backup Register Interface Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x04 "BGREFIFBVERSION,Bandgap Reference Interface Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x08 "VREGIFGVERSION,Voltage Regulator Version Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x0c "BODIFCVERSION,Brown-Out Detector Version Register"
|
|
hexmask.long.word 0x0c 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x10 "RC32KIFBVERSION,32kHz RC Oscillator Version Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x14 "OSC32IFAVERSION,32KHz Oscillator Version Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x18 "VERSION,BSCIF Version Register"
|
|
hexmask.long.word 0x18 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCIF (System Control Interface)"
|
|
base ad:0x400E0800
|
|
width 0x12
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " AE_set/clr ,Access Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " RCFASTLOCKLOST_set/clr ,RCFAST lock lost value Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " RCFASTLOCK_set/clr ,RCFAST Locked on Accurate value Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PLLLOCKLOST0_set/clr ,PLL0 lock lost value Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " PLLLOCK0_set/clr ,PLL0 Locked on Accurate value Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 4. -0x8 4. -0x4 4. " DFLL0RCS_set/clr ,DFLL0 Reference Clock Stopped Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " DFLL0RDY_set/clr ,DFLL0 Synchronization Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " DFLL0LOCKF_set/clr ,DFLL0 Locked on Fine Value Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DFLL0LOCKC_set/clr ,DFLL0 Locked on Coarse Value Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 0. -0x8 0. -0x4 0. " OSC0RDY_set/clr ,OSC0 Ready Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " AE ,Access Error" "Cleared,Pending"
|
|
bitfld.long 0x00 14. " RCFASTLOCKLOST ,RCFAST lock lost value" "Cleared,Pending"
|
|
textline " "
|
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bitfld.long 0x00 13. " RCFASTLOCK ,RCFAST Locked on Accurate value" "Cleared,Pending"
|
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bitfld.long 0x00 7. " PLLLOCKLOST0 ,PLL0 lock lost value" "Cleared,Pending"
|
|
textline " "
|
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bitfld.long 0x00 6. " PLLLOCK0 ,PLL0 Locked on Accurate value" "Cleared,Pending"
|
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textline " "
|
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bitfld.long 0x00 4. " DFLL0RCS ,DFLL0 Reference Clock Stopped" "Cleared,Pending"
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bitfld.long 0x00 3. " DFLL0RDY ,DFLL0 Synchronization Ready" "Cleared,Pending"
|
|
textline " "
|
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bitfld.long 0x00 2. " DFLL0LOCKF ,DFLL0 Locked on Fine Value" "Cleared,Pending"
|
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bitfld.long 0x00 1. " DFLL0LOCKC ,DFLL0 Locked on Coarse Value" "Cleared,Pending"
|
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textline " "
|
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bitfld.long 0x00 0. " OSC0RDY ,OSC0 Ready" "Cleared,Pending"
|
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wgroup.long 0x10++0x03
|
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line.long 0x00 "ICR,Interrupt Clear Register"
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bitfld.long 0x00 31. " AE ,Access Error" "No effect,Clear"
|
|
bitfld.long 0x00 14. " RCFASTLOCKLOST ,RCFAST lock lost value" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x00 13. " RCFASTLOCK ,RCFAST Locked on Accurate value" "No effect,Clear"
|
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bitfld.long 0x00 7. " PLLLOCKLOST0 ,PLL0 lock lost value" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x00 6. " PLLLOCK0 ,PLL0 Locked on Accurate value" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x00 4. " DFLL0RCS ,DFLL0 Reference Clock Stopped" "No effect,Clear"
|
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bitfld.long 0x00 3. " DFLL0RDY ,DFLL0 Synchronization Ready" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x00 2. " DFLL0LOCKF ,DFLL0 Locked on Fine Value" "No effect,Clear"
|
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bitfld.long 0x00 1. " DFLL0LOCKC ,DFLL0 Locked on Coarse Value" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x00 0. " OSC0RDY ,OSC0 Ready" "No effect,Clear"
|
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rgroup.long 0x14++0x03
|
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line.long 0x00 "PCLKSR,Power and Clocks Status Register"
|
|
bitfld.long 0x00 14. " RCFASTLOCKLOST ,RCFAST lock lost value" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " RCFASTLOCK ,RCFAST Locked on Accurate value" "Not locked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 7. " PLLLOCKLOST0 ,PLL0 lock lost value" "Not lost,Lost"
|
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bitfld.long 0x00 6. " PLLLOCK0 ,PLL0 Locked on Accurate value" "Unlocked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 4. " DFLL0RCS ,DFLL0 Reference Clock Stopped" "Running,Stopped"
|
|
textline " "
|
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bitfld.long 0x00 3. " DFLL0RDY ,DFLL0 Synchronization Ready" "Invalid,Valid"
|
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bitfld.long 0x00 2. " DFLL0LOCKF ,DFLL0 Locked on Fine Value" "Unlocked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 1. " DFLL0LOCKC ,DFLL0 Locked on Coarse Value" "Unlocked,Locked"
|
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bitfld.long 0x00 0. " OSC0RDY ,OSC0 Ready" "Not enabled/Not ready,Stable/Ready"
|
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wgroup.long 0x18++0x03
|
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line.long 0x00 "UNLOCK,Unlock Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Unlock Key"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR ,Unlock Address"
|
|
group.long 0x20++0x1B
|
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line.long 0x00 "OSCCTRL0,Oscillator Control Register"
|
|
bitfld.long 0x00 16. " OSCEN ,Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " STARTUP ,Oscillator Start-up Time" "0,557 us,1.1 ms,18 ms,36 ms,71 ms,143 ms,285 ms,35 us,70 us,139 us,278 us,2.2 ms,4.5 ms,8.9 ms,285 ms"
|
|
textline " "
|
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bitfld.long 0x00 3. " AGC ,Automatic Gain Control" "0,1"
|
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bitfld.long 0x00 1.--2. " GAIN ,Select the gain for the oscillator" "G0 (0.45 MHz - 12.0 MHz),G1 (12.0 MHz - 16.0 MHz),G2 (16.0 MHz),G3 (16.0 MHz)"
|
|
textline " "
|
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bitfld.long 0x00 0. " MODE ,Oscillator Mode" "No crystal,Crystal"
|
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line.long 0x04 "PLL0,PLL0 Control Register"
|
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hexmask.long.byte 0x04 24.--29. 1. " PLLCOUNT ,PLL Count"
|
|
bitfld.long 0x04 16.--19. " PLLMU ,PLL Multiply Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
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bitfld.long 0x04 8.--11. " PLLDIV ,PLL Division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 5. " PLLOPT[2] ,Wide-Bandwidth mode" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PLLOPT[1] ,Divides the output frequency by 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PLLOPT[0] ,The VCO frequency range" "80MHz<fvco<180MHz,160MHz<fvco<240MHz"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " PLLOSC ,PLL Oscillator Select" "OSC0,GCLK9,?..."
|
|
bitfld.long 0x04 0. " PLLEN ,PLL Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DFLL0CONF,DFLL0 Configuration Register"
|
|
bitfld.long 0x08 24.--27. " CALIB ,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 23. " FCD ,Fuse Calibration Done" "Any reset,Power-on reset"
|
|
textline " "
|
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bitfld.long 0x08 16.--17. " RANGE ,Range Value" "96-220,50-110,25-55,20-30"
|
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bitfld.long 0x08 6. " QLDIS ,Quick Lock Disable" "No,Yes"
|
|
textline " "
|
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bitfld.long 0x08 5. " CCDIS ,Chill Cycle Disable" "No,Yes"
|
|
bitfld.long 0x08 3. " LLAW ,Lose Lock After Wake" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x08 2. " STABLE ,Stable DFLL Frequency" "Tracks changed in output frequency,Register value fixed after fine lock"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MODE ,Mode Selection" "Open Loop,Closed Loop"
|
|
bitfld.long 0x08 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x0c "DFLL0VAL,DFLL0 Value Register"
|
|
bitfld.long 0x0c 16.--20. " COARSE ,Coarse Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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hexmask.long.byte 0x0c 0.--7. 1. " FINE ,Fine value"
|
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line.long 0x10 "DFLL0MUL,DFLL0 Multiplier Register"
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hexmask.long.word 0x10 0.--15. 1. " MUL ,DFLL Multiply Factor"
|
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line.long 0x14 "DFLL0STEP,DFLL0 Maximum Step Register"
|
|
bitfld.long 0x14 16.--20. " CSTEP ,Coarse Maximum Step" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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hexmask.long.byte 0x14 0.--7. 1. " FSTEP ,Fine Maximum Step"
|
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line.long 0x18 "DFLL0SSG,DFLL0 Spread Spectrum Generator Control Register"
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bitfld.long 0x18 16.--20. " STEPSIZE ,SSG Step Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--12. " AMPLITUDE ,SSG Amplitude" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x18 1. " PRBS ,Pseudo Random Bit Sequence" "Constant intervals,Pseudo-random intervals"
|
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textline " "
|
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bitfld.long 0x18 0. " EN ,SSG Enable" "Disabeled,Enabled"
|
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rgroup.long 0x3C++0x03
|
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line.long 0x00 "DFLL0RATIO,DFLL0 Ratio Register"
|
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hexmask.long.word 0x00 0.--15. 1. " RATIODIFF ,Multiplication Ratio Difference"
|
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wgroup.long 0x40++0x03
|
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line.long 0x00 "DFLL0SYNC,DFLL0 Synchronization Register"
|
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bitfld.long 0x00 0. " SYNC ,Synchronization" "Disabled,Enabled"
|
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group.long 0x44++0x07
|
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line.long 0x00 "RCCR,System RC Oscillator Calibration Register"
|
|
bitfld.long 0x00 16. " FCD ,Flash Calibration Done" "Any reset,Power-on Reset"
|
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hexmask.long.word 0x00 0.--9. 1. " CALIB ,Calibration Value"
|
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line.long 0x04 "RCFASTCFG,4/8/12 MHz RC Oscillator Configuration Register"
|
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hexmask.long.byte 0x04 16.--22. 1. " CALIB ,Oscillator Calibration Value"
|
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bitfld.long 0x04 12.--15. " LOCKMARGIN ,Accepted Count Error for Lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
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bitfld.long 0x04 8.--9. " FRANGE ,Frequency Range" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x04 7. " FCD ,RCFAST Fuse Calibration Done" "Not loaded,Loaded"
|
|
textline " "
|
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bitfld.long 0x04 4.--6. " NBPERIOD ,Number of 32kHz Periods" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 2. " JITMODE ,Jitter Mode" "RCFASTLOCKLOST,Continuously updated"
|
|
textline " "
|
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bitfld.long 0x04 1. " TUNEEN ,Tuner Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EN ,Oscillator Enable" "Disabled,Enabled"
|
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rgroup.long 0x4c++0x03
|
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line.long 0x00 "RCFASTSR,4/8/12 MHz RC Oscillator Status Register"
|
|
bitfld.long 0x00 31. " UPDATED ,Current Trim Value Updated" "No,Yes"
|
|
bitfld.long 0x00 25. " LOCKLOST ,Lock Lost" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " LOCK ,Lock" "No,Yes"
|
|
bitfld.long 0x00 21. " SIGN ,Sign of Current Count Error" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CNTERR ,Current Count Error" "0,1,?..."
|
|
hexmask.long.byte 0x00 0.--6. 1. " CURTRIM ,Current Trim Value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RC80MCR,80MHz RC Oscillator Control Register"
|
|
bitfld.long 0x00 16.--17. " CALIB ,Calibration Value" "0,1,2,3"
|
|
bitfld.long 0x00 7. " FCD ,Flash Calibration Done" "Any reset,Power-on Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Oscillator Enable" "Disabled,Enabled"
|
|
group.long 0x64++0x17
|
|
line.long 0x00 "HRPCR,High Resolution Prescaler Control Register"
|
|
hexmask.long 0x00 8.--31. 1. " HRCOUNT ,High Resolution Counter"
|
|
bitfld.long 0x00 1.--3. " CKSEL ,Clock input selection" "OSC0,PLL0,DFLL0,,RC80M,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " HRPEN ,High Resolution Prescaler Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FPCR,Fractional Prescaler Control Register"
|
|
bitfld.long 0x04 1.--3. " CKSEL ,Clock input selection" "OSC0,PLL0,DFLL0,,RC80M,?..."
|
|
bitfld.long 0x04 0. " FPEN ,High Resolution Prescaler Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FPMUL,Fractional Prescaler Mul Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " FPMUL ,Fractional Prescaler Multiplication Factor"
|
|
line.long 0x0c "FPDIV,Fractional Prescaler Div Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " FPDIV ,Fractional Prescaler Division Factor"
|
|
group.long 0x74++0x2F
|
|
line.long 0x0 "GCCTRL0,Generic Clock Control0"
|
|
hexmask.long.word 0x0 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x0 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x0 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x4 "GCCTRL1,Generic Clock Control1"
|
|
hexmask.long.word 0x4 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x4 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x4 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x8 "GCCTRL2,Generic Clock Control2"
|
|
hexmask.long.word 0x8 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x8 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x8 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0xC "GCCTRL3,Generic Clock Control3"
|
|
hexmask.long.word 0xC 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0xC 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0xC 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GCCTRL4,Generic Clock Control4"
|
|
hexmask.long.word 0x10 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x10 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x14 "GCCTRL5,Generic Clock Control5"
|
|
hexmask.long.word 0x14 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x14 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x14 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x18 "GCCTRL6,Generic Clock Control6"
|
|
hexmask.long.word 0x18 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x18 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x18 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x1C "GCCTRL7,Generic Clock Control7"
|
|
hexmask.long.word 0x1C 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x1C 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x20 "GCCTRL8,Generic Clock Control8"
|
|
hexmask.long.word 0x20 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x20 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x20 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x24 "GCCTRL9,Generic Clock Control9"
|
|
hexmask.long.word 0x24 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x24 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x24 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x28 "GCCTRL10,Generic Clock Control10"
|
|
hexmask.long.word 0x28 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x28 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x28 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x2C "GCCTRL11,Generic Clock Control11"
|
|
hexmask.long.word 0x2C 16.--31. 1. " DIV ,Division Factor"
|
|
bitfld.long 0x2C 8.--12. " OSCSEL ,Oscillator Select" "RCSYS,OSC32K,DFLL0,OSC0,RC80M,RCFAST,RC1M,CLK_CPU,CLK_HSB,CLK_PBA,CLK_PBB,CLK_PBC,CLK_PBD,RC32K,,CLK_1K,PLL0,GCLK_PLL0,HRP,FP,GCLK_IN[0-1],GCLK11,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 1. " DIVEN ,Divide Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
rgroup.long 0x3d8++0x17
|
|
line.long 0x00 "RCFASTVERSION,4/8/12 MHz RC Oscillator Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x04 "GCLKPRESCVERSION,Generic Clock Prescalers Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x08 "PLLIFAVERSION,PLL Version Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x0c "OSCIFAVERSION,Oscillator 0 Version Register"
|
|
hexmask.long.word 0x0c 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x10 "DFLLIFBVERSION,Digital Frequency Locked Loop Version Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x14 "RCOSCIFAVERSION,RC Oscillator Version Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " VERSION ,Version number"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x00 "RC80MVERSION,80MHz RC Oscillator Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x04 "GCLKIFVERSION,Generic Clock Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x08 "VERSION,SCIF Version Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FLASHCALW (Flash Controller)"
|
|
base ad:0x400A0000
|
|
width 0x09
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FCR,Flash Control Register"
|
|
bitfld.long 0x00 7. " WS1OPT ,Wait State 1 Optimization" "No action,Enabled"
|
|
bitfld.long 0x00 6. " FWS ,Flash Wait State" "0 wait states,1 wait state"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ECCE ,ECC Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PROGE ,Programming Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOCKE ,Lock Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRDY ,Flash Ready Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FCMD,Flash Command Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Write protection key"
|
|
hexmask.long.word 0x04 8.--23. 1. " PAGEN ,Page number"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " CMD ,Command" "No operation,Write Page,Erase Page,Clear Page Buffer,Lock region containing given Page,Unlock region containing given Page,Erase All,Write General-Purpose Fuse Bit,Erase General-Purpose Fuse Bit,Set Security Fuses,Program GP Fuse Byte,Erase All GPFuses,Quick Page Read,Write User Page,Erase User Page,Quick Page Read User Page,High Speed Mode Enable,High Speed Mode Disable,?..."
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "FSR,Flash Status Register"
|
|
in
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "FPR,Flash Parameter Register"
|
|
bitfld.long 0x00 8.--10. " PSZ ,Page Size" "32 Byte,64 Byte,128 Byte,256 Byte,512 Byte,1024 Byte,2048 Byte,4096 Byte"
|
|
bitfld.long 0x00 0.--3. " FSZ ,Flash Size" "4-KB,8-KB,16-KB,32-KB,48-KB,64-KB,96-KB,128-KB,192-KB,256-KB,384-KB,512-KB,768-KB,1024-KB,2048-KB,?..."
|
|
line.long 0x04 "FVR,Flash Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x08 "FGPFRHI,Flash General Purpose Fuse Register High"
|
|
bitfld.long 0x08 31. " GPF63 ,General Purpose Fuse 63" "Written/programmed,Erased"
|
|
bitfld.long 0x08 30. " GPF62 ,General Purpose Fuse 62" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 29. " GPF61 ,General Purpose Fuse 61" "Written/programmed,Erased"
|
|
bitfld.long 0x08 28. " GPF60 ,General Purpose Fuse 60" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 27. " GPF59 ,General Purpose Fuse 59" "Written/programmed,Erased"
|
|
bitfld.long 0x08 26. " GPF58 ,General Purpose Fuse 58" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 25. " GPF57 ,General Purpose Fuse 57" "Written/programmed,Erased"
|
|
bitfld.long 0x08 24. " GPF56 ,General Purpose Fuse 56" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 23. " GPF55 ,General Purpose Fuse 55" "Written/programmed,Erased"
|
|
bitfld.long 0x08 22. " GPF54 ,General Purpose Fuse 54" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 21. " GPF53 ,General Purpose Fuse 53" "Written/programmed,Erased"
|
|
bitfld.long 0x08 20. " GPF52 ,General Purpose Fuse 52" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 19. " GPF51 ,General Purpose Fuse 51" "Written/programmed,Erased"
|
|
bitfld.long 0x08 18. " GPF50 ,General Purpose Fuse 50" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 17. " GPF49 ,General Purpose Fuse 49" "Written/programmed,Erased"
|
|
bitfld.long 0x08 16. " GPF48 ,General Purpose Fuse 48" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 15. " GPF47 ,General Purpose Fuse 47" "Written/programmed,Erased"
|
|
bitfld.long 0x08 14. " GPF46 ,General Purpose Fuse 46" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 13. " GPF45 ,General Purpose Fuse 45" "Written/programmed,Erased"
|
|
bitfld.long 0x08 12. " GPF44 ,General Purpose Fuse 44" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 11. " GPF43 ,General Purpose Fuse 43" "Written/programmed,Erased"
|
|
bitfld.long 0x08 10. " GPF42 ,General Purpose Fuse 42" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 9. " GPF41 ,General Purpose Fuse 41" "Written/programmed,Erased"
|
|
bitfld.long 0x08 8. " GPF40 ,General Purpose Fuse 40" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 7. " GPF39 ,General Purpose Fuse 39" "Written/programmed,Erased"
|
|
bitfld.long 0x08 6. " GPF38 ,General Purpose Fuse 38" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GPF37 ,General Purpose Fuse 37" "Written/programmed,Erased"
|
|
bitfld.long 0x08 4. " GPF36 ,General Purpose Fuse 36" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 3. " GPF35 ,General Purpose Fuse 35" "Written/programmed,Erased"
|
|
bitfld.long 0x08 2. " GPF34 ,General Purpose Fuse 34" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GPF33 ,General Purpose Fuse 33" "Written/programmed,Erased"
|
|
bitfld.long 0x08 0. " GPF32 ,General Purpose Fuse 32" "Written/programmed,Erased"
|
|
line.long 0x0C "FGPFRLO,Flash General Purpose Fuse Register Low"
|
|
bitfld.long 0x0C 31. " GPF31 ,General Purpose Fuse 31" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 30. " GPF30 ,General Purpose Fuse 30" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " GPF29 ,General Purpose Fuse 29" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 28. " GPF28 ,General Purpose Fuse 28" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " GPF27 ,General Purpose Fuse 27" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 26. " GPF26 ,General Purpose Fuse 26" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " GPF25 ,General Purpose Fuse 25" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 24. " GPF24 ,General Purpose Fuse 24" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " GPF23 ,General Purpose Fuse 23" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 22. " GPF22 ,General Purpose Fuse 22" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " GPF21 ,General Purpose Fuse 21" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 20. " GPF20 ,General Purpose Fuse 20" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " GPF19 ,General Purpose Fuse 19" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 18. " GPF18 ,General Purpose Fuse 18" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " GPF17 ,General Purpose Fuse 17" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 16. " GPF16 ,General Purpose Fuse 16" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " GPF15 ,General Purpose Fuse 15" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 14. " GPF14 ,General Purpose Fuse 14" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " GPF13 ,General Purpose Fuse 13" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 12. " GPF12 ,General Purpose Fuse 12" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " GPF11 ,General Purpose Fuse 11" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 10. " GPF10 ,General Purpose Fuse 10" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " GPF09 ,General Purpose Fuse 09" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 8. " GPF08 ,General Purpose Fuse 08" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " GPF07 ,General Purpose Fuse 07" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 6. " GPF06 ,General Purpose Fuse 06" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " GPF05 ,General Purpose Fuse 05" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 4. " GPF04 ,General Purpose Fuse 04" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " GPF03 ,General Purpose Fuse 03" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 2. " GPF02 ,General Purpose Fuse 02" "Written/programmed,Erased"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " GPF01 ,General Purpose Fuse 01" "Written/programmed,Erased"
|
|
bitfld.long 0x0C 0. " GPF00 ,General Purpose Fuse 00" "Written/programmed,Erased"
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "CTRL,PicoCache Control Register"
|
|
bitfld.long 0x00 0. " CEN ,Cache Enable" "Disabled,Enabled"
|
|
rgroup.long 0x40c++0x03
|
|
line.long 0x00 "SR,PicoCache Status Register"
|
|
bitfld.long 0x00 0. " CSTS ,Cache Controller Status" "Disabled,Enabled"
|
|
wgroup.long 0x420++0x07
|
|
line.long 0x00 "MAINT0,PicoCache Maintenance Register 0"
|
|
bitfld.long 0x00 0. " INVALL ,Cache Controller Invalidate All" "No effect,Invalidated"
|
|
line.long 0x04 "MAINT1,PicoCache Maintenance Register 1"
|
|
bitfld.long 0x04 4.--7. " INDEX ,Invalidate Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "MCFG,PicoCache Monitor Configuration Register"
|
|
bitfld.long 0x00 0.--1. " MODE ,Cache Controller Monitor Counter Mode" "Cycle counter,Instruction hit counter,Data hit counter,?..."
|
|
wgroup.long 0x42c++0x07
|
|
line.long 0x00 "MEN,PicoCache Monitor Enable Register"
|
|
bitfld.long 0x00 0. " MENABLE ,Monitor Enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCTRL,PicoCache Monitor Control Register"
|
|
bitfld.long 0x04 0. " SWRST ,Monitor Software Reset" "No effect,Reset"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "MSR,PicoCache Monitor Status Register"
|
|
rgroup.long 0x4fc++0x03
|
|
line.long 0x00 "PVR,PicoCache Version Register"
|
|
bitfld.long 0x00 16.--18. " MFN ,Mfn" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
group.long 0x7C7F60004++0x03
|
|
line.long 0x00 "FWUP,First Word of the User Page"
|
|
bitfld.long 0x00 20. " BOD18HYST ,1v8 Brown Out Detector Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " BOD18ACTION ,1v8 Brown Out Detector Action" "No action,Reset,Interrupt,No Action"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOD18EN ,1v8 Brown Out Detector Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 11.--16. 1. " BOD18LEVEL ,1v8 Brown Out Detector Level"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BOD33HYST ,3v3 Brown Out Detector Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " BOD33ACTION ,3v3 Brown Out Detector Action" "No Action,Reset,Interrupt,No Action"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BOD33EN ,3v3 Brown Out Detector Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 1.--6. 1. " BOD33LEVEL ,3v3 Brown Out Detector Level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WDTAUTO ,WatchDog Timer Auto Enable at Startup" "Automatically,Not automatically"
|
|
hgroup.long 0x40760000++0x03
|
|
hide.long 0x00 "SWUP,Second Word of the User Page"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "HMATRIX (HSB Bus Matrix)"
|
|
base ad:0x400A1000
|
|
width 0x08
|
|
group.long 0x00++0x3F
|
|
line.long 0x0 "MCFG0,Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x4 "MCFG1,Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x8 "MCFG2,Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0xC "MCFG3,Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x10 "MCFG4,Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x14 "MCFG5,Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x18 "MCFG6,Master Configuration Register 6"
|
|
bitfld.long 0x18 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x1C "MCFG7,Master Configuration Register 7"
|
|
bitfld.long 0x1C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x20 "MCFG8,Master Configuration Register 8"
|
|
bitfld.long 0x20 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x24 "MCFG9,Master Configuration Register 9"
|
|
bitfld.long 0x24 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x28 "MCFG10,Master Configuration Register 10"
|
|
bitfld.long 0x28 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x2C "MCFG11,Master Configuration Register 11"
|
|
bitfld.long 0x2C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x30 "MCFG12,Master Configuration Register 12"
|
|
bitfld.long 0x30 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x34 "MCFG13,Master Configuration Register 13"
|
|
bitfld.long 0x34 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x38 "MCFG14,Master Configuration Register 14"
|
|
bitfld.long 0x38 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x3C "MCFG15,Master Configuration Register 15"
|
|
bitfld.long 0x3C 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
if (((d.l((ad:0x400A1000+0x40+0x0)))&0x30000)==0x20000)
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "SCFG0,Slave Configuration Register 0"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "SCFG0,Slave Configuration Register 0"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x4)))&0x30000)==0x20000)
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "SCFG1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "SCFG1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x8)))&0x30000)==0x20000)
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "SCFG2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "SCFG2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0xC)))&0x30000)==0x20000)
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "SCFG3,Slave Configuration Register 3"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "SCFG3,Slave Configuration Register 3"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x10)))&0x30000)==0x20000)
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "SCFG4,Slave Configuration Register 4"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "SCFG4,Slave Configuration Register 4"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x14)))&0x30000)==0x20000)
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "SCFG5,Slave Configuration Register 5"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "SCFG5,Slave Configuration Register 5"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x18)))&0x30000)==0x20000)
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "SCFG6,Slave Configuration Register 6"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "SCFG6,Slave Configuration Register 6"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x1C)))&0x30000)==0x20000)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "SCFG7,Slave Configuration Register 7"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "SCFG7,Slave Configuration Register 7"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x20)))&0x30000)==0x20000)
|
|
group.long (0x40+0x20)++0x03
|
|
line.long 0x00 "SCFG8,Slave Configuration Register 8"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x20)++0x03
|
|
line.long 0x00 "SCFG8,Slave Configuration Register 8"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x24)))&0x30000)==0x20000)
|
|
group.long (0x40+0x24)++0x03
|
|
line.long 0x00 "SCFG9,Slave Configuration Register 9"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x24)++0x03
|
|
line.long 0x00 "SCFG9,Slave Configuration Register 9"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x28)))&0x30000)==0x20000)
|
|
group.long (0x40+0x28)++0x03
|
|
line.long 0x00 "SCFG10,Slave Configuration Register 10"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x28)++0x03
|
|
line.long 0x00 "SCFG10,Slave Configuration Register 10"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x2C)))&0x30000)==0x20000)
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "SCFG11,Slave Configuration Register 11"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "SCFG11,Slave Configuration Register 11"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x30)))&0x30000)==0x20000)
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "SCFG12,Slave Configuration Register 12"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "SCFG12,Slave Configuration Register 12"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x34)))&0x30000)==0x20000)
|
|
group.long (0x40+0x34)++0x03
|
|
line.long 0x00 "SCFG13,Slave Configuration Register 13"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x34)++0x03
|
|
line.long 0x00 "SCFG13,Slave Configuration Register 13"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x38)))&0x30000)==0x20000)
|
|
group.long (0x40+0x38)++0x03
|
|
line.long 0x00 "SCFG14,Slave Configuration Register 14"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x38)++0x03
|
|
line.long 0x00 "SCFG14,Slave Configuration Register 14"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l((ad:0x400A1000+0x40+0x3C)))&0x30000)==0x20000)
|
|
group.long (0x40+0x3C)++0x03
|
|
line.long 0x00 "SCFG15,Slave Configuration Register 15"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
group.long (0x40+0x3C)++0x03
|
|
line.long 0x00 "SCFG15,Slave Configuration Register 15"
|
|
bitfld.long 0x00 24. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PRAS0,Priority Register A for Slave 0"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PRAS1,Priority Register A for Slave 1"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PRAS2,Priority Register A for Slave 2"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PRAS3,Priority Register A for Slave 3"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PRAS4,Priority Register A for Slave 4"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PRAS5,Priority Register A for Slave 5"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PRAS6,Priority Register A for Slave 6"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PRAS7,Priority Register A for Slave 7"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PRAS8,Priority Register A for Slave 8"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PRAS9,Priority Register A for Slave 9"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PRAS10,Priority Register A for Slave 10"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PRAS11,Priority Register A for Slave 11"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PRAS12,Priority Register A for Slave 12"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PRAS13,Priority Register A for Slave 13"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PRAS14,Priority Register A for Slave 14"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PRAS15,Priority Register A for Slave 15"
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PRBS0,Priority Register B for Slave 0"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PRBS1,Priority Register B for Slave 1"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PRBS2,Priority Register B for Slave 2"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PRBS3,Priority Register B for Slave 3"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PRBS4,Priority Register B for Slave 4"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PRBS5,Priority Register B for Slave 5"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PRBS6,Priority Register B for Slave 6"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PRBS7,Priority Register B for Slave 7"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PRBS8,Priority Register B for Slave 8"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "PRBS9,Priority Register B for Slave 9"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PRBS10,Priority Register B for Slave 10"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PRBS11,Priority Register B for Slave 11"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PRBS12,Priority Register B for Slave 12"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PRBS13,Priority Register B for Slave 13"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PRBS14,Priority Register B for Slave 14"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PRBS15,Priority Register B for Slave 15"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M12R ,Master 12 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x110++0x3F
|
|
line.long 0x0 "SFR0,Special Function Register 0"
|
|
line.long 0x4 "SFR1,Special Function Register 1"
|
|
line.long 0x8 "SFR2,Special Function Register 2"
|
|
line.long 0xC "SFR3,Special Function Register 3"
|
|
line.long 0x10 "SFR4,Special Function Register 4"
|
|
line.long 0x14 "SFR5,Special Function Register 5"
|
|
line.long 0x18 "SFR6,Special Function Register 6"
|
|
line.long 0x1C "SFR7,Special Function Register 7"
|
|
line.long 0x20 "SFR8,Special Function Register 8"
|
|
line.long 0x24 "SFR9,Special Function Register 9"
|
|
line.long 0x28 "SFR10,Special Function Register 10"
|
|
line.long 0x2C "SFR11,Special Function Register 11"
|
|
line.long 0x30 "SFR12,Special Function Register 12"
|
|
line.long 0x34 "SFR13,Special Function Register 13"
|
|
line.long 0x38 "SFR14,Special Function Register 14"
|
|
line.long 0x3C "SFR15,Special Function Register 15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PDCA (Peripheral DMA Controller)"
|
|
base ad:0x400A2000
|
|
width 0x09
|
|
tree "DMA channel 0x0 configuration registers"
|
|
group.long (0x00+0x0*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x0*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x0*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x0*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x0*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x0*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x1 configuration registers"
|
|
group.long (0x00+0x1*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x1*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x1*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x1*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x1*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x1*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x2 configuration registers"
|
|
group.long (0x00+0x2*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x2*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x2*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x2*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x2*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x2*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x3 configuration registers"
|
|
group.long (0x00+0x3*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x3*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x3*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x3*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x3*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x3*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x4 configuration registers"
|
|
group.long (0x00+0x4*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x4*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x4*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x4*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x4*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x4*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x5 configuration registers"
|
|
group.long (0x00+0x5*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x5*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x5*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x5*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x5*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x5*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x6 configuration registers"
|
|
group.long (0x00+0x6*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x6*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x6*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x6*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x6*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x6*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x7 configuration registers"
|
|
group.long (0x00+0x7*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x7*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x7*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x7*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x7*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x7*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x8 configuration registers"
|
|
group.long (0x00+0x8*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x8*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x8*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x8*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x8*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x8*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0x9 configuration registers"
|
|
group.long (0x00+0x9*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0x9*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0x9*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0x9*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0x9*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x9*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xA configuration registers"
|
|
group.long (0x00+0xA*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xA*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xA*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xA*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xA*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xA*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xB configuration registers"
|
|
group.long (0x00+0xB*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xB*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xB*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xB*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xB*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xB*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xC configuration registers"
|
|
group.long (0x00+0xC*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xC*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xC*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xC*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xC*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xC*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xD configuration registers"
|
|
group.long (0x00+0xD*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xD*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xD*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xD*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xD*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xD*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xE configuration registers"
|
|
group.long (0x00+0xE*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xE*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xE*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xE*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xE*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xE*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "DMA channel 0xF configuration registers"
|
|
group.long (0x00+0xF*0x40)++0x13
|
|
line.long 0x00 "MAR,Memory Address Register"
|
|
line.long 0x04 "PSR,Peripheral Select Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PID ,Peripheral Identifier"
|
|
line.long 0x08 "TCR,Transfer Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TCV ,Transfer Counter Value"
|
|
line.long 0x0c "MARR,Memory Address Reload Register"
|
|
line.long 0x10 "TCRR,Transfer Counter Reload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TCRV ,Transfer Counter Reload Value"
|
|
wgroup.long (0x14+0xF*0x40)++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " ECLR ,Transfer Error Clear" "No effect,Clear"
|
|
group.long (0x18+0xF*0x40)++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 3. " RING ,Ring Buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENTRIG ,Event Trigger" "Transfer requested,Event received"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SIZE ,Size of Transfer" "Byte,Halfword,Word,?..."
|
|
group.long (0x1c+0xF*0x40)++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x8 1. " TEN ,Transfer Enabled" "Disabled,Enabled"
|
|
group.long (0x28+0xF*0x40)++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TERR_set/clr ,Transfer Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRC_set/clr ,Transfer Complete Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RCZ_set/clr ,Reload Counter Zero Interrupt Mask" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0xF*0x40)++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TERR ,Transfer Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRC ,Transfer Complete" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCZ ,Reload Counter Zero" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "Version register"
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "VERSION,PDCA Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USBC (USB Device and Embedded Host Interface)"
|
|
base ad:0x400A5000
|
|
width 0x0B
|
|
tree "General Registers"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "USBCON,General Control Register"
|
|
sif (cpuis("ATSAM4LC*"))
|
|
bitfld.long 0x00 25. " UIMOD ,USBC Mode" "Host,Device"
|
|
elif (cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 25. " UIMOD ,USBC Mode" "Reserved,Device"
|
|
endif
|
|
bitfld.long 0x00 15. " USBE ,USBC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FRZCLK ,Freeze USB Clock" "Enabled,Disabled"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "USBSTA,General Status Register"
|
|
bitfld.long 0x00 16. " SUSPEND ,Suspend usb transceiver state" "Off,On"
|
|
bitfld.long 0x00 14. " CLKUSABLE ,Generic Clock Usable" "Not usable,Usable"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SPEED ,Speed Status" "Full-speed,Reserved,Low-speed,?..."
|
|
setclrfld.long 0x00 9. 0x8 9. 0x4 9. " VBUSRQ_set/clr ,VBUS Request" "Not powered,Powered"
|
|
rgroup.long 0x818++0x1B
|
|
line.long 0x00 "UVERS,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
line.long 0x04 "UFEATURES,Features Register"
|
|
bitfld.long 0x04 0.--3. " EPTNBRMAX ,Maximal Number of pipes/endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "UADDRSIZE,Address Size Register"
|
|
line.long 0x0c "UNAME1,IP Name Register 1"
|
|
line.long 0x10 "UNAME2,IP Name Register 2"
|
|
line.long 0x14 "USBFSM,Finite State Machine Status Register"
|
|
bitfld.long 0x14 0.--3. " DRDSTATE ,Dual Role Device State" "A_idle state,A_wait_vrise,A_wait_bcon,A_host,A_suspend,A_peripheral,A_wait_vfall,A_vbus_err,A_wait_discharge,B_idle,B_peripheral,B_wait_begin_hnp,B_wait_discharge,B_wait_acon,B_host,B_srp_init"
|
|
line.long 0x18 "UDESC,USB Descriptor Address"
|
|
tree.end
|
|
tree "Device Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UDCON,Device General Control Register"
|
|
bitfld.long 0x00 17. " GNAK ,Global NAK" "Normal mode,Enabled"
|
|
bitfld.long 0x00 12. " LS ,Low-speed mode force" "Full-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RMWKUP ,Remote wakeup" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " DETACH ,Detach" "Reconnect,Detached"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADDEN ,Address Enable" "No effect,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " UADD ,USB Address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UDINT,Device Global Interrupt Register"
|
|
bitfld.long 0x00 20. " EP8INT ,Endpoint 8 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 19. " EP7INT ,Endpoint 7 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EP6INT ,Endpoint 6 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 17. " EP5INT ,Endpoint 5 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EP4INT ,Endpoint 4 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 15. " EP3INT ,Endpoint 3 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EP2INT ,Endpoint 2 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " EP1INT ,Endpoint 1 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EP0INT ,Endpoint 0 Interrupt" "Not triggered,Triggered"
|
|
setclrfld.long 0x00 6. 0x8 6. 0x4 6. " UPRSM_set/clr ,Upstream Resume Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x8 5. 0x4 5. " EORSM_set/clr ,End of Resume Interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x8 4. 0x4 4. " WAKEUP_set/clr ,Wakeup Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x8 3. 0x4 3. " EORST_set/clr ,End of Reset Interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x8 2. 0x4 2. " SOF_set/clr ,Start of Frame Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x8 0. 0x4 0. " SUSP_set/clr ,Suspend Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UDINTE,Device Global Interrupt Enable Register"
|
|
setclrfld.long 0x00 20. 0x8 20. 0x4 20. " EP8INTE_set/clr ,Endpoint 8 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x8 19. 0x4 19. " EP7INTE_set/clr ,Endpoint 7 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x8 18. 0x4 18. " EP6INTE_set/clr ,Endpoint 6 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x8 17. 0x4 17. " EP5INTE_set/clr ,Endpoint 5 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x8 16. 0x4 16. " EP4INTE_set/clr ,Endpoint 4 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x8 15. 0x4 15. " EP3INTE_set/clr ,Endpoint 3 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x8 14. 0x4 14. " EP2INTE_set/clr ,Endpoint 2 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x8 13. 0x4 13. " EP1INTE_set/clr ,Endpoint 1 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x8 12. 0x4 12. " EP0INTE_set/clr ,Endpoint 0 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x8 6. 0x4 6. " UPRSME_set/clr ,Upstream Resume Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x8 5. 0x4 5. " EORSME_set/clr ,End of Resume Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x8 4. 0x4 4. " WAKEUPE_set/clr ,Wakeup Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x8 3. 0x4 3. " EORSTE_set/clr ,End of Reset Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x8 2. 0x4 2. " SOFE_set/clr ,Start of Frame Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x8 0. 0x4 0. " SUSPE_set/clr ,Suspend Interrupt" "Disabled,Enabled"
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "UERST,Endpoint Enable/Reset Register"
|
|
bitfld.long 0x00 8. " EPEN8 ,Endpoint 8 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EPEN7 ,Endpoint 7 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EPEN6 ,Endpoint 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EPEN5 ,Endpoint 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EPEN4 ,Endpoint 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EPEN3 ,Endpoint 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPEN2 ,Endpoint 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EPEN1 ,Endpoint 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EPEN0 ,Endpoint 0 Enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "UDFNUM,Device Frame Number Register"
|
|
bitfld.long 0x00 15. " FNCERR ,Frame Number CRC Error" "No errror,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FNUM ,Frame Number"
|
|
tree "Endpoint 0 Registers"
|
|
group.long (0x100+0*0x04)++0x03
|
|
line.long 0x00 "UECFG0,Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+0*0x04)++0x03
|
|
line.long 0x00 "UESTA0,Endpoint 0 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+0*0x04)++0x03
|
|
line.long 0x00 "UESTA0SET,Endpoint 0 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+0*0x04)++0x03
|
|
line.long 0x00 "UECON0,Endpoint 0 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+0*0x04)++0x03
|
|
line.long 0x00 "UECON0CLR,Endpoint 0 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+0*0x04)++0x03
|
|
line.long 0x00 "UECON0SET,Endpoint 0 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 1 Registers"
|
|
group.long (0x100+1*0x04)++0x03
|
|
line.long 0x00 "UECFG1,Endpoint 1 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+1*0x04)++0x03
|
|
line.long 0x00 "UESTA1,Endpoint 1 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+1*0x04)++0x03
|
|
line.long 0x00 "UESTA1SET,Endpoint 1 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+1*0x04)++0x03
|
|
line.long 0x00 "UECON1,Endpoint 1 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+1*0x04)++0x03
|
|
line.long 0x00 "UECON1CLR,Endpoint 1 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+1*0x04)++0x03
|
|
line.long 0x00 "UECON1SET,Endpoint 1 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 2 Registers"
|
|
group.long (0x100+2*0x04)++0x03
|
|
line.long 0x00 "UECFG2,Endpoint 2 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+2*0x04)++0x03
|
|
line.long 0x00 "UESTA2,Endpoint 2 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+2*0x04)++0x03
|
|
line.long 0x00 "UESTA2SET,Endpoint 2 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+2*0x04)++0x03
|
|
line.long 0x00 "UECON2,Endpoint 2 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+2*0x04)++0x03
|
|
line.long 0x00 "UECON2CLR,Endpoint 2 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+2*0x04)++0x03
|
|
line.long 0x00 "UECON2SET,Endpoint 2 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 3 Registers"
|
|
group.long (0x100+3*0x04)++0x03
|
|
line.long 0x00 "UECFG3,Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+3*0x04)++0x03
|
|
line.long 0x00 "UESTA3,Endpoint 3 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+3*0x04)++0x03
|
|
line.long 0x00 "UESTA3SET,Endpoint 3 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+3*0x04)++0x03
|
|
line.long 0x00 "UECON3,Endpoint 3 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+3*0x04)++0x03
|
|
line.long 0x00 "UECON3CLR,Endpoint 3 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+3*0x04)++0x03
|
|
line.long 0x00 "UECON3SET,Endpoint 3 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 4 Registers"
|
|
group.long (0x100+4*0x04)++0x03
|
|
line.long 0x00 "UECFG4,Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+4*0x04)++0x03
|
|
line.long 0x00 "UESTA4,Endpoint 4 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+4*0x04)++0x03
|
|
line.long 0x00 "UESTA4SET,Endpoint 4 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+4*0x04)++0x03
|
|
line.long 0x00 "UECON4,Endpoint 4 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+4*0x04)++0x03
|
|
line.long 0x00 "UECON4CLR,Endpoint 4 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+4*0x04)++0x03
|
|
line.long 0x00 "UECON4SET,Endpoint 4 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 5 Registers"
|
|
group.long (0x100+5*0x04)++0x03
|
|
line.long 0x00 "UECFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+5*0x04)++0x03
|
|
line.long 0x00 "UESTA5,Endpoint 5 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+5*0x04)++0x03
|
|
line.long 0x00 "UESTA5SET,Endpoint 5 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+5*0x04)++0x03
|
|
line.long 0x00 "UECON5,Endpoint 5 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+5*0x04)++0x03
|
|
line.long 0x00 "UECON5CLR,Endpoint 5 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+5*0x04)++0x03
|
|
line.long 0x00 "UECON5SET,Endpoint 5 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 6 Registers"
|
|
group.long (0x100+6*0x04)++0x03
|
|
line.long 0x00 "UECFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+6*0x04)++0x03
|
|
line.long 0x00 "UESTA6,Endpoint 6 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+6*0x04)++0x03
|
|
line.long 0x00 "UESTA6SET,Endpoint 6 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+6*0x04)++0x03
|
|
line.long 0x00 "UECON6,Endpoint 6 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+6*0x04)++0x03
|
|
line.long 0x00 "UECON6CLR,Endpoint 6 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+6*0x04)++0x03
|
|
line.long 0x00 "UECON6SET,Endpoint 6 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree "Endpoint 7 Registers"
|
|
group.long (0x100+7*0x04)++0x03
|
|
line.long 0x00 "UECFG7,Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 16.--19. " REPNB ,Redirected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "OUT,IN"
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPBK ,Endpoint Banks" "Single,Double"
|
|
group.long (0x130+7*0x04)++0x03
|
|
line.long 0x00 "UESTA7,Endpoint 7 Status Register"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "OUT,IN"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,?..."
|
|
setclrfld.long 0x00 11. 0x60 11. 0x30 11. " RAMACERI_set/clr ,Ram Access Error Interrupt" "Interrupt acknowledged,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKINI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " NAKOUTI_set/clr ,NAKed OUT Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " RXSTPI/ERRORFI_set/clr ,Received SETUP Interrupt/Isochronous Error flow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x190+7*0x04)++0x03
|
|
line.long 0x00 "UESTA7SET,Endpoint 7 Status Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks" "0,1"
|
|
group.long (0x1C0+7*0x04)++0x03
|
|
line.long 0x00 "UECON7,Endpoint 7 Control Register"
|
|
setclrfld.long 0x00 25. 0x30 25. 0x60 25. " BUSY1E_set/clr ,Busy Bank1 Enable" "Not busy,Busy"
|
|
setclrfld.long 0x00 24. 0x30 24. 0x60 24. " BUSY0E_set/clr ,Busy Bank0 Enable" "Not busy,Busy"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "No request,Request"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT endpoints)" "Next,TXINI/RXINI"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x30 11. 0x60 11. " RAMACERE_set/clr ,RAMACER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " NREPLY_set/clr ,No Reply" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_set/clr ,NAKed IN Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_set/clr ,NAKed OUT Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/ERRORFE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x220+7*0x04)++0x03
|
|
line.long 0x00 "UECON7CLR,Endpoint 7 Control Clear Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control" "No effect,Clear"
|
|
wgroup.long (0x1F0+7*0x04)++0x03
|
|
line.long 0x00 "UECON7SET,Endpoint 7 Control Set Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No effect,Set"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "No effect,Set"
|
|
tree.end
|
|
tree.end
|
|
sif (!cpuis("ATSAM4LS*"))
|
|
tree "Host Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "UHCON,Host General Control Register"
|
|
bitfld.long 0x00 10. " RESUME ,Send USB Resume" "No effect,Resume"
|
|
bitfld.long 0x00 9. " RESET ,Send USB Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SOFE ,Start of Frame Generation Enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "UHINT,Host Global Interrupt Register"
|
|
bitfld.long 0x00 16. " P8INT ,Pipe 8 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 15. " P7INT ,Pipe 7 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P6INT ,Pipe 6 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " P5INT ,Pipe 5 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P4INT ,Pipe 4 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 11. " P3INT ,Pipe 3 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P2INT ,Pipe 2 Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " P1INT ,Pipe 1 Interrupt" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P0INT ,Pipe 0 Interrupt" "Not triggered,Triggered"
|
|
setclrfld.long 0x00 6. 0x8 6. 0x4 6. " HWUPI_set/clr ,Host Wakeup Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x8 5. 0x4 5. " HSOFI_set/clr ,Host Start of Frame Interrupt" "No effect,Interrupt"
|
|
setclrfld.long 0x00 4. 0x8 4. 0x4 4. " RXRSMI_set/clr ,Upstream Resume Received Interrupt" "No effect,Received"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x8 3. 0x4 3. " RSMEDI_set/clr ,Downstream Resume Sent Interrupt" "No effect,Sent"
|
|
setclrfld.long 0x00 2. 0x8 2. 0x4 2. " RSTI_set/clr ,USB Reset Sent Interrupt" "No effect,Sent"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x8 1. 0x4 1. " DDISCI_set/clr ,Device Disconnection Interrupt" "No effect,Removed"
|
|
setclrfld.long 0x00 0. 0x8 0. 0x4 0. " DCONNI_set/clr ,Device Connection Interrupt" "No effect,Connected"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "UHINTE,Host Global Interrupt Enable Register"
|
|
setclrfld.long 0x00 16. 0x8 16. 0x4 16. " P8INTE_set/clr ,Pipe 8 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x8 15. 0x4 15. " P7INTE_set/clr ,Pipe 7 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x8 14. 0x4 14. " P6INTE_set/clr ,Pipe 6 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x8 13. 0x4 13. " P5INTE_set/clr ,Pipe 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x8 12. 0x4 12. " P4INTE_set/clr ,Pipe 4 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x8 11. 0x4 11. " P3INTE_set/clr ,Pipe 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x8 10. 0x4 10. " P2INTE_set/clr ,Pipe 2 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x8 9. 0x4 9. " P1INTE_set/clr ,Pipe 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x8 8. 0x4 8. " P0INTE_set/clr ,Pipe 0 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x8 6. 0x4 6. " HWUPIE_set/clr ,Host Wakeup Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x8 5. 0x4 5. " HSOFIE_set/clr ,Host Start of Frame Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x8 4. 0x4 4. " RXRSMIE_set/clr ,Upstream Resume Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x8 3. 0x4 3. " RSMEDIE_set/clr ,Downstream Resume Sent Interr" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x8 2. 0x4 2. " RSTIE_set/clr ,USB Reset Sent Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x8 1. 0x4 1. " DDISCIE_set/clr ,Device Disconnection Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x8 0. 0x4 0. " DCONNIE_set/clr ,Device Connection Interrupt" "Disabled,Enabled"
|
|
group.long 0x41C++0x0B
|
|
line.long 0x00 "UPRST,Pipe Enable/Reset Register"
|
|
bitfld.long 0x00 8. " PEN8 ,Pipe 8 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PEN7 ,Pipe 7 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PEN6 ,Pipe 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PEN5 ,Pipe 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PEN4 ,Pipe 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PEN3 ,Pipe 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEN2 ,Pipe 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PEN1 ,Pipe 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PEN0 ,Pipe 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UHFNUM,Host Frame Number Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FLENHIGH ,Frame Length"
|
|
hexmask.long.word 0x04 3.--13. 1. " FNUM ,Frame Number"
|
|
line.long 0x08 "UHSOFC,Host Start Of Frame Control Register"
|
|
bitfld.long 0x08 16. " FLENCE ,Frame Length Control Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--15. 1. " FLENC ,Frame Length Control"
|
|
tree "PIPE 0 Registers"
|
|
group.long (0x500+0*0x04)++0x03
|
|
line.long 0x00 "UPCFG0,Pipe 0 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+0*0x04)++0x03
|
|
line.long 0x00 "UPSTA0,Pipe 0 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+0*0x04)++0x03
|
|
line.long 0x00 "UPCON0,Pipe 0 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+0*0x04)++0x03
|
|
line.long 0x00 "UPINRQ0,Pipe 0 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 1 Registers"
|
|
group.long (0x500+1*0x04)++0x03
|
|
line.long 0x00 "UPCFG1,Pipe 1 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+1*0x04)++0x03
|
|
line.long 0x00 "UPSTA1,Pipe 1 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+1*0x04)++0x03
|
|
line.long 0x00 "UPCON1,Pipe 1 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+1*0x04)++0x03
|
|
line.long 0x00 "UPINRQ1,Pipe 1 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 2 Registers"
|
|
group.long (0x500+2*0x04)++0x03
|
|
line.long 0x00 "UPCFG2,Pipe 2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+2*0x04)++0x03
|
|
line.long 0x00 "UPSTA2,Pipe 2 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+2*0x04)++0x03
|
|
line.long 0x00 "UPCON2,Pipe 2 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+2*0x04)++0x03
|
|
line.long 0x00 "UPINRQ2,Pipe 2 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 3 Registers"
|
|
group.long (0x500+3*0x04)++0x03
|
|
line.long 0x00 "UPCFG3,Pipe 3 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+3*0x04)++0x03
|
|
line.long 0x00 "UPSTA3,Pipe 3 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+3*0x04)++0x03
|
|
line.long 0x00 "UPCON3,Pipe 3 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+3*0x04)++0x03
|
|
line.long 0x00 "UPINRQ3,Pipe 3 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 4 Registers"
|
|
group.long (0x500+4*0x04)++0x03
|
|
line.long 0x00 "UPCFG4,Pipe 4 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+4*0x04)++0x03
|
|
line.long 0x00 "UPSTA4,Pipe 4 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+4*0x04)++0x03
|
|
line.long 0x00 "UPCON4,Pipe 4 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+4*0x04)++0x03
|
|
line.long 0x00 "UPINRQ4,Pipe 4 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 5 Registers"
|
|
group.long (0x500+5*0x04)++0x03
|
|
line.long 0x00 "UPCFG5,Pipe 5 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+5*0x04)++0x03
|
|
line.long 0x00 "UPSTA5,Pipe 5 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+5*0x04)++0x03
|
|
line.long 0x00 "UPCON5,Pipe 5 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+5*0x04)++0x03
|
|
line.long 0x00 "UPINRQ5,Pipe 5 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 6 Registers"
|
|
group.long (0x500+6*0x04)++0x03
|
|
line.long 0x00 "UPCFG6,Pipe 6 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+6*0x04)++0x03
|
|
line.long 0x00 "UPSTA6,Pipe 6 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+6*0x04)++0x03
|
|
line.long 0x00 "UPCON6,Pipe 6 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+6*0x04)++0x03
|
|
line.long 0x00 "UPINRQ6,Pipe 6 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree "PIPE 7 Registers"
|
|
group.long (0x500+7*0x04)++0x03
|
|
line.long 0x00 "UPCFG7,Pipe 7 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,BInterval parameter"
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "SETUP,IN,OUT,?..."
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBK ,Pipe Banks" "Single,Double"
|
|
group.long (0x530+7*0x04)++0x03
|
|
line.long 0x00 "UPSTA7,Pipe 7 Status Register"
|
|
bitfld.long 0x00 14. " CURRBK ,Current Bank" "Bank0,Bank1"
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "All banks are free,1 busy bank,2 busy banks,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x60 10. 0x30 10. " RAMACERI_set/clr ,Ram Access Error Interrupt" "No effect,Error"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " ERRORFI_set/clr ,Errorflow Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_set/clr ,NAKed Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x60 3. 0x30 3. " PERRI_set/clr ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_set/clr ,Transmitted SETUP Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
group.long (0x5C0+7*0x04)++0x03
|
|
line.long 0x00 "UPCON7,Pipe 7 Control Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " INITBK_set/clr ,Bank Initialization" "Bank 0,Bank 1"
|
|
setclrfld.long 0x00 18. 0x30 18. 0x60 18. " INITDTGL_set/clr ,Data Toggle Initialization" "Data 0,Data 1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_set/clr ,Pipe Freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control (IN/OUT&SETUP pipes)" "Next bank,Not empty/Empty"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RAMACERE ,Ram Access Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " ERRORFIE_set/clr ,Errorflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_set/clr ,Transmitted SETUP Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x650+7*0x04)++0x03
|
|
line.long 0x00 "UPINRQ7,Pipe 7 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "INRQ field,Infinite IN requests"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("ATSAM4LC*"))
|
|
tree "AESA (Advanced Encryption Standard)"
|
|
base ad:0x400B0000
|
|
width 0x0C
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 2. " NEWMSG ,New Message" "No effect,New Message"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DKEYGEN ,Decryption Key Generate" "No effect,Generated"
|
|
bitfld.long 0x00 0. " ENABLE , Enable Module" "Disabled,Enabled"
|
|
line.long 0x04 "MODE,Mode Register"
|
|
bitfld.long 0x04 19. " CTYPE[3] ,Countermeasure Type 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CTYPE[2] ,Countermeasure Type 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " CTYPE[1] ,Countermeasure Type 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CTYPE[0] ,Countermeasure Type 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " CFBS ,Cipher Feedback Data Segment Size" "128 bits,64 bits,32 bits,16 bits,8 bits,?..."
|
|
bitfld.long 0x04 4.--6. " OPMODE ,Confidentiality Mode of Operation" "Electronic Code Book,Cipher Block Chaining,Cipher Feedback,Output Feedback,Counter,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " DMA ,DMA Mode" "Non-DMA,DMA"
|
|
bitfld.long 0x04 0. " ENCRYPT ,Encryption mode" "Decryption,Encryption"
|
|
line.long 0x08 "DATABUFPTR,Data Buffer Pointer Register"
|
|
bitfld.long 0x08 4.--5. " ODATAW ,Output Data Word" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " IDATAW ,Input Data Word" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 16. " IBUFRDY ,Input Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ODATARDY ,Output Data Ready" "All ODATAn have been read,Data can be read from the ODATAn"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " IBUFRDY_set/clr ,Input Buffer Ready Interrupt Mask " "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " ODATARDY_set/clr ,Output Data Ready Interrupt Mask " "Disabled,Enabled"
|
|
wgroup.long (0x20+0*0x04)++0x03
|
|
line.long 0x00 "KEY0,Key Register 0"
|
|
wgroup.long (0x20+1*0x04)++0x03
|
|
line.long 0x00 "KEY1,Key Register 1"
|
|
wgroup.long (0x20+2*0x04)++0x03
|
|
line.long 0x00 "KEY2,Key Register 2"
|
|
wgroup.long (0x20+3*0x04)++0x03
|
|
line.long 0x00 "KEY3,Key Register 3"
|
|
wgroup.long (0x20+4*0x04)++0x03
|
|
line.long 0x00 "KEY4,Key Register 4"
|
|
wgroup.long (0x20+5*0x04)++0x03
|
|
line.long 0x00 "KEY5,Key Register 5"
|
|
wgroup.long (0x20+6*0x04)++0x03
|
|
line.long 0x00 "KEY6,Key Register 6"
|
|
wgroup.long (0x20+7*0x04)++0x03
|
|
line.long 0x00 "KEY7,Key Register 7"
|
|
wgroup.long (0x40+0*0x04)++0x03
|
|
line.long 0x00 "INITVECT0,Initialization Vector Register 0"
|
|
wgroup.long (0x40+1*0x04)++0x03
|
|
line.long 0x00 "INITVECT1,Initialization Vector Register 1"
|
|
wgroup.long (0x40+2*0x04)++0x03
|
|
line.long 0x00 "INITVECT2,Initialization Vector Register 2"
|
|
wgroup.long (0x40+3*0x04)++0x03
|
|
line.long 0x00 "INITVECT3,Initialization Vector Register 3"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "IDATA,Input Data Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ODATA,Output Data Register"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "DRNG_SEED,DRNG Seed Register"
|
|
rgroup.long 0xF8++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
bitfld.long 0x00 8. " CTRMEAS ,Countermeasures" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2.--4. " OPMODE ,Maximum Number of Confidentiality Modes of Operation" "ECB,ECB/CBC,ECB/CBC/CFB,ECB/CBC/CFB/OFB,ECB/CBC/CFB/OFB/CTR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " KEYSIZE ,Maximum Key Size" "128,128 & 192 bit,128 & 192 & 256 bit,?..."
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "AST (Asynchronous Timer)"
|
|
base ad:0x400F0800
|
|
width 0x0B
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--20. " PSEL ,Prescaler Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " CA1 ,Clear on Alarm 1" "Not clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CA0 ,Clear on Alarm 0" "Not clear,Clear"
|
|
bitfld.long 0x00 2. " CAL ,Calendar Mode" "Counter,Calendar"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PCLR ,Prescaler Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " EN ,AST Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CV,Counter Value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 29. " CLKRDY ,Clock Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 28. " CLKBUSY ,Clock Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 25. " READY ,AST Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 24. " BUSY ,AST Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PER0 ,Periodic 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALARM0 ,Alarm 0" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OVF ,Overflow" "Not occurred,Occurred"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 29. " CLKRDY ,Clock Ready" "No effect,Clear"
|
|
bitfld.long 0x00 25. " READY ,AST Ready" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PER0 ,Periodic 0" "No effect,Clear"
|
|
bitfld.long 0x00 8. " ALARM0 ,Alarm 0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OVF ,Overflow" "No effect,Clear"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " CLKRDY_set/clr ,Clock Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " READY_set/clr ,AST Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " PER0_set/clr ,Periodic 0 Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ALARM0_set/clr ,Alarm 0 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " OVF_set/clr ,Overflow Interrupt Mask" "Masked,Not masked"
|
|
line.long 0x04 "WER,Wake Enable Register"
|
|
bitfld.long 0x04 16. " PER0 ,Periodic 0" "Not woken up,Woken up"
|
|
bitfld.long 0x04 8. " ALARM0 ,Alarm 0" "Not woken up,Woken up"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OVF ,Overflow" "Not woken up,Woken up"
|
|
line.long 0x08 "AR0,Alarm Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PIR0,Periodic Interval Register 0"
|
|
bitfld.long 0x00 0.--4. " INSEL ,Interval Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CLOCK,Clock Control Register"
|
|
bitfld.long 0x00 8.--10. " CSSEL ,Clock Source Selection" "RCSYS,OSC32/RC32,APB clock,GCLK,CLK_1K,?..."
|
|
bitfld.long 0x00 0. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTR,Digital Tuner Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " VALUE ,Frequency value"
|
|
bitfld.long 0x04 5. " ADD ,Add value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " EXP ,Exponent value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "EVM,Event Mask Register"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " PER0_set/clr ,Periodic 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ALARM0_set/clr ,Alarm 0" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " OVF_set/clr ,Overflow" "Masked,Not masked"
|
|
line.long 0x04 "CALV,Calendar Value"
|
|
hexmask.long.byte 0x04 26.--31. 1. " YEAR ,Current year"
|
|
bitfld.long 0x04 22.--25. " MONTH ,Month" "January,February,March,April,May,June,July,August,September,October,November,December,?..."
|
|
textline " "
|
|
bitfld.long 0x04 17.--21. " DAY ,Day" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
bitfld.long 0x04 12.--16. " HOUR ,Hour" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--11. " MIN ,Minute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x04 0.--5. " SEC ,Second" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
rgroup.long 0xF0++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
bitfld.long 0x00 24.--28. " PER1VALUE ,Periodic Interval 1 Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " PER0VALUE ,Periodic Interval 0 Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIR1WA ,Periodic Interval 1 Writeable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PIR0WA ,Periodic Interval 0 Writeable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NUMPIR ,Number of Periodic Comparators" "One,Two"
|
|
bitfld.long 0x00 8.--9. " NUMAR ,Number of Alarm Comparators" "Zero,One,Two,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--6. " DTEXPVALUE ,Digital Tuner Exponent Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DTEXPWA ,Digital Tuner Exponent Writeable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DT ,Digital Tuner" "Not implemented,Implemented"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400F0C00
|
|
width 0x09
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Key"
|
|
bitfld.long 0x00 18.--22. " TBAN ,Time Ban Prescale Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSSEL ,Clock Source Select" "RC oscillator,32KHz oscillator"
|
|
bitfld.long 0x00 16. " CEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " PSEL ,Time Out Prescale Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " FCD ,Flash Calibration Done" "Redone,Not redone"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IN ,Interrupt Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SFV ,WDT Control Register Store Final Value" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MODE ,WDT Mode" "Basic,Window"
|
|
bitfld.long 0x00 1. " DAR ,WDT Disable After Reset" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,WDT Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CLR,Clear Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Key"
|
|
bitfld.long 0x00 0. " WDTCLR ,Watchdog Clear" "No effect,Clear"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 1. " CLEARED ,WDT Counter Cleared" "No cleared,Cleared"
|
|
bitfld.long 0x00 0. " WINDOW ,Within Window" "TBAN period,PSEL period"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " WINT_set/clr ,Watchdog Interrupt Mask" "Masked,Not masked"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " WINT ,Watchdog Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 2. " WINT ,Watchdog Interrupt Clear" "No effect,Clear"
|
|
rgroup.long 0x3FC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EIC (External Interrupt Controller)"
|
|
base ad:0x400F1000
|
|
width 0x09
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " INT8_set/clr ,External Interrupt 8" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " INT7_set/clr ,External Interrupt 7" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " INT6_set/clr ,External Interrupt 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " INT5_set/clr ,External Interrupt 5" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " INT4_set/clr ,External Interrupt 4" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " INT3_set/clr ,External Interrupt 3" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " INT2_set/clr ,External Interrupt 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " INT1_set/clr ,External Interrupt 1" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " NMI ,Non-Maskable Interrupt" "Masked,Not masked"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "Not occurred,Occurred"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "No effect,Clear"
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "MODE,Mode Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "Edge,Level"
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "Edge,Level"
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "Edge,Level"
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "Edge,Level"
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "Edge,Level"
|
|
line.long 0x04 "EDGE,Edge Register"
|
|
bitfld.long 0x04 8. " INT8 ,External Interrupt 8" "Falling,Rising"
|
|
bitfld.long 0x04 7. " INT7 ,External Interrupt 7" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INT6 ,External Interrupt 6" "Falling,Rising"
|
|
bitfld.long 0x04 5. " INT5 ,External Interrupt 5" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INT4 ,External Interrupt 4" "Falling,Rising"
|
|
bitfld.long 0x04 3. " INT3 ,External Interrupt 3" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INT2 ,External Interrupt 2" "Falling,Rising"
|
|
bitfld.long 0x04 1. " INT1 ,External Interrupt 1" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x04 0. " NMI ,Non-Maskable Interrupt" "Falling,Rising"
|
|
line.long 0x08 "LEVEL,Level Register"
|
|
bitfld.long 0x08 8. " INT8 ,External Interrupt 8" "Low,High"
|
|
bitfld.long 0x08 7. " INT7 ,External Interrupt 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " INT6 ,External Interrupt 6" "Low,High"
|
|
bitfld.long 0x08 5. " INT5 ,External Interrupt 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 4. " INT4 ,External Interrupt 4" "Low,High"
|
|
bitfld.long 0x08 3. " INT3 ,External Interrupt 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INT2 ,External Interrupt 2" "Low,High"
|
|
bitfld.long 0x08 1. " INT1 ,External Interrupt 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " NMI ,Non-Maskable Interrupt" "Low,High"
|
|
line.long 0x0C "FILTER,Filter Register"
|
|
bitfld.long 0x0C 8. " INT8 ,External Interrupt 8" "Not filtered,Filtered"
|
|
bitfld.long 0x0C 7. " INT7 ,External Interrupt 7" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " INT6 ,External Interrupt 6" "Not filtered,Filtered"
|
|
bitfld.long 0x0C 5. " INT5 ,External Interrupt 5" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " INT4 ,External Interrupt 4" "Not filtered,Filtered"
|
|
bitfld.long 0x0C 3. " INT3 ,External Interrupt 3" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " INT2 ,External Interrupt 2" "Not filtered,Filtered"
|
|
bitfld.long 0x0C 1. " INT1 ,External Interrupt 1" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " NMI ,Non-Maskable Interrupt" "Not filtered,Filtered"
|
|
if ((d.l(ad:0x400F1000+0x24)&0x80000000)==0x80000000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 31. " TESTEN ,Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "0,1"
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "0,1"
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "0,1"
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "0,1"
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "0,1"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 31. " TESTEN ,Test Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ASYNC,Asynchronous Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "Synchronized,Asynchronized"
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "Synchronized,Asynchronized"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "Synchronized,Asynchronized"
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "Synchronized,Asynchronized"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "Synchronized,Asynchronized"
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "Synchronized,Asynchronized"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "Synchronized,Asynchronized"
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "Synchronized,Asynchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "Synchronized,Asynchronized"
|
|
wgroup.long 0x30++0x07
|
|
line.long 0x00 "EN,Enable Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "No effect,Enable"
|
|
bitfld.long 0x00 7. " INT8 ,External Interrupt 7" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT8 ,External Interrupt 6" "No effect,Enable"
|
|
bitfld.long 0x00 5. " INT8 ,External Interrupt 5" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT8 ,External Interrupt 4" "No effect,Enable"
|
|
bitfld.long 0x00 3. " INT8 ,External Interrupt 3" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT8 ,External Interrupt 2" "No effect,Enable"
|
|
bitfld.long 0x00 1. " INT8 ,External Interrupt 1" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "No effect,Enable"
|
|
line.long 0x04 "DIS,Disable Register"
|
|
bitfld.long 0x04 8. " INT8 ,External Interrupt 8" "No effect,Yes"
|
|
bitfld.long 0x04 7. " INT7 ,External Interrupt 7" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INT6 ,External Interrupt 6" "No effect,Yes"
|
|
bitfld.long 0x04 5. " INT5 ,External Interrupt 5" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INT4 ,External Interrupt 4" "No effect,Yes"
|
|
bitfld.long 0x04 3. " INT3 ,External Interrupt 3" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INT2 ,External Interrupt 2" "No effect,Yes"
|
|
bitfld.long 0x04 1. " INT1 ,External Interrupt 1" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " NMI ,Non-Maskable Interrupt" "No effect,Yes"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 8. " INT8 ,External Interrupt 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INT7 ,External Interrupt 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INT6 ,External Interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INT5 ,External Interrupt 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INT4 ,External Interrupt 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " INT3 ,External Interrupt 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT2 ,External Interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT1 ,External Interrupt 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,Non-Maskable Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x3Fc++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FREQM (Frequency Meter)"
|
|
base ad:0x400E0C00
|
|
width 0x09
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 0. " START ,Start a measurement" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MODE,Mode Register"
|
|
bitfld.long 0x00 31. " REFCEN ,Reference Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " CLKSEL ,Clock Source Selection" "CLK_CPU,CLK_AHB,CLK_APBA,CLK_APBB,CLK_APBC,CLK_APBD,OSC0,CLK32K,RCSYS,DFLL0,,GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,GCLK8,GCLK9,GCLK10,GCLK11,RC80M,RCFAST,RC1M,PLL,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " REFNUM ,Number of Reference Clock Cycles"
|
|
bitfld.long 0x00 0.--2. " REFSEL ,Reference Clock Selection" "RCSYS,CLK32K,CLK1K,GCLK11,?..."
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 1. " RCLKBUSY ,FREQM Reference Clock Status" "Ready,Not ready"
|
|
bitfld.long 0x00 0. " BUSY ,FREQM Status" "Idle,On-going"
|
|
line.long 0x04 "VALUE,Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " VALUE ,Result from measurement"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " RCLKRDY_set/clr ,FREQM Reference Clock Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " DONE_set/clr ,Operation done Interrupt Mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 1. " RCLKRDY ,FREQM Reference Clock Ready" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " DONE ,Operation done" "Not pending,Pending"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RCLKRDY ,FREQM Reference Clock Ready" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DONE ,Operation done" "No effect,Clear"
|
|
rgroup.long 0x3FC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("ATSAM4L??C"))
|
|
tree.open "GPIO (General-Purpose Input/Output Controller)"
|
|
sif (cpuis("ATSAM4LS*"))
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Value pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Value pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Value pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Value pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Value pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Value pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 31. " P31 ,Pin Value pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Pin Value pin 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pin Value pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Pin Value pin 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pin Value pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x200+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x200+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x200+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x200+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x200+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x400+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Value pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Value pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Value pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x400+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Value pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Value pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Value pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x400+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 31. " P31 ,Pin Value pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Pin Value pin 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pin Value pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Pin Value pin 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pin Value pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x400+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x400+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x400+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x400+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x400+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x400+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x400+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x400+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x400+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x400+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x400+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x400+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x400+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x400+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x400+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x200+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x200+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x200+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x200+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x200+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x400+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x400+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x400+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Value pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Value pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Value pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x400+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Value pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Value pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Value pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x400+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 31. " P31 ,Pin Value pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Pin Value pin 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pin Value pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Pin Value pin 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pin Value pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x400+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x400+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x400+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x400+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x400+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x400+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x400+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x400+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x400+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x400+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x400+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x400+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x400+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x400+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x400+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x400+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x400+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x400+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
elif (cpuis("ATSAM4L??B"))
|
|
tree.open "GPIO (General-Purpose Input/Output Controller)"
|
|
sif (cpuis("ATSAM4LS*"))
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Value pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Value pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Value pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Value pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Value pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Value pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 31. " P31 ,Pin Value pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Pin Value pin 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pin Value pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Pin Value pin 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pin Value pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x200+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x200+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x200+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x200+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x200+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x200+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x200+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x200+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x200+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x200+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x200+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x200+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x200+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x200+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x200+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x200+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x200+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x200+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
elif (cpuis("ATSAM4L??A"))
|
|
tree.open "GPIO (General-Purpose Input/Output Controller)"
|
|
sif (cpuis("ATSAM4LS*"))
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,GPIO Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,GPIO Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,GPIO Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,GPIO Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,GPIO Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Multiplexer Select pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Multiplexer Select pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Multiplexer Select pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Multiplexer Select pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Multiplexer Select pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Driver Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Driver Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driver Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Driver Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driver Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Value pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Value pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Value pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Value pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Value pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Value pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Value pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Value pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 31. " P31 ,Pin Value pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Pin Value pin 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pin Value pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Pin Value pin 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pin Value pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-up Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-up Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-up Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-up Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-up Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Pull-down Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Pull-down Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Pull-down Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Pull-down Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Pull-down Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Mode Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Mode Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Mode Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Mode Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Mode Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Glitch Filter Enable pin 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Glitch Filter Enable pin 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Glitch Filter Enable pin 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Glitch Filter Enable pin 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Glitch Filter Enable pin 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " P31 ,Interrupt Flag pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " P30 ,Interrupt Flag pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Interrupt Flag pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " P28 ,Interrupt Flag pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Interrupt Flag pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 0 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 0 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 0 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 0 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 0 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Output Driving Capability Register Bit 1 pin 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Output Driving Capability Register Bit 1 pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Driving Capability Register Bit 1 pin 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Output Driving Capability Register Bit 1 pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Driving Capability Register Bit 1 pin 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x4 31. 0x8 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x4 30. 0x8 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x4 29. 0x8 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x4 28. 0x8 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x4 27. 0x8 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 31. " P31 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P30 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Port A"
|
|
base ad:0x400E1000
|
|
width 0x0B
|
|
group.long (0x000+0x00)++0x03
|
|
line.long 0x00 "GPER,GPIO Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x0C)++0x03
|
|
line.long 0x0 "GPERT,GPIO Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,GPIO Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,GPIO Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,GPIO Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,GPIO Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,GPIO Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,GPIO Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,GPIO Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,GPIO Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,GPIO Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,GPIO Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,GPIO Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,GPIO Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,GPIO Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,GPIO Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,GPIO Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,GPIO Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,GPIO Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,GPIO Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,GPIO Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,GPIO Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,GPIO Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,GPIO Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,GPIO Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,GPIO Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,GPIO Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,GPIO Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,GPIO Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x10)++0x03
|
|
line.long 0x00 "PMR0,Peripheral Mux Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x1C)++0x03
|
|
line.long 0x00 "PMR0T,Peripheral Mux Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x20)++0x03
|
|
line.long 0x00 "PMR1,Peripheral Mux Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x2C)++0x03
|
|
line.long 0x00 "PMR1T,Peripheral Mux Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x30)++0x03
|
|
line.long 0x00 "PMR2,Peripheral Mux Register 2"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
wgroup.long (0x000+0x3C)++0x03
|
|
line.long 0x00 "PMR2T,Peripheral Mux Toggle Register 2"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Multiplexer Select pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Multiplexer Select pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Multiplexer Select pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Multiplexer Select pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Multiplexer Select pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Multiplexer Select pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Multiplexer Select pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Multiplexer Select pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Multiplexer Select pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Multiplexer Select pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Multiplexer Select pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Multiplexer Select pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Multiplexer Select pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Multiplexer Select pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Multiplexer Select pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Multiplexer Select pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Multiplexer Select pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Multiplexer Select pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Multiplexer Select pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Multiplexer Select pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Multiplexer Select pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Multiplexer Select pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Multiplexer Select pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Multiplexer Select pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Multiplexer Select pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Multiplexer Select pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Multiplexer Select pin 0" "0,1"
|
|
group.long (0x000+0x40)++0x03
|
|
line.long 0x00 "ODER,Output Driver Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x4C)++0x03
|
|
line.long 0x00 "ODERT,Output Driver Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Driver Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Driver Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driver Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Driver Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driver Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Driver Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driver Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Driver Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driver Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Driver Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driver Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Driver Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driver Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Driver Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driver Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Driver Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driver Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Driver Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driver Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Driver Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driver Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Driver Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driver Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Driver Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driver Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Driver Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driver Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x50)++0x03
|
|
line.long 0x00 "OVR,Output Value Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Value pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Value pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Value pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Value pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Value pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Value pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Value pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Value pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Value pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Value pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Value pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Value pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Value pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Value pin 0" "0,1"
|
|
wgroup.long (0x000+0x5C)++0x03
|
|
line.long 0x00 "OVRT,Output Value Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Output Value pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Value pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Value pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Value pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Value pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Value pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Value pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Value pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Value pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Value pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Value pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Value pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Value pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Value pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Value pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Value pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Value pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Value pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Value pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Value pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Value pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Value pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Value pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Value pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Value pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Value pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Value pin 0" "0,1"
|
|
rgroup.long (0x000+0x60)++0x03
|
|
line.long 0x00 "PVR,Pin Value Register"
|
|
bitfld.long 0x00 26. " P26 ,Pin Value pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " P25 ,Pin Value pin 25" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pin Value pin 24" "Low,High"
|
|
bitfld.long 0x00 23. " P23 ,Pin Value pin 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pin Value pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " P21 ,Pin Value pin 21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pin Value pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " P19 ,Pin Value pin 19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pin Value pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " P17 ,Pin Value pin 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pin Value pin 16" "Low,High"
|
|
bitfld.long 0x00 15. " P15 ,Pin Value pin 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pin Value pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " P13 ,Pin Value pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pin Value pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " P11 ,Pin Value pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pin Value pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " P9 ,Pin Value pin 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pin Value pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " P7 ,Pin Value pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pin Value pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " P5 ,Pin Value pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pin Value pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " P3 ,Pin Value pin 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pin Value pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1 ,Pin Value pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pin Value pin 0" "Low,High"
|
|
group.long (0x000+0x70)++0x03
|
|
line.long 0x00 "PUER,Pull-up Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x7C)++0x03
|
|
line.long 0x00 "PUERT,Pull-up Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-up Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-up Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-up Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-up Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-up Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-up Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-up Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-up Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-up Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-up Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-up Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-up Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-up Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-up Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-up Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-up Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-up Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-up Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-up Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-up Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-up Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-up Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-up Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-up Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-up Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-up Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-up Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x80)++0x03
|
|
line.long 0x00 "PDER,Pull-down Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x8C)++0x03
|
|
line.long 0x00 "PDERT,Pull-down Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Pull-down Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Pull-down Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Pull-down Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Pull-down Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Pull-down Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Pull-down Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Pull-down Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Pull-down Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Pull-down Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Pull-down Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Pull-down Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Pull-down Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Pull-down Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Pull-down Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Pull-down Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Pull-down Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Pull-down Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Pull-down Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Pull-down Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Pull-down Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Pull-down Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Pull-down Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Pull-down Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Pull-down Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Pull-down Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Pull-down Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Pull-down Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0x90)++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x9C)++0x03
|
|
line.long 0x00 "IERT,Interrupt Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Enable pin 0" "Disabled,Enabled"
|
|
group.long (0x000+0xA0)++0x03
|
|
line.long 0x00 "IMR0,Interrupt Mode Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0xAC)++0x03
|
|
line.long 0x00 "IMR0T,Interrupt Mode Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0xB0)++0x03
|
|
line.long 0x00 "IMR1,Interrupt Mode Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0xBC)++0x03
|
|
line.long 0x00 "IMR1T,Interrupt Mode Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Mode Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Mode Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Mode Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Mode Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Mode Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Mode Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Mode Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Mode Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Mode Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Mode Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Mode Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Mode Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Mode Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Mode Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Mode Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Mode Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Mode Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Mode Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Mode Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Mode Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Mode Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Mode Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Mode Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Mode Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Mode Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Mode Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Mode Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0xC0)++0x03
|
|
line.long 0x00 "GFER,Glitch Filter Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
wgroup.long (0x000+0xCC)++0x03
|
|
line.long 0x00 "GFERT,Glitch Filter Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Glitch Filter Enable pin 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Glitch Filter Enable pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Glitch Filter Enable pin 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Glitch Filter Enable pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Glitch Filter Enable pin 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Glitch Filter Enable pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Glitch Filter Enable pin 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Glitch Filter Enable pin 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Glitch Filter Enable pin 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Glitch Filter Enable pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Glitch Filter Enable pin 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Glitch Filter Enable pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Glitch Filter Enable pin 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Glitch Filter Enable pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Glitch Filter Enable pin 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Glitch Filter Enable pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Glitch Filter Enable pin 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Glitch Filter Enable pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Glitch Filter Enable pin 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Glitch Filter Enable pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Glitch Filter Enable pin 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Glitch Filter Enable pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Glitch Filter Enable pin 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Glitch Filter Enable pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Glitch Filter Enable pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Glitch Filter Enable pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Glitch Filter Enable pin 0" "Disabled,Enabled"
|
|
rgroup.long (0x000+0xD0)++0x03
|
|
line.long 0x00 "IFR,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
wgroup.long (0x000+0xD8)++0x03
|
|
line.long 0x00 "IFRC,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " P26 ,Interrupt Flag pin 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " P25 ,Interrupt Flag pin 25" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Interrupt Flag pin 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " P23 ,Interrupt Flag pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Interrupt Flag pin 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " P21 ,Interrupt Flag pin 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Interrupt Flag pin 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " P19 ,Interrupt Flag pin 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Interrupt Flag pin 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " P17 ,Interrupt Flag pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Interrupt Flag pin 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " P15 ,Interrupt Flag pin 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Interrupt Flag pin 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " P13 ,Interrupt Flag pin 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Interrupt Flag pin 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " P11 ,Interrupt Flag pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Interrupt Flag pin 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " P9 ,Interrupt Flag pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Interrupt Flag pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " P7 ,Interrupt Flag pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Interrupt Flag pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " P5 ,Interrupt Flag pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Interrupt Flag pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " P3 ,Interrupt Flag pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Interrupt Flag pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " P1 ,Interrupt Flag pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Interrupt Flag pin 0" "No interrupt,Interrupt"
|
|
group.long (0x000+0x100)++0x03
|
|
line.long 0x00 "ODCR0,Output Driving Capability Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
wgroup.long (0x000+0x10C)++0x03
|
|
line.long 0x00 "ODCR0T,Output Driving Capability Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 0 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 0 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 0 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 0 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 0 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 0 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 0 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 0 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 0 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 0 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 0 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 0 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 0 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 0 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 0 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 0 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 0 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 0 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 0 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 0 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 0 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 0 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 0 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 0 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 0 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 0 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 0 pin 0" "0,1"
|
|
group.long (0x000+0x110)++0x03
|
|
line.long 0x00 "ODCR1,Output Driving Capability Register 1"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
wgroup.long (0x000+0x11C)++0x03
|
|
line.long 0x00 "ODCR1T,Output Driving Capability Toggle Register 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Driving Capability Register Bit 1 pin 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Output Driving Capability Register Bit 1 pin 25" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Driving Capability Register Bit 1 pin 24" "0,1"
|
|
bitfld.long 0x00 23. " P23 ,Output Driving Capability Register Bit 1 pin 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Driving Capability Register Bit 1 pin 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Output Driving Capability Register Bit 1 pin 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Driving Capability Register Bit 1 pin 20" "0,1"
|
|
bitfld.long 0x00 19. " P19 ,Output Driving Capability Register Bit 1 pin 19" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Driving Capability Register Bit 1 pin 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Output Driving Capability Register Bit 1 pin 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Driving Capability Register Bit 1 pin 16" "0,1"
|
|
bitfld.long 0x00 15. " P15 ,Output Driving Capability Register Bit 1 pin 15" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Driving Capability Register Bit 1 pin 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Output Driving Capability Register Bit 1 pin 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Driving Capability Register Bit 1 pin 12" "0,1"
|
|
bitfld.long 0x00 11. " P11 ,Output Driving Capability Register Bit 1 pin 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Driving Capability Register Bit 1 pin 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Output Driving Capability Register Bit 1 pin 9" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Driving Capability Register Bit 1 pin 8" "0,1"
|
|
bitfld.long 0x00 7. " P7 ,Output Driving Capability Register Bit 1 pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Driving Capability Register Bit 1 pin 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Output Driving Capability Register Bit 1 pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Driving Capability Register Bit 1 pin 4" "0,1"
|
|
bitfld.long 0x00 3. " P3 ,Output Driving Capability Register Bit 1 pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Driving Capability Register Bit 1 pin 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Output Driving Capability Register Bit 1 pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Driving Capability Register Bit 1 pin 0" "0,1"
|
|
group.long (0x000+0x130)++0x03
|
|
line.long 0x00 "OSRR0,Output Slew Rate Register 0"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x13C)++0x03
|
|
line.long 0x00 "OSRR0T,Output Slew Rate Toggle Register 0"
|
|
bitfld.long 0x00 26. " P26 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Slew Rate Control Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x160)++0x03
|
|
line.long 0x00 "STER,Schmitt Trigger Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x16C)++0x03
|
|
line.long 0x00 "STERT,Schmitt Trigger Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Schmitt Trigger Enable" "Disabled,Enabled"
|
|
group.long (0x000+0x180)++0x03
|
|
line.long 0x00 "EVER,Event Enable Register"
|
|
setclrfld.long 0x00 26. 0x4 26. 0x8 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x4 25. 0x8 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x4 24. 0x8 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x4 23. 0x8 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x4 22. 0x8 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x4 21. 0x8 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x4 20. 0x8 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x4 19. 0x8 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
wgroup.long (0x000+0x18C)++0x03
|
|
line.long 0x00 "EVERT,Event Enable Toggle Register"
|
|
bitfld.long 0x00 26. " P26 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " P24 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P23 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " P19 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " P18 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P15 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P11 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Event Enable" "Disabled,Enabled"
|
|
rgroup.long (0x000+0x1F8)++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART0"
|
|
base ad:0x40024000
|
|
width 10.
|
|
if ((d.l((ad:0x40024000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40024000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40024000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40024000+0x4))&0x1f)==0xE)||(d.l((ad:0x40024000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x40024000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x40028000
|
|
width 10.
|
|
if ((d.l((ad:0x40028000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40028000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40028000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40028000+0x4))&0x1f)==0xE)||(d.l((ad:0x40028000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
width 10.
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x4002C000
|
|
width 10.
|
|
if ((d.l((ad:0x4002C000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x4002C000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x4002C000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4002C000+0x4))&0x1f)==0xE)||(d.l((ad:0x4002C000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
width 10.
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (!cpuis("ATSAM4L??A"))
|
|
tree "USART3"
|
|
base ad:0x40030000
|
|
width 10.
|
|
if ((d.l((ad:0x40030000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40030000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40030000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,,Hardware Handshaking,Modem,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40030000+0x4))&0x1f)==0xE)||(d.l((ad:0x40030000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
width 10.
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PICOUART (Picopower UART)"
|
|
base ad:0x400F1400
|
|
width 0x09
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 1. " DIS ,PICOUART Disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " EN ,PICOUART Enable" "No effect,Enabled"
|
|
if (d.l(ad:0x400F1400+0x04)&0x03)==0x03
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MATCH ,Data Match"
|
|
bitfld.long 0x00 2. " ACTION ,Action to perform" "Device wake up,Event generation"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SOURCE ,Source Enable Mode" "Wake up and event disable,Wake up or event enable on start bit detection,Wake up or event enable on full frame reception,Wake up or event enable on character recognition"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG,Configuration Register"
|
|
bitfld.long 0x00 2. " ACTION ,Action to perform" "Device wake up,Event generation"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SOURCE ,Source Enable Mode" "Wake up and event disable,Wake up or event enable on start bit detection,Wake up or event enable on full frame reception,Wake up or event enable on character recognition"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 1. " DRDY ,Data Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " EN ,PICOUART Enable Status" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CDATA ,Received Data"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40008000
|
|
width 0x0A
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 8. " FLUSHFIFO ,Flush Fifo Command" "No effect,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
if (((d.l((ad:0x40008000+0x4)))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXFIFOEN ,FIFO in Reception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Peripheral device,4- to 16-bit decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
elif (((data.long((ad:0x40008000+0x4)))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXFIFOEN ,FIFO in Reception Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Peripheral device,4- to 16-bit decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Delay Between Chip Selects"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXFIFOEN ,FIFO in Reception Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Peripheral device,4- to 16-bit decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master/Slave Mode" "Slave,Master"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
if (((d.l((ad:0x40008000+0x4)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((data.long((ad:0x40008000+0x4)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if (((d.l((ad:0x40008000+0x30+0x0)))&0x08)==0x0)
|
|
group.long (0x30+0x0)++0x03
|
|
line.long 0x00 "CSR0,Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long (0x30+0x0)++0x03
|
|
line.long 0x00 "CSR0,Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l((ad:0x40008000+0x30+0x4)))&0x08)==0x0)
|
|
group.long (0x30+0x4)++0x03
|
|
line.long 0x00 "CSR1,Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long (0x30+0x4)++0x03
|
|
line.long 0x00 "CSR1,Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l((ad:0x40008000+0x30+0x8)))&0x08)==0x0)
|
|
group.long (0x30+0x8)++0x03
|
|
line.long 0x00 "CSR2,Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long (0x30+0x8)++0x03
|
|
line.long 0x00 "CSR2,Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if (((d.l((ad:0x40008000+0x30+0xC)))&0x08)==0x0)
|
|
group.long (0x30+0xC)++0x03
|
|
line.long 0x00 "CSR3,Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
group.long (0x30+0xC)++0x03
|
|
line.long 0x00 "CSR3,Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,4 bits,5 bits,6 bits,7 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPCR,Write Protection Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabeld,Enabled"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SPIWPVSRC ,SPI Write Protection Violation Source"
|
|
bitfld.long 0x00 0.--2. " SPIWPVS ,SPI Write Protection Violation Status" ",Protected,SW Reset,WR Protection & SW Reset,WR Accesses on MR/CSRi,Protected/WR on MR or CSRi,SW RST Performed/WR Accesses on MR,Protected/SW RST Performed/Write Accesses on MR"
|
|
rgroup.long 0xF8++0x07
|
|
line.long 0x00 "FEATURES,Features Register"
|
|
bitfld.long 0x00 20. " SWIMPL ,Spurious Write Protection Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " FIFORIMPL ,FIFO in Reception Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BRPBHSB ,Bridge Type is PB to HSB" "No,Yes"
|
|
bitfld.long 0x00 17. " CSNAATIMPL ,CSNAAT Features Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EXTDEC ,External Decoder True" "Not implemented,Implemented"
|
|
hexmask.long.byte 0x00 9.--15. 1. " LENNCONF ,Character Length if not Configurable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LENCONF ,Character Length Configurable" "Not configurable,Configurable"
|
|
bitfld.long 0x00 7. " PHZNCONF ,Phase is Zero if Phase not Configurable" "Non-zero,Zero"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PHCONF ,Phase Configurable" "Not configurable,Configurable"
|
|
bitfld.long 0x00 5. " PPNCONF ,Polarity Positive if Polarity not Configurable" "Negative,Positive"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCONF ,Polarity Configurable" "Not configurable,Configurable"
|
|
bitfld.long 0x00 0.--3. " NCS ,Number of Chip Selects" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TWIM (Two-wire Master Interface)"
|
|
tree "TWIM2"
|
|
base ad:0x40078000
|
|
width 0x08
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " STOP ,Stop the Current Transfer" "No effect,Stop"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SMDIS ,SMBus Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " SMEN ,SMBus Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIS ,Master Disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " MEN ,Master Enable" "No effect,Enable"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 28.--30. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " DATA ,Data Setup and Hold Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " STASTO ,START and STOP Cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HIGH ,Clock High Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOW ,Clock Low Cycles"
|
|
line.long 0x04 "SMBTR,SMBus Timing Register"
|
|
bitfld.long 0x04 28.--31. " EXP ,SMBus Timeout Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " THMAX ,Clock High Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
if ((d.l(ad:0x40078000+0xC)&0x800)==0x800)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMDR,Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 12. " REPSAME ,Transfer is to Same Address as Previous Address" "No,Yes"
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--10. 1. " SADR ,Slave Address"
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMDR,Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
endif
|
|
if ((d.l(ad:0x40078000+0x10)&0x800)==0x800)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NCMDR,Next Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 12. " REPSAME ,Transfer is to Same Address as Previous Address" "No,Yes"
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--10. 1. " SADR ,Slave Address"
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NCMDR,Next Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Received Data"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Data to Transmit"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 17. " HSMCACK ,ACK in HS-mode Master Code Phase Received" "Not received,Received"
|
|
bitfld.long 0x00 16. " MENB ,Master Interface Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Stop Request Accepted" "No effect,Yes"
|
|
bitfld.long 0x00 13. " PECERR ,PEC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TOUT ,Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " ARBLST ,Arbitration Lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DNAK ,NAK in Data Phase Received" "Not received,Received"
|
|
bitfld.long 0x00 8. " ANAK ,NAK in Address Phase Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUSFREE ,Two-wire Bus is Free" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " IDLE ,Master Interface is Idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CCOMP ,Command Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " CRDY ,Ready for More Commands" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,THR Data Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,RHR Data Ready" "Not ready,Ready"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " HSMCACK_set/clr ,ACK in HS-mode Master Code Phase Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " STOP_set/clr ,Stop Request Accepted Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " TOUT_set/clr ,Timeout Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " DNAK_set/clr ,NAK in Data Phase Received Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ANAK_set/clr ,NAK in Address Phase Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " BUSFREE_set/clr ,Two-wire Bus is Free Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " IDLE_set/clr ,Master Interface is Idle Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CCOMP_set/clr ,Command Complete Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CRDY_set/clr ,Ready for More Commands Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,THR Data Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RHR Data Ready Interrupt Mask" "Masked,Not masked"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 17. " HSMCACK ,ACK in HS-mode Master Code Phase Received" "No effect,Clear"
|
|
bitfld.long 0x00 14. " STOP ,Stop Request Accepted" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECERR ,PEC Error" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TOUT ,Timeout" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ARBLST ,Arbitration Lost" "No effect,Clear"
|
|
bitfld.long 0x00 9. " DNAK ,NAK in Data Phase Received" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ANAK ,NAK in Address Phase Received" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCOMP ,Command Complete" "No effect,Clear"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "PR,Parameter Register"
|
|
bitfld.long 0x00 0. " HS ,HS-mode" "Not supported,Supported"
|
|
line.long 0x04 "VR,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "HSCWGR,HS-mode Clock Waveform Generator Register"
|
|
bitfld.long 0x00 28.--30. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " DATA ,Data Setup and Hold Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " STASTO ,START and STOP Cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HIGH ,Clock High Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOW ,Clock Low Cycles"
|
|
line.long 0x04 "SRR,Slew Rate Register"
|
|
bitfld.long 0x04 28.--29. " FILTER ,Input Spike Filter Control" ",,Standard/Fast,Fast plus"
|
|
bitfld.long 0x04 24.--25. " CLSLEW ,Clock Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " CLDRIVEL ,Clock Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "HSSRR,HS-mode Slew Rate Register"
|
|
bitfld.long 0x08 28.--29. " FILTER ,Input Spike Filter Control" ",HS-mode,?..."
|
|
bitfld.long 0x08 24.--25. " CLSLEW ,Clock Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " CLDRIVEH ,Clock Drive Strength HIGH" "0,1,2,3"
|
|
bitfld.long 0x08 16.--18. " CLDRIVEL ,Clock Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
bitfld.long 0x08 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("ATSAM4L??A"))
|
|
tree "TWIM3"
|
|
base ad:0x4007C000
|
|
width 0x08
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " STOP ,Stop the Current Transfer" "No effect,Stop"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SMDIS ,SMBus Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " SMEN ,SMBus Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MDIS ,Master Disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " MEN ,Master Enable" "No effect,Enable"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 28.--30. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " DATA ,Data Setup and Hold Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " STASTO ,START and STOP Cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HIGH ,Clock High Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOW ,Clock Low Cycles"
|
|
line.long 0x04 "SMBTR,SMBus Timing Register"
|
|
bitfld.long 0x04 28.--31. " EXP ,SMBus Timeout Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " THMAX ,Clock High Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
if ((d.l(ad:0x4007C000+0xC)&0x800)==0x800)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMDR,Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 12. " REPSAME ,Transfer is to Same Address as Previous Address" "No,Yes"
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--10. 1. " SADR ,Slave Address"
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMDR,Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
endif
|
|
if ((d.l(ad:0x4007C000+0x10)&0x800)==0x800)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NCMDR,Next Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 12. " REPSAME ,Transfer is to Same Address as Previous Address" "No,Yes"
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--10. 1. " SADR ,Slave Address"
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "NCMDR,Next Command Register"
|
|
bitfld.long 0x00 28.--30. " HSMCODE ,HS-mode Master Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. " HS ,HS-mode" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACKLAST ,ACK Last Master RX Byte" "NACKed,ACKed"
|
|
bitfld.long 0x00 24. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of Data Bytes in Transfer"
|
|
bitfld.long 0x00 15. " VALID ,CMDR Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Send STOP Condition" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " START ,Send START Condition" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TENBIT ,Ten Bit Addressing Mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ ,Transfer Direction" "Transmit,Receive"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Received Data"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Data to Transmit"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 17. " HSMCACK ,ACK in HS-mode Master Code Phase Received" "Not received,Received"
|
|
bitfld.long 0x00 16. " MENB ,Master Interface Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " STOP ,Stop Request Accepted" "No effect,Yes"
|
|
bitfld.long 0x00 13. " PECERR ,PEC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TOUT ,Timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " ARBLST ,Arbitration Lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DNAK ,NAK in Data Phase Received" "Not received,Received"
|
|
bitfld.long 0x00 8. " ANAK ,NAK in Address Phase Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUSFREE ,Two-wire Bus is Free" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " IDLE ,Master Interface is Idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CCOMP ,Command Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " CRDY ,Ready for More Commands" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,THR Data Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,RHR Data Ready" "Not ready,Ready"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " HSMCACK_set/clr ,ACK in HS-mode Master Code Phase Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " STOP_set/clr ,Stop Request Accepted Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " TOUT_set/clr ,Timeout Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " DNAK_set/clr ,NAK in Data Phase Received Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ANAK_set/clr ,NAK in Address Phase Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " BUSFREE_set/clr ,Two-wire Bus is Free Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " IDLE_set/clr ,Master Interface is Idle Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CCOMP_set/clr ,Command Complete Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CRDY_set/clr ,Ready for More Commands Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,THR Data Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RHR Data Ready Interrupt Mask" "Masked,Not masked"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 17. " HSMCACK ,ACK in HS-mode Master Code Phase Received" "No effect,Clear"
|
|
bitfld.long 0x00 14. " STOP ,Stop Request Accepted" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECERR ,PEC Error" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TOUT ,Timeout" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ARBLST ,Arbitration Lost" "No effect,Clear"
|
|
bitfld.long 0x00 9. " DNAK ,NAK in Data Phase Received" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ANAK ,NAK in Address Phase Received" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCOMP ,Command Complete" "No effect,Clear"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "PR,Parameter Register"
|
|
bitfld.long 0x00 0. " HS ,HS-mode" "Not supported,Supported"
|
|
line.long 0x04 "VR,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "HSCWGR,HS-mode Clock Waveform Generator Register"
|
|
bitfld.long 0x00 28.--30. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " DATA ,Data Setup and Hold Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " STASTO ,START and STOP Cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HIGH ,Clock High Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOW ,Clock Low Cycles"
|
|
line.long 0x04 "SRR,Slew Rate Register"
|
|
bitfld.long 0x04 28.--29. " FILTER ,Input Spike Filter Control" ",,Standard/Fast,Fast plus"
|
|
bitfld.long 0x04 24.--25. " CLSLEW ,Clock Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " CLDRIVEL ,Clock Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "HSSRR,HS-mode Slew Rate Register"
|
|
bitfld.long 0x08 28.--29. " FILTER ,Input Spike Filter Control" ",HS-mode,?..."
|
|
bitfld.long 0x08 24.--25. " CLSLEW ,Clock Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " CLDRIVEH ,Clock Drive Strength HIGH" "0,1,2,3"
|
|
bitfld.long 0x08 16.--18. " CLDRIVEL ,Clock Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
bitfld.long 0x08 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "TWIS (Two-wire Slave Interface)"
|
|
tree "TWIMS0"
|
|
base ad:0x40018000
|
|
width 0x08
|
|
if ((d.l(ad:0x40018000+0x00)&0x4000000)==0x0)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 26. " TENBIT ,Ten Bit Address Match" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " ADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SODR ,Stretch Clock on Data Byte Reception" "Not stretched,Stretched"
|
|
bitfld.long 0x00 14. " SOAM ,Stretch Clock on Address Match" "Not stretched,Stretched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUP ,NBYTES Count Up" "Counted down,Counted up"
|
|
bitfld.long 0x00 12. " ACK ,Slave Receiver Data Phase ACK Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMHH ,SMBus Host Header" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SMDA ,SMBus Default Address" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STREN ,Clock Stretch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GCMATCH ,General Call Address Match" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMATCH ,Slave Address Match" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 1. " SMEN ,SMBus Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEN ,Slave Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 26. " TENBIT ,Ten Bit Address Match" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--25. 1. " ADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SODR ,Stretch Clock on Data Byte Reception" "Not stretched,Stretched"
|
|
bitfld.long 0x00 14. " SOAM ,Stretch Clock on Address Match" "Not stretched,Stretched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUP ,NBYTES Count Up" "Counted down,Counted up"
|
|
bitfld.long 0x00 12. " ACK ,Slave Receiver Data Phase ACK Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMHH ,SMBus Host Header" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SMDA ,SMBus Default Address" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STREN ,Clock Stretch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GCMATCH ,General Call Address Match" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMATCH ,Slave Address Match" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 1. " SMEN ,SMBus Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEN ,Slave Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "NBYTES,NBYTES Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NBYTES ,Number of Bytes to Transfer"
|
|
line.long 0x04 "TR,Timing Register"
|
|
bitfld.long 0x04 28.--31. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SUDAT ,Data Setup Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TTOUT ,SMBus TTIMEOUT Cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TLOWS ,SMBus TLOW:SEXT Cycles"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Received Data Byte"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Data Byte to Transmit"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "PECR,Packet Error Check Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Calculated PEC Value"
|
|
line.long 0x04 "SR,Status Register"
|
|
bitfld.long 0x04 23. " BTF ,Byte Transfer Finished" "Not finished,Finished"
|
|
bitfld.long 0x04 22. " REP ,Repeated Start Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STO ,Stop Received" "Not received,Stop"
|
|
bitfld.long 0x04 20. " SMBDAM ,SMBus Default Address Match" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SMBHHM ,SMBus Host Header Address Match" "Not matched,Matched"
|
|
bitfld.long 0x04 17. " GCM ,General Call Match" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SAM ,Slave Address Match" "Not matched,Matched"
|
|
bitfld.long 0x04 14. " BUSERR ,Bus Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SMBPECERR ,SMBus PEC Error" "No error,Error"
|
|
bitfld.long 0x04 12. " SMBTOUT ,SMBus Timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 8. " NAK ,NAK Received" "Not received,Received"
|
|
bitfld.long 0x04 7. " ORUN ,Overrun" "Not received,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 6. " URUN ,Underrun" "Not received,Occurred"
|
|
bitfld.long 0x04 5. " TRA ,Transmitter Mode" "Receiver,Transmitter"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TCOMP ,Transmission Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " SEN ,Slave Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TXRDY ,TX Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RXRDY ,RX Buffer Ready" "Not ready,Ready"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " BTF_set/clr ,Byte Transfer Finished Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " REP_set/clr ,Repeated Start Received Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " STO_set/clr ,Stop Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " GCM_set/clr ,General Call Match Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " SAM_set/clr ,Slave Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " BUSERR_set/clr ,Bus Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " SMBPECERR_set/clr ,SMBus PEC Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " SMBTOUT_set/clr ,SMBus Timeout Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " NAK_set/clr ,NAK Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ORUN_set/clr ,Overrun Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " URUN_set/clr ,Underrun Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " TCOMP_set/clr ,Transmission Complete Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TX Buffer Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RX Buffer Ready Interrupt Mask" "Masked,Not masked"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 23. " BTF ,Byte Transfer Finished" "No effect,Clear"
|
|
bitfld.long 0x00 22. " REP ,Repeated Start Received" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STO ,Stop Received" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SMBDAM ,SMBus Default Address Match" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SMBHHM ,SMBus Host Header Address Match" "No effect,Clear"
|
|
bitfld.long 0x00 17. " GCM ,General Call Match" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SAM ,Slave Address Match" "No effect,Clear"
|
|
bitfld.long 0x00 14. " BUSERR ,Bus Error" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SMBPECERR ,SMBus PEC Error" "No effect,Clear"
|
|
bitfld.long 0x00 12. " SMBTOUT ,SMBus Timeout" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NAK ,NAK Received" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ORUN ,Overrun" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " URUN ,Underrun" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TCOMP ,Transmission Complete" "No effect,Clear"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "PR,Parameter Register"
|
|
bitfld.long 0x00 0. " HS ,HS-mode" "Not supported,Supported"
|
|
line.long 0x04 "VR,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "HSTR,HS-mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HDDAT ,Data Hold Cycles"
|
|
line.long 0x04 "SRR,Slew Rate Register"
|
|
bitfld.long 0x04 28.--29. " FILTER ,Input Spike Filter Control" ",,Standard/Fast,Fast plus"
|
|
bitfld.long 0x04 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "HSSRR,HS-mode Slew Rate Register"
|
|
bitfld.long 0x08 28.--29. " FILTER ,Input Spike Filter Control" ",HS-mode,?..."
|
|
bitfld.long 0x08 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("ATSAM4L??A"))
|
|
tree "TWIMS1"
|
|
base ad:0x4001C000
|
|
width 0x08
|
|
if ((d.l(ad:0x4001C000+0x00)&0x4000000)==0x0)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 26. " TENBIT ,Ten Bit Address Match" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 1. " ADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SODR ,Stretch Clock on Data Byte Reception" "Not stretched,Stretched"
|
|
bitfld.long 0x00 14. " SOAM ,Stretch Clock on Address Match" "Not stretched,Stretched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUP ,NBYTES Count Up" "Counted down,Counted up"
|
|
bitfld.long 0x00 12. " ACK ,Slave Receiver Data Phase ACK Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMHH ,SMBus Host Header" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SMDA ,SMBus Default Address" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STREN ,Clock Stretch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GCMATCH ,General Call Address Match" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMATCH ,Slave Address Match" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 1. " SMEN ,SMBus Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEN ,Slave Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 26. " TENBIT ,Ten Bit Address Match" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--25. 1. " ADR ,Slave Address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SODR ,Stretch Clock on Data Byte Reception" "Not stretched,Stretched"
|
|
bitfld.long 0x00 14. " SOAM ,Stretch Clock on Address Match" "Not stretched,Stretched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUP ,NBYTES Count Up" "Counted down,Counted up"
|
|
bitfld.long 0x00 12. " ACK ,Slave Receiver Data Phase ACK Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECEN ,Packet Error Checking Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SMHH ,SMBus Host Header" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SMDA ,SMBus Default Address" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STREN ,Clock Stretch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GCMATCH ,General Call Address Match" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMATCH ,Slave Address Match" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 1. " SMEN ,SMBus Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEN ,Slave Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "NBYTES,NBYTES Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NBYTES ,Number of Bytes to Transfer"
|
|
line.long 0x04 "TR,Timing Register"
|
|
bitfld.long 0x04 28.--31. " EXP ,Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SUDAT ,Data Setup Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TTOUT ,SMBus TTIMEOUT Cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TLOWS ,SMBus TLOW:SEXT Cycles"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,Received Data Byte"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Data Byte to Transmit"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "PECR,Packet Error Check Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Calculated PEC Value"
|
|
line.long 0x04 "SR,Status Register"
|
|
bitfld.long 0x04 23. " BTF ,Byte Transfer Finished" "Not finished,Finished"
|
|
bitfld.long 0x04 22. " REP ,Repeated Start Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 21. " STO ,Stop Received" "Not received,Stop"
|
|
bitfld.long 0x04 20. " SMBDAM ,SMBus Default Address Match" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SMBHHM ,SMBus Host Header Address Match" "Not matched,Matched"
|
|
bitfld.long 0x04 17. " GCM ,General Call Match" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SAM ,Slave Address Match" "Not matched,Matched"
|
|
bitfld.long 0x04 14. " BUSERR ,Bus Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SMBPECERR ,SMBus PEC Error" "No error,Error"
|
|
bitfld.long 0x04 12. " SMBTOUT ,SMBus Timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 8. " NAK ,NAK Received" "Not received,Received"
|
|
bitfld.long 0x04 7. " ORUN ,Overrun" "Not received,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 6. " URUN ,Underrun" "Not received,Occurred"
|
|
bitfld.long 0x04 5. " TRA ,Transmitter Mode" "Receiver,Transmitter"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TCOMP ,Transmission Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " SEN ,Slave Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TXRDY ,TX Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RXRDY ,RX Buffer Ready" "Not ready,Ready"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " BTF_set/clr ,Byte Transfer Finished Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " REP_set/clr ,Repeated Start Received Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " STO_set/clr ,Stop Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " GCM_set/clr ,General Call Match Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " SAM_set/clr ,Slave Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " BUSERR_set/clr ,Bus Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " SMBPECERR_set/clr ,SMBus PEC Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " SMBTOUT_set/clr ,SMBus Timeout Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " NAK_set/clr ,NAK Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ORUN_set/clr ,Overrun Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " URUN_set/clr ,Underrun Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " TCOMP_set/clr ,Transmission Complete Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TX Buffer Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RX Buffer Ready Interrupt Mask" "Masked,Not masked"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "SCR,Status Clear Register"
|
|
bitfld.long 0x00 23. " BTF ,Byte Transfer Finished" "No effect,Clear"
|
|
bitfld.long 0x00 22. " REP ,Repeated Start Received" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STO ,Stop Received" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SMBDAM ,SMBus Default Address Match" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SMBHHM ,SMBus Host Header Address Match" "No effect,Clear"
|
|
bitfld.long 0x00 17. " GCM ,General Call Match" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SAM ,Slave Address Match" "No effect,Clear"
|
|
bitfld.long 0x00 14. " BUSERR ,Bus Error" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SMBPECERR ,SMBus PEC Error" "No effect,Clear"
|
|
bitfld.long 0x00 12. " SMBTOUT ,SMBus Timeout" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NAK ,NAK Received" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ORUN ,Overrun" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " URUN ,Underrun" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TCOMP ,Transmission Complete" "No effect,Clear"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "PR,Parameter Register"
|
|
bitfld.long 0x00 0. " HS ,HS-mode" "Not supported,Supported"
|
|
line.long 0x04 "VR,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "HSTR,HS-mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HDDAT ,Data Hold Cycles"
|
|
line.long 0x04 "SRR,Slew Rate Register"
|
|
bitfld.long 0x04 28.--29. " FILTER ,Input Spike Filter Control" ",,Standard/Fast,Fast plus"
|
|
bitfld.long 0x04 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "HSSRR,HS-mode Slew Rate Register"
|
|
bitfld.long 0x08 28.--29. " FILTER ,Input Spike Filter Control" ",HS-mode,?..."
|
|
bitfld.long 0x08 8.--9. " DASLEW ,Data Slew Limit" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " DADRIVEL ,Data Drive Strength LOW" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IISC (Inter-IC Sound Controller)"
|
|
base ad:0x40004000
|
|
width 0x0B
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CKEN ,Clocks Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " IWS24 ,IWS TDM Slot Width" "32-bit,24-bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master Clock Mode" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master Clock to fs Ratio" "16 fs,32 fs,48 fs,64 fs,80 fs,96 fs,112 fs,128 fs,144 fs,160 fs,176 fs,192 fs,208 fs,224 fs,240 fs,256 fs,272 fs,288 fs,304 fs,320 fs,336 fs,352 fs,368 fs,384 fs,400 fs,416 fs,432 fs,448 fs,464 fs,480 fs,496 fs,512 fs,528 fs,544 fs,560 fs,576 fs,592 fs,608 fs,624 fs,640 fs,656 fs,672 fs,688 fs,704 fs,720 fs,736 fs,752 fs,768 fs,784 fs,800 fs,816 fs,832 fs,848 fs,864 fs,880 fs,896 fs,912 fs,928 fs,944 fs,960 fs,976 fs,992 fs,1008 fs,1024 fs"
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit Data when Underrun" "Zero sample,Previous sample"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TXDMA ,Single or multiple DMA Channels for Transmitter" "Single,Multiple"
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit Mono" "Stereo,Mono"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back Test Mode" "Normal mode,Test Mode"
|
|
bitfld.long 0x00 9. " RXDMA ,Single or multiple DMA Channels for Receiver" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXMONO ,Receive Mono" "Stereo,Mono"
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data Word Length" "32 bits,24 bits,20 bits,18 bits,16 bits,16 bits compact stereo,8 bits,8 bits compact stereo"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MODE ,Mode" "SLAVE,MASTER"
|
|
line.long 0x04 "SR,Status Register"
|
|
setclrfld.long 0x04 21. 0x8 21. 0x4 21. " TXURCH[1]_set/clr ,Transmit Underrun Channel[1]" "No effect,Error"
|
|
setclrfld.long 0x04 20. 0x8 20. 0x4 20. " TXURCH[0]_set/clr ,Transmit Underrun Channel[0]" "No effect,Error"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x8 9. 0x4 9. " RXORCH[1]_set/clr ,Receive Overrun Channel[1]" "No effect,Error"
|
|
setclrfld.long 0x04 8. 0x8 8. 0x4 8. " RXORCH[0]_set/clr ,Receive Overrun Channel[0]" "No effect,Error"
|
|
textline " "
|
|
setclrfld.long 0x04 6. 0x8 6. 0x4 6. " TXUR_set/clr ,Transmit Underrun" "No effect,Error"
|
|
rbitfld.long 0x04 5. " TXRDY ,Transmit Ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " TXEN ,Transmitter Enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x8 2. 0x4 2. " RXOR_set/clr ,Receive Overrun" "No effect,Error"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " RXRDY ,Receive Ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " RXEN ,Receiver Enabled" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " TXUR_set/clr ,Transmit Underrun Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXOR_set/clr ,Receive Overrun Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Ready Interrupt Mask" "Masked,Not masked"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RHR,Receive Holding Register"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "VERSION,Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "PARAMETER,Module Parameters"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TC (Timer/Counter)"
|
|
tree "TC0"
|
|
base ad:0x40010000
|
|
width 0xA
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40010000+0x0+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x0+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x0+0x04))&0x8000)==0x1)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x0+0x04)))&0x8000)==0x0)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40010000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
elif (((d.l(ad:0x40010000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x0+0x04)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0,Channel 0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40010000+0x40+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x40+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x40+0x04))&0x8000)==0x1)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x40+0x04)))&0x8000)==0x0)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40010000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
elif (((d.l(ad:0x40010000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x40+0x04)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1,Channel 1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40010000+0x80+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x80+0x04))&0x8000)==0x0)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40010000+0x80+0x04))&0x8000)==0x1)&&((d.l(ad:0x40010000+0xE4)&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x80+0x04)))&0x8000)==0x0)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40010000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
elif (((d.l(ad:0x40010000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40010000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40010000+0x80+0x04)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2,Channel 2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Block Registers"
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,MAXimum FILTer" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,InDeX pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,INVerted InDeX" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,INVerted phB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,INVerted phA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,EDGe on PHA count mode" "Both PHA & PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding TRANSparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,SPEED Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,POSition Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA1,TIOA2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4N*"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR,QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " QERR_set/clr ,Quadrature ERRor" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIRCHG_set/clr ,DIRection CHanGe" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " IDX_set/clr ,InDeX" "Disabled,Enabled"
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
endif
|
|
sif cpuis("ATSAM4N*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
rgroup.long 0xF8++0x07
|
|
line.long 0x00 "FEATURES,Features Register"
|
|
bitfld.long 0x00 9. " BRPBHSB ,Bridge type is PB to HSB" "No,Yes"
|
|
bitfld.long 0x00 8. " UPDNIMPL ,Up/down is implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTRSIZE ,Counter size"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("ATSAM4L??C"))
|
|
tree "TC1"
|
|
base ad:0x40014000
|
|
width 0xA
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40014000+0x0+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x0+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x0+0x04))&0x8000)==0x1)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x0+0x04)))&0x8000)==0x0)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0, Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40014000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
elif (((d.l(ad:0x40014000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x0+0x04)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA0,Channel 0 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0,Channel 0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40014000+0x40+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x40+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x40+0x04))&0x8000)==0x1)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x40+0x04)))&0x8000)==0x0)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1, Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40014000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
elif (((d.l(ad:0x40014000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x40+0x04)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA1,Channel 1 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1,Channel 1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enable"
|
|
sif (cpuis("ATASAMA5D36"))
|
|
if ((((d.l(ad:0x40014000+0x80+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x80+0x04))&0x8000)==0x0)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((d.l(ad:0x40014000+0x80+0x04))&0x8000)==0x1)&&((d.l(ad:0x40014000+0xE4)&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x80+0x04)))&0x8000)==0x0)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2, Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35"))
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if (((d.l(ad:0x40014000+0xE4)&0x01)==0x00)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
elif (((d.l(ad:0x40014000+0xE4)&0x01)==0x01)&&((d.l(ad:0x40014000+0x8000)&0x8000)==0x8000))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40014000+0x80+0x04)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RA2,Channel 2 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A"
|
|
endif
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMA5D36"))
|
|
if ((d.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C"
|
|
endif
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2,Channel 2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " ENDRX_set/clr ,End of Receiver Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " ETRGS_set/clr ,External Trigger Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " LDRBS_set/clr ,RB Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " LDRAS_set/clr ,RA Loading Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CPCS_set/clr ,RC Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CPBS_set/clr ,RB Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CPAS_set/clr ,RA Compare Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " LOVRS_set/clr ,Load Overrun Status Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " COVFS_set/clr ,Counter Overflow Status Interrupt Mask" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Block Registers"
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command" "No effect,Assert"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,MAXimum FILTer" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,InDeX pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,INVerted InDeX" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,INVerted phB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,INVerted phA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,EDGe on PHA count mode" "Both PHA & PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding TRANSparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,SPEED Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,POSition Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA1,TIOA2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,None,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,None,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,None,TIOA1,TIOA2"
|
|
endif
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4N*"))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR,QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " QERR_set/clr ,Quadrature ERRor" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " DIRCHG_set/clr ,DIRection CHanGe" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " IDX_set/clr ,InDeX" "Disabled,Enabled"
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
endif
|
|
sif cpuis("ATSAM4N*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36")&&!cpuis("ATSAM4N*"))
|
|
rgroup.long 0xF8++0x07
|
|
line.long 0x00 "FEATURES,Features Register"
|
|
bitfld.long 0x00 9. " BRPBHSB ,Bridge type is PB to HSB" "No,Yes"
|
|
bitfld.long 0x00 8. " UPDNIMPL ,Up/down is implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTRSIZE ,Counter size"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PEVC (Peripheral Event Controller)"
|
|
base ad:0x400A6000
|
|
width 0x0B
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CHSR,Channel Status Register"
|
|
setclrfld.long 0x00 18. 0x4 18. 0x8 18. " CHS18_set/clr ,Channel 18 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x4 17. 0x8 17. " CHS17_set/clr ,Channel 17 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x4 16. 0x8 16. " CHS16_set/clr ,Channel 16 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x4 15. 0x8 15. " CHS15_set/clr ,Channel 15 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x4 14. 0x8 14. " CHS14_set/clr ,Channel 14 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x4 13. 0x8 13. " CHS13_set/clr ,Channel 13 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x4 12. 0x8 12. " CHS12_set/clr ,Channel 12 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " CHS11_set/clr ,Channel 11 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " CHS10_set/clr ,Channel 10 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " CHS9_set/clr ,Channel 9 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " CHS8_set/clr ,Channel 8 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x4 7. 0x8 7. " CHS7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " CHS6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " CHS5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " CHS4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " CHS3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " CHS2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " CHS1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " CHS0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SEV,Software Event Register"
|
|
bitfld.long 0x00 18. " SEV18 ,Software Event 18" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " SEV17 ,Software Event 17" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEV16 ,Software Event 16" "No effect,Trigger"
|
|
bitfld.long 0x00 15. " SEV15 ,Software Event 15" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SEV14 ,Software Event 14" "No effect,Trigger"
|
|
bitfld.long 0x00 13. " SEV13 ,Software Event 13" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEV12 ,Software Event 12" "No effect,Trigger"
|
|
bitfld.long 0x00 11. " SEV11 ,Software Event 11" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEV10 ,Software Event 10" "No effect,Trigger"
|
|
bitfld.long 0x00 9. " SEV9 ,Software Event 9" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SEV8 ,Software Event 8" "No effect,Trigger"
|
|
bitfld.long 0x00 7. " SEV7 ,Software Event 7" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEV6 ,Software Event 6" "No effect,Trigger"
|
|
bitfld.long 0x00 5. " SEV5 ,Software Event 5" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEV4 ,Software Event 4" "No effect,Trigger"
|
|
bitfld.long 0x00 3. " SEV3 ,Software Event 3" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEV2 ,Software Event 2" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " SEV1 ,Software Event 1" "No effect,Trigger"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEV0 ,Software Event 0" "No effect,Trigger"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BUSY,Channel / User Busy"
|
|
bitfld.long 0x00 18. " BUSY18 ,Channel Status 18" "Idle,Busy"
|
|
bitfld.long 0x00 17. " BUSY17 ,Channel Status 17" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY16 ,Channel Status 16" "Idle,Busy"
|
|
bitfld.long 0x00 15. " BUSY15 ,Channel Status 15" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " BUSY14 ,Channel Status 14" "Idle,Busy"
|
|
bitfld.long 0x00 13. " BUSY13 ,Channel Status 13" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BUSY12 ,Channel Status 12" "Idle,Busy"
|
|
bitfld.long 0x00 11. " BUSY11 ,Channel Status 11" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BUSY10 ,Channel Status 10" "Idle,Busy"
|
|
bitfld.long 0x00 9. " BUSY9 ,Channel Status 9" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUSY8 ,Channel Status 8" "Idle,Busy"
|
|
bitfld.long 0x00 7. " BUSY7 ,Channel Status 7" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BUSY6 ,Channel Status 6" "Idle,Busy"
|
|
bitfld.long 0x00 5. " BUSY5 ,Channel Status 5" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BUSY4 ,Channel Status 4" "Idle,Busy"
|
|
bitfld.long 0x00 3. " BUSY3 ,Channel Status 3" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BUSY2 ,Channel Status 2" "Idle,Busy"
|
|
bitfld.long 0x00 1. " BUSY1 ,Channel Status 1" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUSY0 ,Channel Status 0" "Idle,Busy"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRIMR,Trigger Interrupt Mask Register"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " TRIM18 ,Trigger Interrupt Mask 18" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " TRIM17 ,Trigger Interrupt Mask 17" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " TRIM16 ,Trigger Interrupt Mask 16" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " TRIM15 ,Trigger Interrupt Mask 15" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " TRIM14 ,Trigger Interrupt Mask 14" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " TRIM13 ,Trigger Interrupt Mask 13" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " TRIM12 ,Trigger Interrupt Mask 12" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TRIM11 ,Trigger Interrupt Mask 11" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " TRIM10 ,Trigger Interrupt Mask 10" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TRIM9 ,Trigger Interrupt Mask 9" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TRIM8 ,Trigger Interrupt Mask 8" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " TRIM7 ,Trigger Interrupt Mask 7" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " TRIM6 ,Trigger Interrupt Mask 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " TRIM5 ,Trigger Interrupt Mask 5" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " TRIM4 ,Trigger Interrupt Mask 4" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " TRIM3 ,Trigger Interrupt Mask 3" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TRIM2 ,Trigger Interrupt Mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TRIM1 ,Trigger Interrupt Mask 1" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " TRIM0 ,Trigger Interrupt Mask 0" "Masked,Not masked"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRSR,Trigger Status Register"
|
|
bitfld.long 0x00 18. " TRS18 ,Trigger Interrupt Status 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " TRS17 ,Trigger Interrupt Status 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TRS16 ,Trigger Interrupt Status 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " TRS15 ,Trigger Interrupt Status 15" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRS14 ,Trigger Interrupt Status 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " TRS13 ,Trigger Interrupt Status 13" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TRS12 ,Trigger Interrupt Status 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TRS11 ,Trigger Interrupt Status 11" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TRS10 ,Trigger Interrupt Status 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " TRS9 ,Trigger Interrupt Status 9" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRS8 ,Trigger Interrupt Status 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " TRS7 ,Trigger Interrupt Status 7" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRS6 ,Trigger Interrupt Status 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " TRS5 ,Trigger Interrupt Status 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRS4 ,Trigger Interrupt Status 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TRS3 ,Trigger Interrupt Status 3" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TRS2 ,Trigger Interrupt Status 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TRS1 ,Trigger Interrupt Status 1" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRS0 ,Trigger Interrupt Status 0" "Not occurred,Occurred"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TRSCR,Trigger Status Clear Register"
|
|
bitfld.long 0x00 18. " TRSC18 ,Trigger Interrupt Status Clear 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " TRSC17 ,Trigger Interrupt Status Clear 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TRSC16 ,Trigger Interrupt Status Clear 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " TRSC15 ,Trigger Interrupt Status Clear 15" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRSC14 ,Trigger Interrupt Status Clear 14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " TRSC13 ,Trigger Interrupt Status Clear 13" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TRSC12 ,Trigger Interrupt Status Clear 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " TRSC11 ,Trigger Interrupt Status Clear 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TRSC10 ,Trigger Interrupt Status Clear 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TRSC9 ,Trigger Interrupt Status Clear 9" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRSC8 ,Trigger Interrupt Status Clear 8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TRSC7 ,Trigger Interrupt Status Clear 7" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRSC6 ,Trigger Interrupt Status Clear 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TRSC5 ,Trigger Interrupt Status Clear 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TRSC4 ,Trigger Interrupt Status Clear 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TRSC3 ,Trigger Interrupt Status Clear 3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TRSC2 ,Trigger Interrupt Status Clear 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " TRSC1 ,Trigger Interrupt Status Clear 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRSC0 ,Trigger Interrupt Status Clear 0" "No effect,Clear"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "OVIMR,Overrun Interrupt Mask Register"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " OVIM18 ,Overrun Interrupt Mask 18" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " OVIM17 ,Overrun Interrupt Mask 17" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " OVIM16 ,Overrun Interrupt Mask 16" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " OVIM15 ,Overrun Interrupt Mask 15" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " OVIM14 ,Overrun Interrupt Mask 14" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " OVIM13 ,Overrun Interrupt Mask 13" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " OVIM12 ,Overrun Interrupt Mask 12" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " OVIM11 ,Overrun Interrupt Mask 11" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " OVIM10 ,Overrun Interrupt Mask 10" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " OVIM9 ,Overrun Interrupt Mask 9" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " OVIM8 ,Overrun Interrupt Mask 8" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " OVIM7 ,Overrun Interrupt Mask 7" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " OVIM6 ,Overrun Interrupt Mask 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVIM5 ,Overrun Interrupt Mask 5" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " OVIM4 ,Overrun Interrupt Mask 4" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " OVIM3 ,Overrun Interrupt Mask 3" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " OVIM2 ,Overrun Interrupt Mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " OVIM1 ,Overrun Interrupt Mask 1" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " OVIM0 ,Overrun Interrupt Mask 0" "Masked,Not masked"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "OVSR,Overrun Status Register"
|
|
bitfld.long 0x00 18. " OVS18 ,Overrun Interrupt Status 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " OVS17 ,Overrun Interrupt Status 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OVS16 ,Overrun Interrupt Status 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " OVS15 ,Overrun Interrupt Status 15" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OVS14 ,Overrun Interrupt Status 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " OVS13 ,Overrun Interrupt Status 13" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVS12 ,Overrun Interrupt Status 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " OVS11 ,Overrun Interrupt Status 11" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OVS10 ,Overrun Interrupt Status 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " OVS9 ,Overrun Interrupt Status 9" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OVS8 ,Overrun Interrupt Status 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " OVS7 ,Overrun Interrupt Status 7" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OVS6 ,Overrun Interrupt Status 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " OVS5 ,Overrun Interrupt Status 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVS4 ,Overrun Interrupt Status 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " OVS3 ,Overrun Interrupt Status 3" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OVS2 ,Overrun Interrupt Status 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " OVS1 ,Overrun Interrupt Status 1" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OVS0 ,Overrun Interrupt Status 0" "Not occurred,Occurred"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "OVSCR,Overrun Status Clear Register"
|
|
bitfld.long 0x00 18. " OVSC18 ,Overrun Interrupt Status Clear 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " OVSC17 ,Overrun Interrupt Status Clear 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OVSC16 ,Overrun Interrupt Status Clear 16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " OVSC15 ,Overrun Interrupt Status Clear 15" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OVSC14 ,Overrun Interrupt Status Clear 14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " OVSC13 ,Overrun Interrupt Status Clear 13" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVSC12 ,Overrun Interrupt Status Clear 12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " OVSC11 ,Overrun Interrupt Status Clear 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OVSC10 ,Overrun Interrupt Status Clear 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " OVSC9 ,Overrun Interrupt Status Clear 9" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OVSC8 ,Overrun Interrupt Status Clear 8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " OVSC7 ,Overrun Interrupt Status Clear 7" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OVSC6 ,Overrun Interrupt Status Clear 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " OVSC5 ,Overrun Interrupt Status Clear 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVSC4 ,Overrun Interrupt Status Clear 4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " OVSC3 ,Overrun Interrupt Status Clear 3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OVSC2 ,Overrun Interrupt Status Clear 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " OVSC1 ,Overrun Interrupt Status Clear 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OVSC0 ,Overrun Interrupt Status Clear 0" "No effect,Clear"
|
|
if (((d.l((ad:0x400A6000+0x100+0x0)))&0x100)==0x100)
|
|
group.long (0x100+0x0)++0x3
|
|
line.long 0x00 "CHMX0,Channel Multiplexer 0 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x0)++0x3
|
|
line.long 0x00 "CHMX0,Channel Multiplexer 0 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x4)))&0x100)==0x100)
|
|
group.long (0x100+0x4)++0x3
|
|
line.long 0x00 "CHMX1,Channel Multiplexer 1 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x4)++0x3
|
|
line.long 0x00 "CHMX1,Channel Multiplexer 1 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x8)))&0x100)==0x100)
|
|
group.long (0x100+0x8)++0x3
|
|
line.long 0x00 "CHMX2,Channel Multiplexer 2 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x8)++0x3
|
|
line.long 0x00 "CHMX2,Channel Multiplexer 2 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0xC)))&0x100)==0x100)
|
|
group.long (0x100+0xC)++0x3
|
|
line.long 0x00 "CHMX3,Channel Multiplexer 3 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0xC)++0x3
|
|
line.long 0x00 "CHMX3,Channel Multiplexer 3 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x10)))&0x100)==0x100)
|
|
group.long (0x100+0x10)++0x3
|
|
line.long 0x00 "CHMX4,Channel Multiplexer 4 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x10)++0x3
|
|
line.long 0x00 "CHMX4,Channel Multiplexer 4 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x14)))&0x100)==0x100)
|
|
group.long (0x100+0x14)++0x3
|
|
line.long 0x00 "CHMX5,Channel Multiplexer 5 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x14)++0x3
|
|
line.long 0x00 "CHMX5,Channel Multiplexer 5 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x18)))&0x100)==0x100)
|
|
group.long (0x100+0x18)++0x3
|
|
line.long 0x00 "CHMX6,Channel Multiplexer 6 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x18)++0x3
|
|
line.long 0x00 "CHMX6,Channel Multiplexer 6 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x1C)))&0x100)==0x100)
|
|
group.long (0x100+0x1C)++0x3
|
|
line.long 0x00 "CHMX7,Channel Multiplexer 7 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x1C)++0x3
|
|
line.long 0x00 "CHMX7,Channel Multiplexer 7 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x20)))&0x100)==0x100)
|
|
group.long (0x100+0x20)++0x3
|
|
line.long 0x00 "CHMX8,Channel Multiplexer 8 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x20)++0x3
|
|
line.long 0x00 "CHMX8,Channel Multiplexer 8 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x24)))&0x100)==0x100)
|
|
group.long (0x100+0x24)++0x3
|
|
line.long 0x00 "CHMX9,Channel Multiplexer 9 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x24)++0x3
|
|
line.long 0x00 "CHMX9,Channel Multiplexer 9 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x28)))&0x100)==0x100)
|
|
group.long (0x100+0x28)++0x3
|
|
line.long 0x00 "CHMX10,Channel Multiplexer 10 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x28)++0x3
|
|
line.long 0x00 "CHMX10,Channel Multiplexer 10 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x2C)))&0x100)==0x100)
|
|
group.long (0x100+0x2C)++0x3
|
|
line.long 0x00 "CHMX11,Channel Multiplexer 11 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x2C)++0x3
|
|
line.long 0x00 "CHMX11,Channel Multiplexer 11 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x30)))&0x100)==0x100)
|
|
group.long (0x100+0x30)++0x3
|
|
line.long 0x00 "CHMX12,Channel Multiplexer 12 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x30)++0x3
|
|
line.long 0x00 "CHMX12,Channel Multiplexer 12 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x34)))&0x100)==0x100)
|
|
group.long (0x100+0x34)++0x3
|
|
line.long 0x00 "CHMX13,Channel Multiplexer 13 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x34)++0x3
|
|
line.long 0x00 "CHMX13,Channel Multiplexer 13 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x38)))&0x100)==0x100)
|
|
group.long (0x100+0x38)++0x3
|
|
line.long 0x00 "CHMX14,Channel Multiplexer 14 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x38)++0x3
|
|
line.long 0x00 "CHMX14,Channel Multiplexer 14 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x3C)))&0x100)==0x100)
|
|
group.long (0x100+0x3C)++0x3
|
|
line.long 0x00 "CHMX15,Channel Multiplexer 15 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x3C)++0x3
|
|
line.long 0x00 "CHMX15,Channel Multiplexer 15 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x40)))&0x100)==0x100)
|
|
group.long (0x100+0x40)++0x3
|
|
line.long 0x00 "CHMX16,Channel Multiplexer 16 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x40)++0x3
|
|
line.long 0x00 "CHMX16,Channel Multiplexer 16 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x44)))&0x100)==0x100)
|
|
group.long (0x100+0x44)++0x3
|
|
line.long 0x00 "CHMX17,Channel Multiplexer 17 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x44)++0x3
|
|
line.long 0x00 "CHMX17,Channel Multiplexer 17 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
if (((d.l((ad:0x400A6000+0x100+0x48)))&0x100)==0x100)
|
|
group.long (0x100+0x48)++0x3
|
|
line.long 0x00 "CHMX18,Channel Multiplexer 18 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
else
|
|
group.long (0x100+0x48)++0x3
|
|
line.long 0x00 "CHMX18,Channel Multiplexer 18 Register"
|
|
bitfld.long 0x00 8. " SMX ,Software Event Multiplexer" "Not selected,Selected"
|
|
bitfld.long 0x00 0.--5. " EVMX ,Event Multiplexer" "PAD_EVT 0,PAD_EVT 1,PAD_EVT 2,PAD_EVT 3,GCLK 8,GCLK 9,AST - alarm event 0,,AST - periodic event 0,,AST - overflow event,ACIFC - AC0 VINP>VINN,ACIFC - AC1 VINP>VINN,ACIFC - AC2 VINP>VINN,ACIFC - AC3 VINP>VINN,ACIFC - AC0 VINP<VINN,ACIFC - AC1 VINP<VINN,ACIFC - AC2 VINP<VINN,ACIFC - AC3 VINP<VINN,ACIFC - AC0-AC1,ACIFC - AC2-AC3,TC0 - A0,TC0 - A1,TC0 - A2,TC0 - B0,TC0 - B1,TC0 - B2,ADC - match,ADC - end,VREGIFG,PICOUART,?..."
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "EVS0,Event Shaper 0 Register"
|
|
bitfld.long 0x00 18. " IGFON ,Input Glitch Filter Status" "Off,On"
|
|
bitfld.long 0x00 17. " IGFF ,Input Glitch Filter Fall" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IGFR ,Input Glitch Filter Rise" "No event,Event"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "EVS1,Event Shaper 1 Register"
|
|
bitfld.long 0x00 18. " IGFON ,Input Glitch Filter Status" "Off,On"
|
|
bitfld.long 0x00 17. " IGFF ,Input Glitch Filter Fall" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IGFR ,Input Glitch Filter Rise" "No event,Event"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "EVS2,Event Shaper 2 Register"
|
|
bitfld.long 0x00 18. " IGFON ,Input Glitch Filter Status" "Off,On"
|
|
bitfld.long 0x00 17. " IGFF ,Input Glitch Filter Fall" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IGFR ,Input Glitch Filter Rise" "No event,Event"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "EVS3,Event Shaper 3 Register"
|
|
bitfld.long 0x00 18. " IGFON ,Input Glitch Filter Status" "Off,On"
|
|
bitfld.long 0x00 17. " IGFF ,Input Glitch Filter Fall" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IGFR ,Input Glitch Filter Rise" "No event,Event"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "EVS4,Event Shaper 4 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EVS5,Event Shaper 5 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "EVS6,Event Shaper 6 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EVS8,Event Shaper 8 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "EVS10,Event Shaper 10 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "EVS21,Event Shaper 21 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "EVS22,Event Shaper 22 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "EVS23,Event Shaper 23 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "EVS24,Event Shaper 24 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "EVS25,Event Shaper 25 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "EVS26,Event Shaper 26 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "EVS30,Event Shaper 30 Register"
|
|
bitfld.long 0x00 0. " EN ,Event Shaper Enable" "Off,On"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "IGFDR,Input Glitch Filter Divider Register"
|
|
bitfld.long 0x00 0.--3. " IGFDR ,Input Glitch Filter Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "PARAMETER,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TRIGOUT ,Number of Trigger Outputs / Channels / Users"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EVIN ,Number of Event Inputs / Generators"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " EVS_COUNT ,Number of Event Shapers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IGF_COUNT ,Number of Input Glitch Filters"
|
|
line.long 0x04 "VERSION,Version Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION ,Version number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ABDACB (Audio Bit Stream DAC)"
|
|
base ad:0x40064000
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CR, Control Register"
|
|
bitfld.long 0x00 24.--27. " FS ,Sampling Frequency" "8000Hz,11025Hz,12000Hz,16000Hz,22050Hz,24000Hz,32000Hz,44100Hz,48000Hz,?..."
|
|
bitfld.long 0x00 16.--18. " DATAFORMAT ,Data Word Format" "32 bits,24 bits,20 bits,18 bits,16 bits,16 bits stereo,8 bits,8 bits stereo"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MONO ,Mono Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CMOC ,Common Mode Offset Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ALTUPR ,Alternative Upsampling Ratio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWAP ,Swap Channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x40064000))&0x70000)==0x00000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x10000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DATA , Sample Data"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DATA , Sample Data"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x20000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " DATA , Sample Data"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " DATA , Sample Data"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x30000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DATA , Sample Data"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " DATA , Sample Data"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x40000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA , Sample Data"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " DATA , Sample Data"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x50000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " DATA , Sample Data for CH1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA , Sample Data for CH0"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x60000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA , Sample Data"
|
|
line.long 0x04 "SDR1, Sample Data Register 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA , Sample Data"
|
|
elif (((d.l(ad:0x40064000))&0x70000)==0x70000)
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "SDR0, Sample Data Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA , Sample Data for CH1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA , Sample Data for CH0"
|
|
endif
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "VCR0, Volume Control Register 0"
|
|
bitfld.long 0x00 31. " MUTE , Mute" "Not muted,Muted"
|
|
hexmask.long.word 0x00 0.--14. 1. " VOLUME , Volume Control"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "VCR1, Volume Control Register 1"
|
|
bitfld.long 0x00 31. " MUTE , Mute" "Not muted,Muted"
|
|
hexmask.long.word 0x00 0.--14. 1. " VOLUME , Volume Control"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXUR_set/clr , Transmit Underrun" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr , Transmit Ready" "Masked,Not masked"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 2. " TXUR ,Transmit Underrun" "No underrun,Underrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmit Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " BUSY ,ABDACB Busy" "Not busy,Busy"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "SCR, Status Clear Register"
|
|
bitfld.long 0x00 2. " TXUR ,Transmit Underrun" "No effect,Clear"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmit Ready" "No effect,Clear"
|
|
hgroup.long 0x28++0x3
|
|
hide.long 0x00 "PARAMETER, Parameter Register"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
tree.end
|
|
tree "DACC (Digital to Analog Converter Controller)"
|
|
base ad:0x4003C000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DACC_CR,DACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
if (((data.long((ad:0x4003C000+0xE4)))&0x1)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CLKDIV ,DAC Clock Divider for Internal Trigger"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STARTUP ,Startup Time Selection"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 4. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4L*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,Peripheral event,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CLKDIV ,DAC Clock Divider for Internal Trigger"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STARTUP ,Startup Time Selection"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 4. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4L*"))
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,Peripheral event,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "DACC_CDR,DACC Conversion Data Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x0 "DACC_IMR,DACC Interrupt Mask Register"
|
|
sif (!cpuis("ATSAM4L*"))
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXBUFE ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " ENDTX ,End of PDC Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXRDY ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "DACC_ISR,DACC Interrupt Status Register"
|
|
in
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DACC_WPMR,DACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DACC_WPSR,DACC Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "CATB (Capacitive Touch Module)"
|
|
base ad:0x40070000
|
|
width 13.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "CR, Control Register"
|
|
bitfld.long 0x00 31. " SWRST , Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 16.--19. " CHARGET , Charge Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ESAMPLES , Number of Event Samples"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAEN , DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DIFF , Differential Mode" "Normal acquisition,Differential"
|
|
bitfld.long 0x00 5. " CKSEL , Clock Select" "RC,GCLK"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTRES , Internal Resistors" "External,Internal"
|
|
bitfld.long 0x00 3. " ETRIG , Event Triggered Operation" "Normal,Peripheral Event System"
|
|
bitfld.long 0x00 2. " IIDLE , Initialize Idle Value" "CATB,Next value"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUN , Start Operation" "Stopped,Started"
|
|
bitfld.long 0x00 0. " EN , Access Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTCR, Counter Control Register"
|
|
bitfld.long 0x04 28.--30. " REPEAT , Repeat Measurements" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 24.--27. " SPREAD , Spread Spectrum" "Normal,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " TOP , Counter Top Value"
|
|
line.long 0x08 "IDLE, Sensor Idle Level"
|
|
hexmask.long.word 0x08 12.--27. 1. " RIDLE , Integer Sensor Idle"
|
|
hexmask.long.word 0x08 0.--9. 1. " FIDLE , Fractional Sensor Idle"
|
|
rgroup.long 0x0C++0x7
|
|
line.long 0x00 "LEVEL, Sensor Relative Level"
|
|
hexmask.long.byte 0x00 12.--19. 1. " RLEVEL , Integer Sensor Level"
|
|
hexmask.long.word 0x00 0.--9. 1. " FLEVEL , Fractional Sensor Level"
|
|
line.long 0x04 "RAW, Sensor Raw Value"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RAWB , Last Sensor Raw Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RAWA , Current Sensor Raw Value"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 "TIMING, Filter Timing Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " TIDLE , Idle Smoothening"
|
|
hexmask.long.word 0x00 0.--9. 1. " TLEVEL , Relative Level Smoothening"
|
|
line.long 0x04 "THRESH, Threshold Register"
|
|
bitfld.long 0x04 24.--28. " LENGTH , Threshold Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 23. " DIR , Threshold Direction" "Above,Below"
|
|
hexmask.long.byte 0x04 12.--19. 1. " RTHRESH , Integer Threshold Value"
|
|
textline " "
|
|
hexmask.long.word 0x04 2.--11. 1. " FTHRESH , Fractional Threshold Value"
|
|
line.long 0x08 "PINSEL, Pin Selection Register"
|
|
bitfld.long 0x08 0.--4. " PINSEL ,Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "DMA, Direct Memory Access Register"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " OUTTCH_set/clr ,Out-of-Touch" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INTCH_set/clr ,In-touch" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " SAMPLE_set/clr ,Sample Ready" "Masked,Not masked"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "SCR, Status Clear Register"
|
|
bitfld.long 0x00 2. " OUTTCH ,Out-of-Touch" "No effect,Clear"
|
|
bitfld.long 0x00 1. " INTCH ,In-touch" "No effect,Clear"
|
|
bitfld.long 0x00 0. " SAMPLE ,Sample Ready" "No effect,Clear"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "INTCH, In-Touch Status Register"
|
|
sif !cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 31. " INTCH31 , In-Touch 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " INTCH30 , In-Touch 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " INTCH29 , In-Touch 29" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTCH28 , In-Touch 28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " INTCH27 , In-Touch 27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " INTCH26 , In-Touch 26" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " INTCH25 , In-Touch 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " INTCH24 , In-Touch 24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " INTCH23 , In-Touch 23" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTCH22 , In-Touch 22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " INTCH21 , In-Touch 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " INTCH20 , In-Touch 20" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCH19 , In-Touch 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " INTCH18 , In-Touch 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " INTCH17 , In-Touch 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTCH16 , In-Touch 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " INTCH15 , In-Touch 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " INTCH14 , In-Touch 14" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCH13 , In-Touch 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " INTCH12 , In-Touch 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " INTCH11 , In-Touch 11" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTCH10 , In-Touch 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " INTCH9 , In-Touch 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " INTCH8 , In-Touch 8" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCH7 , In-Touch 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INTCH6 , In-Touch 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " INTCH5 , In-Touch 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTCH4 , In-Touch 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " INTCH3 , In-Touch 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INTCH2 , In-Touch 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCH1 , In-Touch 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INTCH0 , In-Touch 0" "Not occurred,Occurred"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "INTCHCLR, In-Touch Status Clear Register"
|
|
sif !cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 31. " INTCHCLR31 , In-Touch Clear 31" "No clear,Clear"
|
|
bitfld.long 0x00 30. " INTCHCLR30 , In-Touch Clear 30" "No clear,Clear"
|
|
bitfld.long 0x00 29. " INTCHCLR29 , In-Touch Clear 29" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTCHCLR28 , In-Touch Clear 28" "No clear,Clear"
|
|
bitfld.long 0x00 27. " INTCHCLR27 , In-Touch Clear 27" "No clear,Clear"
|
|
bitfld.long 0x00 26. " INTCHCLR26 , In-Touch Clear 26" "No clear,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " INTCHCLR25 , In-Touch Clear 25" "No clear,Clear"
|
|
bitfld.long 0x00 24. " INTCHCLR24 , In-Touch Clear 24" "No clear,Clear"
|
|
bitfld.long 0x00 23. " INTCHCLR23 , In-Touch Clear 23" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " INTCHCLR22 , In-Touch Clear 22" "No clear,Clear"
|
|
bitfld.long 0x00 21. " INTCHCLR21 , In-Touch Clear 21" "No clear,Clear"
|
|
bitfld.long 0x00 20. " INTCHCLR20 , In-Touch Clear 20" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCHCLR19 , In-Touch Clear 19" "No clear,Clear"
|
|
bitfld.long 0x00 18. " INTCHCLR18 , In-Touch Clear 18" "No clear,Clear"
|
|
bitfld.long 0x00 17. " INTCHCLR17 , In-Touch Clear 17" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INTCHCLR16 , In-Touch Clear 16" "No clear,Clear"
|
|
bitfld.long 0x00 15. " INTCHCLR15 , In-Touch Clear 15" "No clear,Clear"
|
|
bitfld.long 0x00 14. " INTCHCLR14 , In-Touch Clear 14" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCHCLR13 , In-Touch Clear 13" "No clear,Clear"
|
|
bitfld.long 0x00 12. " INTCHCLR12 , In-Touch Clear 12" "No clear,Clear"
|
|
bitfld.long 0x00 11. " INTCHCLR11 , In-Touch Clear 11" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INTCHCLR10 , In-Touch Clear 10" "No clear,Clear"
|
|
bitfld.long 0x00 9. " INTCHCLR9 , In-Touch Clear 9" "No clear,Clear"
|
|
bitfld.long 0x00 8. " INTCHCLR8 , In-Touch Clear 8" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCHCLR7 , In-Touch Clear 7" "No clear,Clear"
|
|
bitfld.long 0x00 6. " INTCHCLR6 , In-Touch Clear 6" "No clear,Clear"
|
|
bitfld.long 0x00 5. " INTCHCLR5 , In-Touch Clear 5" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTCHCLR4 , In-Touch Clear 4" "No clear,Clear"
|
|
bitfld.long 0x00 3. " INTCHCLR3 , In-Touch Clear 3" "No clear,Clear"
|
|
bitfld.long 0x00 2. " INTCHCLR2 , In-Touch Clear 2" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCHCLR1 , In-Touch Clear 1" "No clear,Clear"
|
|
bitfld.long 0x00 0. " INTCHCLR0 , In-Touch Clear 0" "No clear,Clear"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "OUTTCH, Out-of-Touch Status Register"
|
|
sif !cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 31. " OUTTCH31 , Out-of-Touch 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " OUTTCH30 , Out-of-Touch 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " OUTTCH29 , Out-of-Touch 29" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OUTTCH28 , Out-of-Touch 28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " OUTTCH27 , Out-of-Touch 27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " OUTTCH26 , Out-of-Touch 26" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " OUTTCH25 , Out-of-Touch 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " OUTTCH24 , Out-of-Touch 24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " OUTTCH23 , Out-of-Touch 23" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OUTTCH22 , Out-of-Touch 22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " OUTTCH21 , Out-of-Touch 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " OUTTCH20 , Out-of-Touch 20" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUTTCH19 , Out-of-Touch 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " OUTTCH18 , Out-of-Touch 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " OUTTCH17 , Out-of-Touch 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OUTTCH16 , Out-of-Touch 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " OUTTCH15 , Out-of-Touch 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " OUTTCH14 , Out-of-Touch 14" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUTTCH13 , Out-of-Touch 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " OUTTCH12 , Out-of-Touch 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " OUTTCH11 , Out-of-Touch 11" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUTTCH10 , Out-of-Touch 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " OUTTCH9 , Out-of-Touch 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " OUTTCH8 , Out-of-Touch 8" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUTTCH7 , Out-of-Touch 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " OUTTCH6 , Out-of-Touch 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " OUTTCH5 , Out-of-Touch 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUTTCH4 , Out-of-Touch 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " OUTTCH3 , Out-of-Touch 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " OUTTCH2 , Out-of-Touch 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUTTCH1 , Out-of-Touch 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " OUTTCH0 , Out-of-Touch 0" "Not occurred,Occurred"
|
|
wgroup.long 0x70++0x3
|
|
line.long 0x00 "OUTTCHCLR, Out of Touch Status Clear Register"
|
|
sif !cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 31. " OUTTCHCLR31 , Out-of-Touch 31" "No clear,Clear"
|
|
bitfld.long 0x00 30. " OUTTCHCLR30 , Out-of-Touch 30" "No clear,Clear"
|
|
bitfld.long 0x00 29. " OUTTCHCLR29 , Out-of-Touch 29" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OUTTCHCLR28 , Out-of-Touch 28" "No clear,Clear"
|
|
bitfld.long 0x00 27. " OUTTCHCLR27 , Out-of-Touch 27" "No clear,Clear"
|
|
bitfld.long 0x00 26. " OUTTCHCLR26 , Out-of-Touch 26" "No clear,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " OUTTCHCLR25 , Out-of-Touch 25" "No clear,Clear"
|
|
bitfld.long 0x00 24. " OUTTCHCLR24 , Out-of-Touch 24" "No clear,Clear"
|
|
bitfld.long 0x00 23. " OUTTCHCLR23 , Out-of-Touch 23" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OUTTCHCLR22 , Out-of-Touch 22" "No clear,Clear"
|
|
bitfld.long 0x00 21. " OUTTCHCLR21 , Out-of-Touch 21" "No clear,Clear"
|
|
bitfld.long 0x00 20. " OUTTCHCLR20 , Out-of-Touch 20" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUTTCHCLR19 , Out-of-Touch 19" "No clear,Clear"
|
|
bitfld.long 0x00 18. " OUTTCHCLR18 , Out-of-Touch 18" "No clear,Clear"
|
|
bitfld.long 0x00 17. " OUTTCHCLR17 , Out-of-Touch 17" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " OUTTCHCLR16 , Out-of-Touch 16" "No clear,Clear"
|
|
bitfld.long 0x00 15. " OUTTCHCLR15 , Out-of-Touch 15" "No clear,Clear"
|
|
bitfld.long 0x00 14. " OUTTCHCLR14 , Out-of-Touch 14" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUTTCHCLR13 , Out-of-Touch 13" "No clear,Clear"
|
|
bitfld.long 0x00 12. " OUTTCHCLR12 , Out-of-Touch 12" "No clear,Clear"
|
|
bitfld.long 0x00 11. " OUTTCHCLR11 , Out-of-Touch 11" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUTTCHCLR10 , Out-of-Touch 10" "No clear,Clear"
|
|
bitfld.long 0x00 9. " OUTTCHCLR9 , Out-of-Touch 9" "No clear,Clear"
|
|
bitfld.long 0x00 8. " OUTTCHCLR8 , Out-of-Touch 8" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUTTCHCLR7 , Out-of-Touch 7" "No clear,Clear"
|
|
bitfld.long 0x00 6. " OUTTCHCLR6 , Out-of-Touch 6" "No clear,Clear"
|
|
bitfld.long 0x00 5. " OUTTCHCLR5 , Out-of-Touch 5" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUTTCHCLR4 , Out-of-Touch 4" "No clear,Clear"
|
|
bitfld.long 0x00 3. " OUTTCHCLR3 , Out-of-Touch 3" "No clear,Clear"
|
|
bitfld.long 0x00 2. " OUTTCHCLR2 , Out-of-Touch 2" "No clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUTTCHCLR1 , Out-of-Touch 1" "No clear,Clear"
|
|
bitfld.long 0x00 0. " OUTTCHCLR0 , Out-of-Touch 0" "No clear,Clear"
|
|
rgroup.long 0xF8++0x7
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
bitfld.long 0x00 16.--19. " FRACTIONAL ,Number of Fractional bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NSTATUS , Number of Status bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NPINS , Number of Pins"
|
|
line.long 0x04 "VERSION, Module Version"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40068000
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " KEY ,Security Key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY_set/clr ,Data Ready" "Masked,Not masked"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x00 "ISR,TRNG Interrupt Status Register"
|
|
in
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "ODATA,TRNG Output Data Register"
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
tree.end
|
|
tree "GLOC (Glue Logic Controller)"
|
|
base ad:0x40060000
|
|
sif (cpuis("ATSAM4LC?C")||cpuis("ATSAM4LC?B")||cpuis("ATSAM4LS?C")||cpuis("ATSAM4LS?B"))
|
|
width 11.
|
|
group.long 0x0++0x7
|
|
line.long 0x00 "CR0, Control Register 0"
|
|
bitfld.long 0x00 31. " FILTEN , Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AEN[3] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AEN[2] , Enable IN Inputs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AEN[1] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AEN[0] , Enable IN Inputs" "Disabled,Enabled"
|
|
line.long 0x04 "TRUTH0, Truth Table Register 0"
|
|
hexmask.long.word 0x04 0.--15. 1. " TRUTH , Truth Table Value"
|
|
group.long 0x8++0x7
|
|
line.long 0x00 "CR1, Control Register 1"
|
|
bitfld.long 0x00 31. " FILTEN , Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AEN[3] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AEN[2] , Enable IN Inputs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AEN[1] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AEN[0] , Enable IN Inputs" "Disabled,Enabled"
|
|
line.long 0x04 "TRUTH1, Truth Table Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " TRUTH , Truth Table Value"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUTS , Lookup Table Units Implemented"
|
|
line.long 0x04 "VERSION, Module Version"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
elif (cpuis("ATSAM4LC?A")||cpuis("ATSAM4LS?A"))
|
|
width 11.
|
|
group.long 0x0++0x7
|
|
line.long 0x00 "CR0, Control Register 0"
|
|
bitfld.long 0x00 31. " FILTEN , Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AEN[3] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " AEN[2] , Enable IN Inputs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AEN[1] , Enable IN Inputs" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AEN[0] , Enable IN Inputs" "Disabled,Enabled"
|
|
line.long 0x04 "TRUTH0, Truth Table Register 0"
|
|
hexmask.long.word 0x04 0.--15. 1. " TRUTH , Truth Table Value"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUTS , Lookup Table Units Implemented"
|
|
line.long 0x04 "VERSION, Module Version"
|
|
hexmask.long.word 0x04 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "ACIFC (Analog Comparator Interface)"
|
|
base ad:0x40040000
|
|
sif (cpuis("ATSAM4LC?C")||cpuis("ATSAM4LS?C"))
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRL, Control Register"
|
|
bitfld.long 0x00 7. " ACTEST ,Analog Comparator Test Mode" "ACIFC,AC test register"
|
|
bitfld.long 0x00 5. " ESTART ,Peripheral Event Start Single Comparison" "No effect,Started"
|
|
bitfld.long 0x00 4. " USTART ,User Start Single Comparison" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVENTEN ,Peripheral Event Trigger Enable" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " EN ,ACIFC Enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 27. " WFCS3 ,Window 3 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 26. " WFCS2 ,Window 2 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 25. " WFCS1 ,Window 1 Mode Current Status" "Outside,Inside"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WFCS0 ,Window 0 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 15. " ACRDY7 ,AC 7 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 14. " ACCS7 ,AC 7 Current Comparison Status" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACRDY6 ,AC 6 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " ACCS6 ,AC 6 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 11. " ACRDY5 ,AC 5 Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ACCS5 ,AC 5 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 9. " ACRDY4 ,AC 4 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " ACCS4 ,AC 4 Current Comparison Status" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACRDY3 ,AC 3 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ACCS3 ,AC 3 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 5. " ACRDY2 ,AC 2 Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACCS2 ,AC 2 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 3. " ACRDY1 ,AC 1 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ACCS1 ,AC 1 Current Comparison Status" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACRDY0 ,AC 0 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ACCS0 ,AC 0 Current Comparison Status" "Lower,Greater"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " WFINT3_set/clr ,Window 3 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " WFINT2_set/clr ,Window 2 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " WFINT1_set/clr ,Window 1 Mode Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " WFINT0_set/clr ,Window 0 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " SUTINT7_set/clr ,AC 7 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " ACINT7_set/clr ,AC 7 Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUTINT6_set/clr ,AC 6 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ACINT6_set/clr ,AC 6 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUTINT5_set/clr ,AC 5 Startup Time Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ACINT5_set/clr ,AC 5 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUTINT4_set/clr ,AC 4 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ACINT4_set/clr ,AC 4 Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " SUTINT3_set/clr ,AC 3 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ACINT3 ,AC 3 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " SUTINT2_set/clr ,AC 2 Startup Time Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ACINT2_set/clr ,AC 2 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ACINT1_set/clr ,AC 1 Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " SUTINT0_set/clr ,AC 0 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACINT0_set/clr ,AC 0 Interrupt Status" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "ISR, Interrupt Status Register"
|
|
bitfld.long 0x00 27. " WFINT3 ,Window 3 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WFINT2 ,Window 2 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WFINT1 ,Window 1 Mode Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SUTINT7 ,AC 7 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " ACINT7 ,AC 7 Interrupt Status" "No normal mode,Normal mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SUTINT6 ,AC 6 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " ACINT6 ,AC 6 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 11. " SUTINT5 ,AC 5 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ACINT5 ,AC 5 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 9. " SUTINT4 ,AC 4 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ACINT4 ,AC 4 Interrupt Status" "No normal mode,Normal mode"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUTINT3 ,AC 3 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ACINT3 ,AC 3 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 5. " SUTINT2 ,AC 2 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACINT2 ,AC 2 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No normal mode,Normal mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No normal mode,Normal mode"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "ICR, Interrupt Status Clear Register"
|
|
bitfld.long 0x00 27. " WFINT3 ,Window 3 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 26. " WFINT2 ,Window 2 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 25. " WFINT1 ,Window 1 Mode Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 15. " SUTINT7 ,AC 7 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 14. " ACINT7 ,AC 7 Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SUTINT6 ,AC 6 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 12. " ACINT6 ,AC 6 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 11. " SUTINT5 ,AC 5 Startup Time Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ACINT5 ,AC 5 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SUTINT4 ,AC 4 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 8. " ACINT4 ,AC 4 Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUTINT3 ,AC 3 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ACINT3 ,AC 3 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 5. " SUTINT2 ,AC 2 Startup Time Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACINT2 ,AC 2 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No effect,Clear"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TR, Test Register"
|
|
bitfld.long 0x00 7. " ACTEST7 ,AC 7 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 6. " ACTEST6 ,AC 6 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 5. " ACTEST5 ,AC 5 Output Override Value" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACTEST4 ,AC 4 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 3. " ACTEST3 ,AC 3 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 2. " ACTEST2 ,AC 2 Output Override Value" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTEST1 ,AC 1 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 0. " ACTEST0 ,AC 0 Output Override Value" "No override,Override"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
bitfld.long 0x00 19. " WIMPL3 , Window 3 Mode Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 18. " WIMPL2 , Window 2 Mode Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 17. " WIMPL1 , Window 1 Mode Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WIMPL0 , Window 0 Mode Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 7. " ACIMPL7 , Analog Comparator 7 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " ACIMPL6 , Analog Comparator 6 Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ACIMPL5 , Analog Comparator 5 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " ACIMPL4 , Analog Comparator 4 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 3. " ACIMPL3 , Analog Comparator 3 Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACIMPL2 , Analog Comparator 2 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " ACIMPL1 , Analog Comparator 1 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " ACIMPL0 , Analog Comparator 0 Implemented" "Not implemented,Implemented"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "CONFW0, Window 0 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "CONFW1, Window 1 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "CONFW2, Window 2 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "CONFW3, Window 3 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "CONF0, AC 0 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "CONF1, AC 1 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "CONF2, AC 2 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "CONF3, AC 3 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "CONF4, AC 4 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "CONF5, AC 5 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "CONF6, AC 6 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "CONF7, AC 7 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
elif (cpuis("ATSAM4LC?B")||cpuis("ATSAM4LS?B"))
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRL, Control Register"
|
|
bitfld.long 0x00 7. " ACTEST ,Analog Comparator Test Mode" "ACIFC,AC test register"
|
|
bitfld.long 0x00 5. " ESTART ,Peripheral Event Start Single Comparison" "No effect,Started"
|
|
bitfld.long 0x00 4. " USTART ,User Start Single Comparison" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVENTEN ,Peripheral Event Trigger Enable" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " EN ,ACIFC Enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 25. " WFCS1 ,Window 1 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 24. " WFCS0 ,Window 0 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 7. " ACRDY3 ,AC 3 Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACCS3 ,AC 3 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 5. " ACRDY2 ,AC 2 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ACCS2 ,AC 2 Current Comparison Status" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACRDY1 ,AC 1 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ACCS1 ,AC 1 Current Comparison Status" "Lower,Greater"
|
|
bitfld.long 0x00 1. " ACRDY0 ,AC 0 Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACCS0 ,AC 0 Current Comparison Status" "Lower,Greater"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " WFINT1_set/clr ,Window 1 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " WFINT0_set/clr ,Window 0 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " SUTINT3_set/clr ,AC 3 Startup Time Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ACINT3 ,AC 3 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " SUTINT2_set/clr ,AC 2 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ACINT2_set/clr ,AC 2 Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ACINT1_set/clr ,AC 1 Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " SUTINT0_set/clr ,AC 0 Startup Time Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACINT0_set/clr ,AC 0 Interrupt Status" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "ISR, Interrupt Status Register"
|
|
bitfld.long 0x00 25. " WFINT1 ,Window 1 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SUTINT3 ,AC 3 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACINT3 ,AC 3 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 5. " SUTINT2 ,AC 2 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ACINT2 ,AC 2 Interrupt Status" "No normal mode,Normal mode"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No normal mode,Normal mode"
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No normal mode,Normal mode"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "ICR, Interrupt Status Clear Register"
|
|
bitfld.long 0x00 25. " WFINT1 ,Window 1 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 7. " SUTINT3 ,AC 3 Startup Time Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACINT3 ,AC 3 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 5. " SUTINT2 ,AC 2 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ACINT2 ,AC 2 Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No effect,Clear"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TR, Test Register"
|
|
bitfld.long 0x00 3. " ACTEST3 ,AC 3 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 2. " ACTEST2 ,AC 2 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 1. " ACTEST1 ,AC 1 Output Override Value" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACTEST0 ,AC 0 Output Override Value" "No override,Override"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
bitfld.long 0x00 17. " WIMPL1 , Window 1 Mode Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 16. " WIMPL0 , Window 0 Mode Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 3. " ACIMPL3 , Analog Comparator 3 Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACIMPL2 , Analog Comparator 2 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " ACIMPL1 , Analog Comparator 1 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " ACIMPL0 , Analog Comparator 0 Implemented" "Not implemented,Implemented"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "CONFW0, Window 0 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "CONFW1, Window 1 Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "CONF0, AC 0 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "CONF1, AC 1 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "CONF2, AC 2 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "CONF3, AC 3 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
width 0xB
|
|
elif (cpuis("ATSAM4LC?A")||cpuis("ATSAM4LS?A"))
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRL, Control Register"
|
|
bitfld.long 0x00 7. " ACTEST ,Analog Comparator Test Mode" "ACIFC,AC test register"
|
|
bitfld.long 0x00 5. " ESTART ,Peripheral Event Start Single Comparison" "No effect,Started"
|
|
bitfld.long 0x00 4. " USTART ,User Start Single Comparison" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVENTEN ,Peripheral Event Trigger Enable" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " EN ,ACIFC Enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 24. " WFCS0 ,Window 0 Mode Current Status" "Outside,Inside"
|
|
bitfld.long 0x00 3. " ACRDY1 ,AC 1 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ACCS1 ,AC 1 Current Comparison Status" "Lower,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACRDY0 ,AC 0 Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ACCS0 ,AC 0 Current Comparison Status" "Lower,Greater"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " WFINT0_set/clr ,Window 0 Mode Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ACINT1_set/clr ,AC 1 Interrupt Status" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " SUTINT0_set/clr ,AC 0 Startup Time Interrupt Status" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACINT0_set/clr ,AC 0 Interrupt Status" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "ISR, Interrupt Status Register"
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No normal mode,Normal mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No normal mode,Normal mode"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "ICR, Interrupt Status Clear Register"
|
|
bitfld.long 0x00 24. " WFINT0 ,Window 0 Mode Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 3. " SUTINT1 ,AC 1 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ACINT1 ,AC 1 Interrupt Status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUTINT0 ,AC 0 Startup Time Interrupt Status" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACINT0 ,AC 0 Interrupt Status" "No effect,Clear"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TR, Test Register"
|
|
bitfld.long 0x00 1. " ACTEST1 ,AC 1 Output Override Value" "No override,Override"
|
|
bitfld.long 0x00 0. " ACTEST0 ,AC 0 Output Override Value" "No override,Override"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "PARAMETER, Parameter Register"
|
|
bitfld.long 0x00 1. " ACIMPL1 , Analog Comparator 1 Implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " ACIMPL0 , Analog Comparator 0 Implemented" "Not implemented,Implemented"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "CONFW, Window Configuration Register"
|
|
bitfld.long 0x00 16. " WFEN ,Window Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WEVEN ,Window Peripheral Event Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " WEVSRC ,Peripheral Event Source Selection for Window Mode" "ACWOUT rising edge,ACWOUT falling edge,ACWOUT rising or falling edge,Inside window,Outside window,Measure done,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WIS ,Window Mode Interrupt Settings" "Inside the window,Outside the window,ACWOUT,Done,Entered the window,Left the window,?..."
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "CONF0, AC 0 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "CONF1, AC 1 Configuration Register"
|
|
bitfld.long 0x00 27. " ALWAYSON ,Always On" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FAST ,Fast Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " HYS ,Hysteresis Voltage Value" "0,25,50,75"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENP ,Peripheral Event Enable Positive" "Not output,Output"
|
|
bitfld.long 0x00 16. " EVENN ,Peripheral Event Enable Negative" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " INSELN ,Negative Input Select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Analog Comparator Mode" "Off,Continuous measurement,User triggered single,Peripheral event"
|
|
bitfld.long 0x00 0.--1. " IS ,Interrupt Settings" "Greater,Lower,ACOUT,Comparison done"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
width 0xB
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
endif
|
|
tree.end
|
|
tree "ADCIFE (ADC Interface)"
|
|
base ad:0x40038000
|
|
width 11.
|
|
wgroup.long 0x00++0x7
|
|
line.long 0x00 "CR, Control Register"
|
|
bitfld.long 0x00 11. " BGREQDIS ,Bandgap buffer request disable" "No effect,Yes"
|
|
bitfld.long 0x00 10. " BGREQEN ,Bandgap buffer request enable" "No effect,Enable"
|
|
bitfld.long 0x00 9. " DIS ,ADCIFE disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EN ,ADCIFE enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " REFBUFDIS ,Reference buffer disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " REFBUFEN ,Reference buffer enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STRIG ,Sequencer trigger" "No effect,Event"
|
|
bitfld.long 0x00 2. " TSTART ,Internal timer start bit" "No effect,Start"
|
|
bitfld.long 0x00 1. " TSTOP ,Internal timer stop bit" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No effect,Reset"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CFG, Configuration Register"
|
|
bitfld.long 0x00 8.--10. " PRESCAL , Prescaler Rate Slection" "4,8,16,32,64,128,256,512"
|
|
bitfld.long 0x00 6. " CLKSEL , Clock Selection for sequencer/ADC cell" "Generic,ABP"
|
|
bitfld.long 0x00 4.--5. " SPEED , ADC current reduction" "300ksps,225ksps,150ksps,75ksps"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " REFSEL , ADC Reference selection" "Internal 1.0V,0.625,Reference 1,Reference 2,VCC/2,VCC/2,VCC/2,VCC/2"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 30. " BGREQ ,Bandgap buffer request Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " REFBUF ,Reference Buffer Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CBUSY ,Conversion busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SBUSY ,Sequencer busy" "Not busy,Busy"
|
|
bitfld.long 0x00 25. " TBUSY ,Timer busy" "Not busy,Busy"
|
|
bitfld.long 0x00 24. " EN ,Enable Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TTO ,Timer time-out" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " SMTRG ,Sequencer missed trigger event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " WM ,Window monitor" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOVR ,Sequencer last converted value overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " SEOC ,Sequencer end of conversion" "Not occurred,Occurred"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "SCR, Status Clear Register"
|
|
bitfld.long 0x00 5. " TTO ,Timer time-out" "No effect,Clear"
|
|
bitfld.long 0x00 3. " SMTRG ,Sequencer missed trigger event" "No effect,Clear"
|
|
bitfld.long 0x00 2. " WM ,Window monitor" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOVR ,Sequencer last converted value overrun" "No effect,Clear"
|
|
bitfld.long 0x00 0. " SEOC ,Sequencer end of conversion" "No effect,Clear"
|
|
if (((d.l(ad:0x40038000+0x14))&0xC004)==0xC004)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "Vsingle = 0.9*Vref,Pad Ground,Vcalib3 = Vref/10,Reference Ground,Not used,Vcalib3 = Vref/10,Not used,Pad Ground"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground,Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0xC000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "Not used,Pad Ground,Not used,Not used,Not used,Not used,Not used,Pad Ground"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground,Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0x8004)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "Vsingle = 0.9*Vref,Pad Ground,Vcalib3 = Vref/10,Reference Ground,Not used,Vcalib3 = Vref/10,Not used,Pad Ground"
|
|
textline " "
|
|
sif cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,,,,,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
elif cpuis("ATSAM4L*B")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
else
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
endif
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0x8000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "Not used,Pad Ground,Not used,Not used,Not used,Not used,Not used,Pad Ground"
|
|
textline " "
|
|
sif cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,,,,,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
elif cpuis("ATSAM4L*B")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
else
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
endif
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0x4004)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "primary_anahot_0,primary_anahot_1,primary_anahot_2,primary_anahot_3,primary_anahot_4,primary_anahot_5,primary_anahot_6,primary_anahot_7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground,Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0x4000)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "primary_anahot_0 -> ground,primary_anahot_1 -> ground,primary_anahot_2 -> ground,primary_anahot_3 -> ground,primary_anahot_4 -> ground,primary_anahot_5 -> ground,primary_anahot_6 -> ground,primary_anahot_7 -> ground"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground,Not used,Bandgap,Scaled Vcc,DAC internal,Not used,Not used,Vsingle = 0.9*Vref,Reference Ground"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
elif (((d.l(ad:0x40038000+0x14))&0xC004)==0x0004)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "primary_anahot_0,primary_anahot_1,primary_anahot_2,primary_anahot_3,primary_anahot_4,primary_anahot_5,primary_anahot_6,primary_anahot_7"
|
|
textline " "
|
|
sif cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,,,,,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
elif cpuis("ATSAM4L*B")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
else
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
endif
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SEQCFG, Sequencer Configuration Register"
|
|
bitfld.long 0x00 28.--30. " ZOOMRANGE ,Zoom shift/unipolar reference source selection" "Vref,Vdd/4,Vdd/2,3*Vdd/4,0.9*Vref,0.9*Vref,0.9*Vref,0.9*Vref"
|
|
bitfld.long 0x00 20.--22. " MUXNEG ,MUX selection on Negative ADC input channel" "primary_anahot_0 -> ground,primary_anahot_1 -> ground,primary_anahot_2 -> ground,primary_anahot_3 -> ground,primary_anahot_4 -> ground,primary_anahot_5 -> ground,primary_anahot_6 -> ground,primary_anahot_7 -> ground"
|
|
textline " "
|
|
sif cpuis("ATSAM4L*A")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,,,,,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
elif cpuis("ATSAM4L*B")
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,,,,,,,,,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
else
|
|
bitfld.long 0x00 16.--19. " MUXPOS ,MUX selection on Positive ADC input channel" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,Bandgap"
|
|
bitfld.long 0x00 14.--15. " INTERNAL ,Internal Voltage Sources Selection" "Primary/Secondary,Internal,Primary/Secondary,Internal"
|
|
endif
|
|
bitfld.long 0x00 12. " RES ,Resolution" "12,8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRGSEL ,Trigger selection" "Software,Internal ADC timer,Internal trigger source,Continuous mode,External trigger pin rising edge,External trigger pin falling edge,External trigger pin both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " GCOMP ,Gain Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " GAIN ,Gain factor" "1,2,4,8,16,32,64,0.5"
|
|
bitfld.long 0x00 2. " BIPOLAR ,Bipolar Mode" "Differential,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWLA ,Half Word Left Adjust" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "CDMA, Configuration Direct Memory Access"
|
|
endif
|
|
group.long 0x1C++0xF
|
|
line.long 0x00 "TIM, Timing Configuration Register"
|
|
bitfld.long 0x00 8. " ENSTUP , Enable Startup" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " STARTUP , Startup time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x04 "ITIMER, Internal Timer Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ITMC , Internal Timer Max Counter"
|
|
line.long 0x08 "WCFG, Window Monitor Configuration"
|
|
bitfld.long 0x08 12.--14. " WM , Window Monitor Mode" "OFF,1,2,3,4,?..."
|
|
line.long 0x0C "WTH, Window Monitor Threshold Configuration"
|
|
hexmask.long.word 0x0C 16.--27. 1. " HT , High Threshold"
|
|
hexmask.long.word 0x0C 0.--11. 1. " LT , Low Threshold"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "LCV, Sequencer Last Converted Value"
|
|
bitfld.long 0x00 20.--22. " LCNC , Last converted negative channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " LCPC , Last converted positive channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " LCV , Last converted value"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TTO_set/clr ,Timer time-out" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " SMTRG_set/clr ,Sequencer missed trigger event" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " WM_set/clr ,Window monitor" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVR_set/clr ,Sequencer last converted value overrun" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " SEOC_set/clr ,Sequencer end of conversion" "Masked,Not masked"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "CALIB, Calibration Register"
|
|
bitfld.long 0x00 16. " FCD , Flash Calibration Done" "Power-on-reset,Any reset"
|
|
bitfld.long 0x00 12.--15. " BIASCAL , Bias calibration" "4.1,4.85,5.6,6.35,5.2,5.95,6.7,7.45,5.5,5.5,5.5,5.5,6.6,6.6,6.6,6.6"
|
|
bitfld.long 0x00 8. " BIASSEL , Select bias mode" "Mixed,Bandgap"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CALIB , Calibration value"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version number"
|
|
line.long 0x04 "PARAMETER, Parameter Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " N , Number of channels"
|
|
tree.end
|
|
sif (!(cpuis("ATSAM4LS*")))
|
|
tree "LCDCA (LCD Controller)"
|
|
base ad:0x40080000
|
|
width 8.
|
|
wgroup.long 0x00++0xB
|
|
line.long 0x00 "CR, Control Register"
|
|
bitfld.long 0x00 14. " CSTOP , Circular Shift Stop" "No stop,Stop"
|
|
bitfld.long 0x00 13. " CSTART , Circular Shift Start" "No start,Start"
|
|
bitfld.long 0x00 12. " BSTOP , Blinking Stop" "No stop,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSTART , Blinking Start" "No start,Start"
|
|
bitfld.long 0x00 10. " WEN , Wake up Enable" "No effect,Enable"
|
|
bitfld.long 0x00 9. " WDIS , Wake up Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CDM , Clear Display Memory" "No clear,Clear"
|
|
bitfld.long 0x00 7. " FC2EN , Frame Counter 2 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 6. " FC2DIS , Frame Counter 2 Disable" "No effect,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FC1EN , Frame Counter 1 Enable" "No effect,Enable"
|
|
bitfld.long 0x00 4. " FC1DIS , Frame Counter 1 Disable" "No effect,Yes"
|
|
bitfld.long 0x00 3. " FC0EN , Frame Counter 0 Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FC0DIS , Frame Counter 0 Disable" "No effect,Yes"
|
|
bitfld.long 0x00 1. " EN , Enable" "No effect,Enable"
|
|
bitfld.long 0x00 0. " DIS , Disable" "No effect,Yes"
|
|
line.long 0x04 "CFG, Configuration Register"
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x04 24.--29. " NSU , Number of Segment Terminals in Use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,?..."
|
|
elif cpuis("ATSAM4LC?B")
|
|
bitfld.long 0x04 24.--29. " NSU , Number of Segment Terminals in Use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
elif cpuis("ATSAM4LC?A")
|
|
bitfld.long 0x04 24.--29. " NSU , Number of Segment Terminals in Use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..."
|
|
endif
|
|
bitfld.long 0x04 16.--21. " FCST , Fine Contrast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--9. " DUTY , Duty Select" "1/4,Static,1/2,1/3"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOCK , Lock" "Unlocked,Locked"
|
|
bitfld.long 0x04 2. " BLANK , Blank LCD" "Defined,Turned off"
|
|
bitfld.long 0x04 1. " WMOD , Waveform Mode" "Low,Standard"
|
|
textline " "
|
|
bitfld.long 0x04 0. " XBIAS , External Bias Generation" "Internal,External"
|
|
line.long 0x08 "TIM, Timing Register"
|
|
bitfld.long 0x08 24.--28. " FC2 , Frame Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " FC1 , Frame Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 13. " FC0PB , Frame Counter 0 Prescaler Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x08 8.--12. " FC0 , Frame Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 1.--3. " CLKDIV , LCD Clock Division" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0. " PRESC , LCD Prescaler Select" "8,16"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 8. " CPS , Charge Pump Status" "Not ready,Ready"
|
|
bitfld.long 0x00 7. " CSRS , Circular Shift Register Status" "Not running,Running"
|
|
bitfld.long 0x00 6. " BLKS , Blink Status" "Not running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WEN , Wake up Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN , LCDCA Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FC2S , Frame Counter 2 Status" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FC1S , Frame Counter 1 Status" "Stopped,Running"
|
|
bitfld.long 0x00 1. " FC0S , Frame Counter 0 Status" "Stopped,Running"
|
|
bitfld.long 0x00 0. " FC0R , Frame Counter 0 Rollover" "No effect,Clear"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x00 "SCR, Status Clear Register"
|
|
bitfld.long 0x00 0. " FC0R , Frame Counter 0 Rollover" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DRL0 , Data Register Low 0 "
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 31. " DATA31 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 30. " DATA30 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 29. " DATA29 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DATA28 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 27. " DATA27 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 26. " DATA26 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DATA25 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 24. " DATA24 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 23. " DATA23 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("ATSAM4LC?B")||cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 22. " DATA22 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 21. " DATA21 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 20. " DATA20 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATA19 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 18. " DATA18 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 17. " DATA17 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA16 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 15. " DATA15 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 14. " DATA14 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DATA13 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " DATA10 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 9. " DATA9 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 8. " DATA8 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATA7 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 , Segments Value" "Low,High"
|
|
sif cpuis("ATSAM4LC?C")
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "DRH0 , Data Register High 0 "
|
|
bitfld.long 0x00 7. " DATA39 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA38 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA37 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA36 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA35 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA34 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA33 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA32 , Segments Value" "Low,High"
|
|
endif
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "DRL1 , Data Register Low 1 "
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 31. " DATA31 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 30. " DATA30 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 29. " DATA29 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DATA28 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 27. " DATA27 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 26. " DATA26 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DATA25 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 24. " DATA24 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 23. " DATA23 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("ATSAM4LC?B")||cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 22. " DATA22 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 21. " DATA21 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 20. " DATA20 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATA19 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 18. " DATA18 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 17. " DATA17 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA16 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 15. " DATA15 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 14. " DATA14 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DATA13 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " DATA10 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 9. " DATA9 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 8. " DATA8 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATA7 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 , Segments Value" "Low,High"
|
|
sif cpuis("ATSAM4LC?C")
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "DRH1 , Data Register High 1 "
|
|
bitfld.long 0x00 7. " DATA39 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA38 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA37 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA36 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA35 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA34 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA33 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA32 , Segments Value" "Low,High"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "DRL2 , Data Register Low 2 "
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 31. " DATA31 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 30. " DATA30 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 29. " DATA29 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DATA28 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 27. " DATA27 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 26. " DATA26 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DATA25 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 24. " DATA24 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 23. " DATA23 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("ATSAM4LC?B")||cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 22. " DATA22 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 21. " DATA21 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 20. " DATA20 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATA19 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 18. " DATA18 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 17. " DATA17 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA16 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 15. " DATA15 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 14. " DATA14 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DATA13 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " DATA10 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 9. " DATA9 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 8. " DATA8 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATA7 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 , Segments Value" "Low,High"
|
|
sif cpuis("ATSAM4LC?C")
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "DRH2 , Data Register High 2 "
|
|
bitfld.long 0x00 7. " DATA39 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA38 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA37 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA36 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA35 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA34 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA33 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA32 , Segments Value" "Low,High"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DRL3 , Data Register Low 3 "
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 31. " DATA31 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 30. " DATA30 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 29. " DATA29 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DATA28 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 27. " DATA27 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 26. " DATA26 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DATA25 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 24. " DATA24 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 23. " DATA23 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("ATSAM4LC?B")||cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x00 22. " DATA22 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 21. " DATA21 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 20. " DATA20 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DATA19 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 18. " DATA18 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 17. " DATA17 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA16 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 15. " DATA15 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 14. " DATA14 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DATA13 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " DATA12 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 11. " DATA11 , Segments Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " DATA10 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 9. " DATA9 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 8. " DATA8 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATA7 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 , Segments Value" "Low,High"
|
|
sif cpuis("ATSAM4LC?C")
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "DRH3 , Data Register High 3 "
|
|
bitfld.long 0x00 7. " DATA39 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 6. " DATA38 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 5. " DATA37 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA36 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 3. " DATA35 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 2. " DATA34 , Segments Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA33 , Segments Value" "Low,High"
|
|
bitfld.long 0x00 0. " DATA32 , Segments Value" "Low,High"
|
|
endif
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "IADR, Indirect Access Data Register"
|
|
hexmask.long.byte 0x00 16.--20. 1. " OFF , Byte Offset"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DMASK , Data Mask"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA , Segments Value"
|
|
group.long 0x38++0xB
|
|
line.long 0x00 "BCFG, Blink Configuration Register"
|
|
bitfld.long 0x00 15. " BSS1[3] , Blink Segment Selection 1 [3]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " BSS1[2] , Blink Segment Selection 1 [2]" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " BSS1[1] , Blink Segment Selection 1 [1]" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BSS1[0] , Blink Segment Selection 1 [0]" "Not selected,Selected"
|
|
bitfld.long 0x00 11. " BSS0[3] , Blink Segment Selection 0 [3]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " BSS0[2] , Blink Segment Selection 0 [2]" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BSS0[1] , Blink Segment Selection 0 [1]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " BSS0[0] , Blink Segment Selection 0 [0]" "Not selected,Selected"
|
|
bitfld.long 0x00 1.--2. " FCS , Frame Counter Selection" "FC0,FC1,FC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " MODE , Blinking Mode" "All,Selected"
|
|
line.long 0x04 "CSRCFG, Circular Shift Register Configuration"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA , Circular Shift Register Value"
|
|
bitfld.long 0x04 3.--5. " SIZE , Size" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x04 1.--2. " FCS , Frame Counter Selection" "FC0,FC1,FC2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0. " DIR , Direction" "Left,Right"
|
|
line.long 0x08 "CMCFG, Character Mapping Configuration Register"
|
|
sif cpuis("ATSAM4LC?C")
|
|
bitfld.long 0x08 8.--13. " STSEG ,Start Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,?..."
|
|
elif cpuis("ATSAM4LC?B")
|
|
bitfld.long 0x08 8.--13. " STSEG ,Start Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..."
|
|
elif cpuis("ATSAM4LC?A")
|
|
bitfld.long 0x08 8.--13. " STSEG ,Start Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
endif
|
|
bitfld.long 0x08 1.--2. " TDG , Type of Digit" "7-segment COM[2:0],7-segment COM[3:0],14-segment COM[3:0],16-segment COM[2:0]"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DREV , Digit Reverse Mode" "Disabled,Enabled"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x00 "CMDR, Character Mapping Data Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ASCII , ASCII Code"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ACMCFG,Automated Character Mapping Configuration Register"
|
|
bitfld.long 0x00 24.--27. " DIGN ,Digit Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " STEPS ,Scrolling Steps"
|
|
bitfld.long 0x00 8.--13. " STSEG ,Start Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TDG , Type of Digit" "7-segment COM[2:0],7-segment COM[3:0],14-segment COM[3:0],16-segment COM[2:0]"
|
|
bitfld.long 0x00 4. " DREV , Digit Reverse Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MODE ,Mode" "Sequential,Scrolling"
|
|
bitfld.long 0x00 1.--2. " FCS ,Frame Counter Selection" "FC0,FC1,FC2,?..."
|
|
bitfld.long 0x00 0. " EN ,Automated Character Mapping Enable" "Disabled,Enabled"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "ACMDR,Automated Character Mapping Data Register"
|
|
hexmask.long.byte 0x00 0.--6. 0x1 " ASCII ,ASCII Code"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ABMCFG,Automated Bit Mapping Configuration Register"
|
|
bitfld.long 0x00 8.--12. " SIZE ,Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1.--2. " FCS ,Frame Counter Selection" "FC0,FC1,FC2,?..."
|
|
bitfld.long 0x00 0. " EN ,Automated Bit Mapping Enable" "Disabled,Enabled"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "ABMDR,Automated Bit Mapping Data Register"
|
|
hexmask.long.byte 0x00 16.--20. 1. " OFF , Byte Offset"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DMASK , Data Mask"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA , Segments Value"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
bitfld.long 0x00 0. " FC0R_set/clr , Frame Counter 0 Rollover" "Masked,Not masked"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x00 "VERSION, Module Version"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version numer"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "PARC (Parallel Capture)"
|
|
base ad:0x4006C000
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "CFG, Configuration Register"
|
|
bitfld.long 0x00 7. " ODD , Odd Capture" "Even,Odd"
|
|
bitfld.long 0x00 6. " HALF , Half Capture" "All,Half"
|
|
bitfld.long 0x00 5. " EDGE , Sampling Edge Select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMODE , Events Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SMODE , Sampling Mode" "PCEN1,PCEN1 and PCEN2,PCEN1 or PCEN2,Always"
|
|
bitfld.long 0x00 0.--1. " DSIZE , Data Size" "Byte,Half-word,Word,Word"
|
|
line.long 0x04 "CR, Control Register"
|
|
bitfld.long 0x04 3. " STOP , Stop Capture" "No effect,Enabled"
|
|
bitfld.long 0x04 2. " START , Start Capture" "No effect,Enabled"
|
|
bitfld.long 0x04 1. " DIS , Disable" "No effect,PARC Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN , Enable" "No effect,PARC Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "IMR, Interrupt Mask Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVR_set/clr , Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DRDY_set/clr , Data Ready" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SR, Status Register"
|
|
bitfld.long 0x00 3. " OVR , Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " DRDY , Data Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " CS , Capture Status" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN , Enable Status" "Disabled,Enabled"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "ICR, Interrupt Status Clear Register"
|
|
bitfld.long 0x00 3. " OVR , Overrun" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " DRDY , Data Ready" "No efect,Clear"
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x00 "RHR, Receive Holding Register"
|
|
in
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "VERSION, Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version Number"
|
|
width 0xB
|
|
tree.end
|
|
tree "CRCCU (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x400A4000
|
|
width 0x13
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRCCU_DSCR,CRCCU Descriptor Base Address Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 0x02 " DSCR ,Descriptor Base Address"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRCCU_DMA_SR,CRCCU DMA Status Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DMASR ,DMA Status Register" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRCCU_DMA_IMR,CRCCU DMA Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DMAIMR ,Interrupt Mask Register" "Disabled,Enabled"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "CRCCU_DMA_ISR, CRCCU DMA Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "CRCCU_CR,CRCCU Control Register"
|
|
bitfld.long 0x00 0. " RESET ,CRC Computation Reset" "No effect,Reset"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CRCCU_MR,CRCCU Mode Register"
|
|
bitfld.long 0x00 4.--7. " DIVIDER ,Request Divider" "2^1,2^2,2^3,2^4,2^5,2^6,2^7,2^8,2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^16"
|
|
bitfld.long 0x00 2.--3. " PTYPE ,Primitive Polynomial" "0x04C11DB7,0x1EDC6F41,0x1021,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMPARE ,CRC Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,CRC Enable" "Disabled,Enabled"
|
|
if ((d.l((ad:0x400A4000+0x38))&0x02)==0x02)
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CRCCU_SR,CRCCU Status Register"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CRCCU_SR,CRCCU Status Register"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRCCU_IMR,CRCCU Interrupt Mask Register"
|
|
sif cpuis("ATSAM4S*")
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ERRIMR ,CRC Error Interrupt Mask Register" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DMAIMR ,Interrupt Mask Register" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CRCCU_ISR, CRCCU Interrupt Status Register"
|
|
bitfld.long 0x00 0. " ERRISR ,CRC Error Interrupt Status" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "CRCCU_ISR, CRCCU Interrupt Status Register"
|
|
in
|
|
endif
|
|
sif (cpuis("ATSAM4L*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION, Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION , Version Number"
|
|
endif
|
|
tree "Transfer Control Registers"
|
|
base ad:(d.l(ad:0x400A4000)&0xFFFFFE00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TR_ADDR,Transfer Address Register"
|
|
line.long 0x04 "TR_CTRL,Transfer Control Register"
|
|
sif (cpuis("ATSAM4S16C")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4L*"))
|
|
bitfld.long 0x04 27. " IEN ,Context Done Interrupt Enable" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 27. " IEN ,Context Done Interrupt Enable" "Enabled,Disabled"
|
|
endif
|
|
bitfld.long 0x04 24.--25. " TRWIDTH ,Transfer Width Register" "BYTE,HALFWORD,WORD,?..."
|
|
hexmask.long.word 0x04 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TR_CRC,Transfer Reference Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|