69430 lines
4.1 MiB
69430 lines
4.1 MiB
; --------------------------------------------------------------------------------
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; @Title: ADSP-CM40x On-Chip Peripherals
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; @Props: Released
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; @Author: MSU, MRD
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; @Changelog: 2018-03-30 MRD
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; @Manufacturer: Analog Devices
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; @Doc: ADSP-CM40x_hrm_rev.0.2.pdf (Rev. 0.2, 2013-09)
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; ADSP-CM40x-hrm.pdf (Rev. 0.3, 2015-11)
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; ADSP-CM402F_CM403F_CM407F_CM408F.pdf (Rev. PrE, 2013-09)
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; UG-480.pdf (Rev. A, 2015-11)
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; @Chip: ADSPCM402F, ADSPCM403F, ADSPCM407F, ADSPCM408F, ADSPCM409F
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; @Core: Cortex-M4F
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peradspcm4.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SCB (System Crossbars)"
|
|
base ad:0x80242020
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCB_MST00_IB_SYNC,SCB0 Master 0 IB Sync Mode"
|
|
bitfld.long 0x00 0.--2. " VALUE ,IB read quality of service value" "Sync 1:1,Sync n:1,,,Async,?..."
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "SCB_MST00_IB_RQOS,SCB0 Master 0 Read Quality of Service"
|
|
bitfld.long 0x00 0.--3. " VALUE ,IB read quality of service value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SCB_MST00_IB_WQOS,SCB0 Master 0 Write Quality of Service"
|
|
bitfld.long 0x04 0.--3. " VALUE ,IB read quality of service value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "SCB_MST01_IB_SYNC,SCB0 Master 1 IB Sync Mode"
|
|
bitfld.long 0x00 0.--2. " VALUE ,IB read quality of service value" "Sync 1:1,Sync n:1,,,Async,?..."
|
|
group.long 0x10E0++0x07
|
|
line.long 0x00 "SCB_MST01_IB_RQOS,SCB0 Master 1 Read Quality of Service"
|
|
bitfld.long 0x00 0.--3. " VALUE ,IB read quality of service value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SCB_MST01_IB_WQOS,SCB0 Master 1 Write Quality of Service"
|
|
bitfld.long 0x04 0.--3. " VALUE ,IB read quality of service value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0x20E0++0x07
|
|
hide.long 0x00 "SCB0_MST2_RQOS,SCB0 Read Quality of Service for Master 2"
|
|
in
|
|
hide.long 0x04 "SCB0_MST2_WQOS,SCB0 Write Quality of Service for Master 2"
|
|
in
|
|
hgroup.long 0x30E0++0x07
|
|
hide.long 0x00 "SCB0_MST3_RQOS,SCB0 Read Quality of Service for Master 3"
|
|
in
|
|
hide.long 0x04 "SCB0_MST3_WQOS,SCB0 Write Quality of Service for Master 3"
|
|
in
|
|
hgroup.long 0x40E0++0x07
|
|
hide.long 0x00 "SCB0_MST4_RQOS,SCB0 Read Quality of Service for Master 4"
|
|
in
|
|
hide.long 0x04 "SCB0_MST4_WQOS,SCB0 Write Quality of Service for Master 4"
|
|
in
|
|
hgroup.long 0x50E0++0x07
|
|
hide.long 0x00 "SCB0_MST5_RQOS,SCB0 Read Quality of Service for Master 5"
|
|
in
|
|
hide.long 0x04 "SCB0_MST5_WQOS,SCB0 Write Quality of Service for Master 5"
|
|
in
|
|
hgroup.long 0x60E0++0x07
|
|
hide.long 0x00 "SCB0_MST6_RQOS,SCB0 Read Quality of Service for Master 6"
|
|
in
|
|
hide.long 0x04 "SCB0_MST6_WQOS,SCB0 Write Quality of Service for Master 6"
|
|
in
|
|
hgroup.long 0x70E0++0x07
|
|
hide.long 0x00 "SCB0_MST7_RQOS,SCB0 Read Quality of Service for Master 7"
|
|
in
|
|
hide.long 0x04 "SCB0_MST7_WQOS,SCB0 Write Quality of Service for Master 7"
|
|
in
|
|
hgroup.long 0x80E0++0x07
|
|
hide.long 0x00 "SCB0_MST8_RQOS,SCB0 Read Quality of Service for Master 8"
|
|
in
|
|
hide.long 0x04 "SCB0_MST8_WQOS,SCB0 Write Quality of Service for Master 8"
|
|
in
|
|
hgroup.long 0x90E0++0x07
|
|
hide.long 0x00 "SCB0_MST9_RQOS,SCB0 Read Quality of Service for Master 9"
|
|
in
|
|
hide.long 0x04 "SCB0_MST9_WQOS,SCB0 Write Quality of Service for Master 9"
|
|
in
|
|
hgroup.long 0xA0E0++0x07
|
|
hide.long 0x00 "SCB0_MST10_RQOS,SCB0 Read Quality of Service for Master 10"
|
|
in
|
|
hide.long 0x04 "SCB0_MST10_WQOS,SCB0 Write Quality of Service for Master 10"
|
|
in
|
|
hgroup.long 0xB0E0++0x07
|
|
hide.long 0x00 "SCB0_MST11_RQOS,SCB0 Read Quality of Service for Master 11"
|
|
in
|
|
hide.long 0x04 "SCB0_MST11_WQOS,SCB0 Write Quality of Service for Master 11"
|
|
in
|
|
hgroup.long 0xC0E0++0x07
|
|
hide.long 0x00 "SCB0_MST12_RQOS,SCB0 Read Quality of Service for Master 12"
|
|
in
|
|
hide.long 0x04 "SCB0_MST12_WQOS,SCB0 Write Quality of Service for Master 12"
|
|
in
|
|
hgroup.long 0xD0E0++0x07
|
|
hide.long 0x00 "SCB0_MST13_RQOS,SCB0 Read Quality of Service for Master 13"
|
|
in
|
|
hide.long 0x04 "SCB0_MST13_WQOS,SCB0 Write Quality of Service for Master 13"
|
|
in
|
|
hgroup.long 0xE0E0++0x07
|
|
hide.long 0x00 "SCB0_MST14_RQOS,SCB0 Read Quality of Service for Master 14"
|
|
in
|
|
hide.long 0x04 "SCB0_MST14_WQOS,SCB0 Write Quality of Service for Master 14"
|
|
in
|
|
hgroup.long 0xF0E0++0x07
|
|
hide.long 0x00 "SCB0_MST15_RQOS,SCB0 Read Quality of Service for Master 15"
|
|
in
|
|
hide.long 0x04 "SCB0_MST15_WQOS,SCB0 Write Quality of Service for Master 15"
|
|
in
|
|
hgroup.long 0x100E0++0x07
|
|
hide.long 0x00 "SCB0_MST16_RQOS,SCB0 Read Quality of Service for Master 16"
|
|
in
|
|
hide.long 0x04 "SCB0_MST16_WQOS,SCB0 Write Quality of Service for Master 16"
|
|
in
|
|
hgroup.long 0x110E0++0x07
|
|
hide.long 0x00 "SCB0_MST17_RQOS,SCB0 Read Quality of Service for Master 17"
|
|
in
|
|
hide.long 0x04 "SCB0_MST17_WQOS,SCB0 Write Quality of Service for Master 17"
|
|
in
|
|
hgroup.long 0x120E0++0x07
|
|
hide.long 0x00 "SCB0_MST18_RQOS,SCB0 Read Quality of Service for Master 18"
|
|
in
|
|
hide.long 0x04 "SCB0_MST18_WQOS,SCB0 Write Quality of Service for Master 18"
|
|
in
|
|
hgroup.long 0x130E0++0x07
|
|
hide.long 0x00 "SCB0_MST19_RQOS,SCB0 Read Quality of Service for Master 19"
|
|
in
|
|
hide.long 0x04 "SCB0_MST19_WQOS,SCB0 Write Quality of Service for Master 19"
|
|
in
|
|
hgroup.long 0x140E0++0x07
|
|
hide.long 0x00 "SCB0_MST20_RQOS,SCB0 Read Quality of Service for Master 20"
|
|
in
|
|
hide.long 0x04 "SCB0_MST20_WQOS,SCB0 Write Quality of Service for Master 20"
|
|
in
|
|
hgroup.long 0x150E0++0x07
|
|
hide.long 0x00 "SCB0_MST21_RQOS,SCB0 Read Quality of Service for Master 21"
|
|
in
|
|
hide.long 0x04 "SCB0_MST21_WQOS,SCB0 Write Quality of Service for Master 21"
|
|
in
|
|
hgroup.long 0x160E0++0x07
|
|
hide.long 0x00 "SCB0_MST22_RQOS,SCB0 Read Quality of Service for Master 22"
|
|
in
|
|
hide.long 0x04 "SCB0_MST22_WQOS,SCB0 Write Quality of Service for Master 22"
|
|
in
|
|
hgroup.long 0x170E0++0x07
|
|
hide.long 0x00 "SCB0_MST23_RQOS,SCB0 Read Quality of Service for Master 23"
|
|
in
|
|
hide.long 0x04 "SCB0_MST23_WQOS,SCB0 Write Quality of Service for Master 23"
|
|
in
|
|
hgroup.long 0x180E0++0x07
|
|
hide.long 0x00 "SCB0_MST24_RQOS,SCB0 Read Quality of Service for Master 24"
|
|
in
|
|
hide.long 0x04 "SCB0_MST24_WQOS,SCB0 Write Quality of Service for Master 24"
|
|
in
|
|
hgroup.long 0x190E0++0x07
|
|
hide.long 0x00 "SCB0_MST25_RQOS,SCB0 Read Quality of Service for Master 25"
|
|
in
|
|
hide.long 0x04 "SCB0_MST25_WQOS,SCB0 Write Quality of Service for Master 25"
|
|
in
|
|
hgroup.long 0x1A0E0++0x07
|
|
hide.long 0x00 "SCB0_MST26_RQOS,SCB0 Read Quality of Service for Master 26"
|
|
in
|
|
hide.long 0x04 "SCB0_MST26_WQOS,SCB0 Write Quality of Service for Master 26"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "CGU (System Crossbars)"
|
|
base ad:0x40016000
|
|
width 19.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CGU0_CTL,CGU0 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " WFI ,Wait for idle" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier select"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DF ,Divide frequency" "OSC_CLKIN,OSC_CLKIN/2"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " PLLEN ,PLL enable" "No action,Enabled"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No action,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Exit bypass"
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No bypass,Bypass"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 15. " OSCWDSTATF ,Oscillator watchdog status fault" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " OSCWDSTATFC ,Oscillator watchdog status fault code bit" "No fault,No Input clock,Sub harmonic CLKIN,Harmonic CLKIN,No AUX_CLK,CLKIN>BOUF,,Multiple limit faults"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 22. " PLOCKERR ,PLL lock error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " DIVERR ,DIV error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " OCBF ,OUTCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " DCBF ,DCLK buffer status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " CCBF0 ,CCLK0 buffer status" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CGU0_STAT,CGU0 Status Register"
|
|
eventfld.long 0x00 21. " PCFGERR ,PLL configuration error" "No error,Error"
|
|
eventfld.long 0x00 20. " WDIVERR ,Write to DIV error" "No error,Error"
|
|
eventfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
rbitfld.long 0x00 3. " CLKSALGN ,Clock alignment" "Aligned,Not aligned"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " PLOCK ,PLL lock" "Unlocked,Locked"
|
|
rbitfld.long 0x00 1. " PLLBP ,PLL bypass" "No bypass,Bypass"
|
|
rbitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,PLL clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 Divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " UPDT ,Update clock divisors" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ALGN ,Align" "No action,Align"
|
|
textline " "
|
|
hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OUTCLK divisor"
|
|
bitfld.long 0x00 16.--20. " DSEL ,DCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 divisor" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 divisor" "8,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CSEL ,CCLK divisor" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,,,,,,,SCLK1_0,,SCLK0_0,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,,,,,,,SCLK1_0,,SCLK0_0,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,CLKO8,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--21. " USBCLKSEL ,USBCLK select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT select" "CLKIN0,CLKIN1,CGU0_0.SYSCLK,CLKO0,CLKO2,CLKO3,CLKO5,CLKO7,CLKO8,?..."
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 23. " FAULTPINDIS ,Fault pin disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " MONDIS ,Oscillator watchdog monitor functions disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN ,Fault detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BOUEN ,Bad oscillator upper frequency limit detection enabled" "Low,High"
|
|
bitfld.long 0x00 8.--12. " BOUF ,Bad oscillator upper frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CNGEN ,Clock not good enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HODEN ,Harmonic oscillation detection enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's Clock Divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load Counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 4.--7. " TSDIV ,Counter's clock divider" "1,2,4,9,16,25,36,49,64,81,100,121,144,169,196,225"
|
|
bitfld.long 0x00 1. " LOAD ,Load counter" "No action,Load"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "CGU0_TSVALUE0,CGU0 Time Stamp Counter Initial 32 LSB Value Register"
|
|
line.long 0x04 "CGU0_TSVALUE1,CGU0 Time Stamp Counter Initial MSB Value Register"
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "CGU0_TSCOUNT0,CGU0 Time Stamp Counter 32 LSB Register"
|
|
line.long 0x04 "CGU0_TSCOUNT1,CGU0 Time Stamp Counter 32 MSB Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CGU0_CCBF_STAT,CGU0 Core Clock Buffer Status Register"
|
|
bitfld.long 0x00 1. " CCBF1 ,Core clock buffer 1" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0" "Enabled,Disabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40016000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40016000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 3. " OUTCLKBF ,Output clock buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DCLK buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CGU0_SCBF_STAT,CGU0 System Clock Buffer Status Register"
|
|
bitfld.long 0x00 3. " OCLKBF ,Output clock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DCLKBF ,DClock 1 buffer" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " SCLK1BF ,System clock 1 buffer" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCLK0BF ,System clock 0 buffer" "Enabled,Disabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CGU0_REVID,CGU0 Revision ID Register"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPU (System Protection Unit)"
|
|
base ad:0x40027000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SPU_CTL,SPU Control Register"
|
|
bitfld.long 0x00 16. " WPLCK ,Write protect register lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 14. " PINTEN ,Protection violation interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " GLCK ,Global lock"
|
|
line.long 0x04 "SPU_STAT,SPU Status Register"
|
|
eventfld.long 0x04 31. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error" "No error,Error"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
eventfld.long 0x04 12. " VIRQ ,Violation interrupt request" "Not detected,Detected"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x04 0. " GLCK ,Global lock status" "Unlocked,Locked"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 17. " SM[1] ,System master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,System master 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CM[2] ,Core master 2 write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core master 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Core master 0 write protect enable" "Disabled,Enabled"
|
|
elif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SPU_WP0,SPU Write Protect Register 0"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "SPU_WP1,SPU Write Protect Register 1"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SPU_WP2,SPU Write Protect Register 2"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "SPU_WP3,SPU Write Protect Register 3"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SPU_WP4,SPU Write Protect Register 4"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SPU_WP5,SPU Write Protect Register 5"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "SPU_WP6,SPU Write Protect Register 6"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SPU_WP7,SPU Write Protect Register 7"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SPU_WP8,SPU Write Protect Register 8"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SPU_WP9,SPU Write Protect Register 9"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SPU_WP10,SPU Write Protect Register 10"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "SPU_WP11,SPU Write Protect Register 11"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "SPU_WP12,SPU Write Protect Register 12"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "SPU_WP13,SPU Write Protect Register 13"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "SPU_WP14,SPU Write Protect Register 14"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "SPU_WP15,SPU Write Protect Register 15"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SPU_WP16,SPU Write Protect Register 16"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "SPU_WP17,SPU Write Protect Register 17"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "SPU_WP18,SPU Write Protect Register 18"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "SPU_WP19,SPU Write Protect Register 19"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "SPU_WP20,SPU Write Protect Register 20"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "SPU_WP21,SPU Write Protect Register 21"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "SPU_WP22,SPU Write Protect Register 22"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "SPU_WP23,SPU Write Protect Register 23"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "SPU_WP24,SPU Write Protect Register 24"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "SPU_WP25,SPU Write Protect Register 25"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "SPU_WP26,SPU Write Protect Register 26"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "SPU_WP27,SPU Write Protect Register 27"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "SPU_WP28,SPU Write Protect Register 28"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "SPU_WP29,SPU Write Protect Register 29"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "SPU_WP30,SPU Write Protect Register 30"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "SPU_WP31,SPU Write Protect Register 31"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SPU_WP32,SPU Write Protect Register 32"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "SPU_WP33,SPU Write Protect Register 33"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "SPU_WP34,SPU Write Protect Register 34"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "SPU_WP35,SPU Write Protect Register 35"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "SPU_WP36,SPU Write Protect Register 36"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "SPU_WP37,SPU Write Protect Register 37"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "SPU_WP38,SPU Write Protect Register 38"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "SPU_WP39,SPU Write Protect Register 39"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "SPU_WP40,SPU Write Protect Register 40"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "SPU_WP41,SPU Write Protect Register 41"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "SPU_WP42,SPU Write Protect Register 42"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "SPU_WP43,SPU Write Protect Register 43"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "SPU_WP44,SPU Write Protect Register 44"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "SPU_WP45,SPU Write Protect Register 45"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "SPU_WP46,SPU Write Protect Register 46"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "SPU_WP47,SPU Write Protect Register 47"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "SPU_WP48,SPU Write Protect Register 48"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "SPU_WP49,SPU Write Protect Register 49"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "SPU_WP50,SPU Write Protect Register 50"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "SPU_WP51,SPU Write Protect Register 51"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "SPU_WP52,SPU Write Protect Register 52"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "SPU_WP53,SPU Write Protect Register 53"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "SPU_WP54,SPU Write Protect Register 54"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "SPU_WP55,SPU Write Protect Register 55"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "SPU_WP56,SPU Write Protect Register 56"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "SPU_WP57,SPU Write Protect Register 57"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "SPU_WP58,SPU Write Protect Register 58"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "SPU_WP59,SPU Write Protect Register 59"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "SPU_WP60,SPU Write Protect Register 60"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "SPU_WP61,SPU Write Protect Register 61"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "SPU_WP62,SPU Write Protect Register 62"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "SPU_WP63,SPU Write Protect Register 63"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "SPU_WP64,SPU Write Protect Register 64"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "SPU_WP65,SPU Write Protect Register 65"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "SPU_WP66,SPU Write Protect Register 66"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "SPU_WP67,SPU Write Protect Register 67"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "SPU_WP68,SPU Write Protect Register 68"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "SPU_WP69,SPU Write Protect Register 69"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "SPU_WP70,SPU Write Protect Register 70"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "SPU_WP71,SPU Write Protect Register 71"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "SPU_WP72,SPU Write Protect Register 72"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "SPU_WP73,SPU Write Protect Register 73"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "SPU_WP74,SPU Write Protect Register 74"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "SPU_WP75,SPU Write Protect Register 75"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "SPU_WP76,SPU Write Protect Register 76"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "SPU_WP77,SPU Write Protect Register 77"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "SPU_WP78,SPU Write Protect Register 78"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "SPU_WP79,SPU Write Protect Register 79"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "SPU_WP80,SPU Write Protect Register 80"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "SPU_WP81,SPU Write Protect Register 81"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "SPU_WP82,SPU Write Protect Register 82"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "SPU_WP83,SPU Write Protect Register 83"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "SPU_WP84,SPU Write Protect Register 84"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "SPU_WP85,SPU Write Protect Register 85"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "SPU_WP86,SPU Write Protect Register 86"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "SPU_WP87,SPU Write Protect Register 87"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "SPU_WP88,SPU Write Protect Register 88"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "SPU_WP89,SPU Write Protect Register 89"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "SPU_WP90,SPU Write Protect Register 90"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "SPU_WP91,SPU Write Protect Register 91"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "SPU_WP92,SPU Write Protect Register 92"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "SPU_WP93,SPU Write Protect Register 93"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "SPU_WP94,SPU Write Protect Register 94"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "SPU_WP95,SPU Write Protect Register 95"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SPU_WP96,SPU Write Protect Register 96"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "SPU_WP97,SPU Write Protect Register 97"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "SPU_WP98,SPU Write Protect Register 98"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "SPU_WP99,SPU Write Protect Register 99"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "SPU_WP100,SPU Write Protect Register 100"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "SPU_WP101,SPU Write Protect Register 101"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "SPU_WP102,SPU Write Protect Register 102"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "SPU_WP103,SPU Write Protect Register 103"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "SPU_WP104,SPU Write Protect Register 104"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "SPU_WP105,SPU Write Protect Register 105"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "SPU_WP106,SPU Write Protect Register 106"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "SPU_WP107,SPU Write Protect Register 107"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "SPU_WP108,SPU Write Protect Register 108"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "SPU_WP109,SPU Write Protect Register 109"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "SPU_WP110,SPU Write Protect Register 110"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "SPU_WP111,SPU Write Protect Register 111"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "SPU_WP112,SPU Write Protect Register 112"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "SPU_WP113,SPU Write Protect Register 113"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "SPU_WP114,SPU Write Protect Register 114"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "SPU_WP115,SPU Write Protect Register 115"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "SPU_WP116,SPU Write Protect Register 116"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "SPU_WP117,SPU Write Protect Register 117"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "SPU_WP118,SPU Write Protect Register 118"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "SPU_WP119,SPU Write Protect Register 119"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "SPU_WP120,SPU Write Protect Register 120"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "SPU_WP121,SPU Write Protect Register 121"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "SPU_WP122,SPU Write Protect Register 122"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "SPU_WP123,SPU Write Protect Register 123"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "SPU_WP124,SPU Write Protect Register 124"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "SPU_WP125,SPU Write Protect Register 125"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "SPU_WP126,SPU Write Protect Register 126"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "SPU_WP127,SPU Write Protect Register 127"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPU_WP128,SPU Write Protect Register 128"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SPU_WP129,SPU Write Protect Register 129"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x608++0x03
|
|
line.long 0x00 "SPU_WP130,SPU Write Protect Register 130"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SPU_WP130,SPU Write Protect Register 130"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x60C++0x03
|
|
line.long 0x00 "SPU_WP131,SPU Write Protect Register 131"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SPU_WP131,SPU Write Protect Register 131"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "SPU_WP132,SPU Write Protect Register 132"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SPU_WP132,SPU Write Protect Register 132"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x614++0x03
|
|
line.long 0x00 "SPU_WP133,SPU Write Protect Register 133"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SPU_WP133,SPU Write Protect Register 133"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x618++0x03
|
|
line.long 0x00 "SPU_WP134,SPU Write Protect Register 134"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SPU_WP134,SPU Write Protect Register 134"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x61C++0x03
|
|
line.long 0x00 "SPU_WP135,SPU Write Protect Register 135"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SPU_WP135,SPU Write Protect Register 135"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "SPU_WP136,SPU Write Protect Register 136"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SPU_WP136,SPU Write Protect Register 136"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x624++0x03
|
|
line.long 0x00 "SPU_WP137,SPU Write Protect Register 137"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SPU_WP137,SPU Write Protect Register 137"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x628++0x03
|
|
line.long 0x00 "SPU_WP138,SPU Write Protect Register 138"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SPU_WP138,SPU Write Protect Register 138"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x62C++0x03
|
|
line.long 0x00 "SPU_WP139,SPU Write Protect Register 139"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SPU_WP139,SPU Write Protect Register 139"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "SPU_WP140,SPU Write Protect Register 140"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SPU_WP140,SPU Write Protect Register 140"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x634++0x03
|
|
line.long 0x00 "SPU_WP141,SPU Write Protect Register 141"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SPU_WP141,SPU Write Protect Register 141"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x638++0x03
|
|
line.long 0x00 "SPU_WP142,SPU Write Protect Register 142"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SPU_WP142,SPU Write Protect Register 142"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x63C++0x03
|
|
line.long 0x00 "SPU_WP143,SPU Write Protect Register 143"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SPU_WP143,SPU Write Protect Register 143"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "SPU_WP144,SPU Write Protect Register 144"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SPU_WP144,SPU Write Protect Register 144"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x644++0x03
|
|
line.long 0x00 "SPU_WP145,SPU Write Protect Register 145"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SPU_WP145,SPU Write Protect Register 145"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x648++0x03
|
|
line.long 0x00 "SPU_WP146,SPU Write Protect Register 146"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SPU_WP146,SPU Write Protect Register 146"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x64C++0x03
|
|
line.long 0x00 "SPU_WP147,SPU Write Protect Register 147"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SPU_WP147,SPU Write Protect Register 147"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x650++0x03
|
|
line.long 0x00 "SPU_WP148,SPU Write Protect Register 148"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SPU_WP148,SPU Write Protect Register 148"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "SPU_WP149,SPU Write Protect Register 149"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SPU_WP149,SPU Write Protect Register 149"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "SPU_WP150,SPU Write Protect Register 150"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SPU_WP150,SPU Write Protect Register 150"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x65C++0x03
|
|
line.long 0x00 "SPU_WP151,SPU Write Protect Register 151"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SPU_WP151,SPU Write Protect Register 151"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "SPU_WP152,SPU Write Protect Register 152"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SPU_WP152,SPU Write Protect Register 152"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x664++0x03
|
|
line.long 0x00 "SPU_WP153,SPU Write Protect Register 153"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SPU_WP153,SPU Write Protect Register 153"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x668++0x03
|
|
line.long 0x00 "SPU_WP154,SPU Write Protect Register 154"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SPU_WP154,SPU Write Protect Register 154"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x66C++0x03
|
|
line.long 0x00 "SPU_WP155,SPU Write Protect Register 155"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SPU_WP155,SPU Write Protect Register 155"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "SPU_WP156,SPU Write Protect Register 156"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SPU_WP156,SPU Write Protect Register 156"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x674++0x03
|
|
line.long 0x00 "SPU_WP157,SPU Write Protect Register 157"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SPU_WP157,SPU Write Protect Register 157"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x678++0x03
|
|
line.long 0x00 "SPU_WP158,SPU Write Protect Register 158"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SPU_WP158,SPU Write Protect Register 158"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x67C++0x03
|
|
line.long 0x00 "SPU_WP159,SPU Write Protect Register 159"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SPU_WP159,SPU Write Protect Register 159"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x680++0x03
|
|
line.long 0x00 "SPU_WP160,SPU Write Protect Register 160"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SPU_WP160,SPU Write Protect Register 160"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x684++0x03
|
|
line.long 0x00 "SPU_WP161,SPU Write Protect Register 161"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SPU_WP161,SPU Write Protect Register 161"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x688++0x03
|
|
line.long 0x00 "SPU_WP162,SPU Write Protect Register 162"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SPU_WP162,SPU Write Protect Register 162"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "SPU_WP163,SPU Write Protect Register 163"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SPU_WP163,SPU Write Protect Register 163"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "SPU_WP164,SPU Write Protect Register 164"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SPU_WP164,SPU Write Protect Register 164"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x694++0x03
|
|
line.long 0x00 "SPU_WP165,SPU Write Protect Register 165"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SPU_WP165,SPU Write Protect Register 165"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x698++0x03
|
|
line.long 0x00 "SPU_WP166,SPU Write Protect Register 166"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SPU_WP166,SPU Write Protect Register 166"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "SPU_WP167,SPU Write Protect Register 167"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SPU_WP167,SPU Write Protect Register 167"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "SPU_WP168,SPU Write Protect Register 168"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SPU_WP168,SPU Write Protect Register 168"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A4++0x03
|
|
line.long 0x00 "SPU_WP169,SPU Write Protect Register 169"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SPU_WP169,SPU Write Protect Register 169"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6A8++0x03
|
|
line.long 0x00 "SPU_WP170,SPU Write Protect Register 170"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SPU_WP170,SPU Write Protect Register 170"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "SPU_WP171,SPU Write Protect Register 171"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SPU_WP171,SPU Write Protect Register 171"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "SPU_WP172,SPU Write Protect Register 172"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SPU_WP172,SPU Write Protect Register 172"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B4++0x03
|
|
line.long 0x00 "SPU_WP173,SPU Write Protect Register 173"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SPU_WP173,SPU Write Protect Register 173"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6B8++0x03
|
|
line.long 0x00 "SPU_WP174,SPU Write Protect Register 174"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SPU_WP174,SPU Write Protect Register 174"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "SPU_WP175,SPU Write Protect Register 175"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SPU_WP175,SPU Write Protect Register 175"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C0++0x03
|
|
line.long 0x00 "SPU_WP176,SPU Write Protect Register 176"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SPU_WP176,SPU Write Protect Register 176"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C4++0x03
|
|
line.long 0x00 "SPU_WP177,SPU Write Protect Register 177"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SPU_WP177,SPU Write Protect Register 177"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6C8++0x03
|
|
line.long 0x00 "SPU_WP178,SPU Write Protect Register 178"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SPU_WP178,SPU Write Protect Register 178"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "SPU_WP179,SPU Write Protect Register 179"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SPU_WP179,SPU Write Protect Register 179"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "SPU_WP180,SPU Write Protect Register 180"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SPU_WP180,SPU Write Protect Register 180"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D4++0x03
|
|
line.long 0x00 "SPU_WP181,SPU Write Protect Register 181"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SPU_WP181,SPU Write Protect Register 181"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6D8++0x03
|
|
line.long 0x00 "SPU_WP182,SPU Write Protect Register 182"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SPU_WP182,SPU Write Protect Register 182"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "SPU_WP183,SPU Write Protect Register 183"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SPU_WP183,SPU Write Protect Register 183"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "SPU_WP184,SPU Write Protect Register 184"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SPU_WP184,SPU Write Protect Register 184"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "SPU_WP185,SPU Write Protect Register 185"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SPU_WP185,SPU Write Protect Register 185"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "SPU_WP186,SPU Write Protect Register 186"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SPU_WP186,SPU Write Protect Register 186"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "SPU_WP187,SPU Write Protect Register 187"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SPU_WP187,SPU Write Protect Register 187"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0x10000)==0x10000)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "SPU_WP188,SPU Write Protect Register 188"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM core write protect enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SPU_WP188,SPU Write Protect Register 188"
|
|
bitfld.long 0x00 19. " SM3 ,Enhanced BW MDMA write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SM2 ,ETR write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SM1 ,DBG write protect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ADSP-SC589"))
|
|
bitfld.long 0x00 16. " SM0 ,PCIE write protect enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CM2 ,SHARC core 1 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM1 ,SHARC core 0 write protect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CM0 ,ARM Core write protect enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SPU_SECURECTL,SPU Secure Control Register"
|
|
bitfld.long 0x00 16. " SCRLCK ,Secure register lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 14. " SINTEN ,Secure violation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MSECCLR ,Master secure clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSECCLR ,Slave secure clear" "No action,Clear"
|
|
rgroup.long 0x84C++0x03
|
|
line.long 0x00 "SPU_SECURECHK,SPU Secure Check Register"
|
|
if (((per.l(ad:0x40027000+0x840))&0x10000)==0x00)&&(((per.l(ad:0x40027000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SPU_SECUREC0,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
rgroup.long 0x984++0x03
|
|
line.long 0x00 "SPU_SECUREC1,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SPU_SECUREC2,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SPU_SECUREP140,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC34++0x03
|
|
line.long 0x00 "SPU_SECUREP141,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SPU_SECUREP142,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC3C++0x03
|
|
line.long 0x00 "SPU_SECUREP143,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SPU_SECUREP144,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC44++0x03
|
|
line.long 0x00 "SPU_SECUREP145,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SPU_SECUREP146,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC4C++0x03
|
|
line.long 0x00 "SPU_SECUREP147,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SPU_SECUREP148,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC54++0x03
|
|
line.long 0x00 "SPU_SECUREP149,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SPU_SECUREP150,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC5C++0x03
|
|
line.long 0x00 "SPU_SECUREP151,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SPU_SECUREP152,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC64++0x03
|
|
line.long 0x00 "SPU_SECUREP153,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SPU_SECUREP154,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC6C++0x03
|
|
line.long 0x00 "SPU_SECUREP155,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SPU_SECUREP156,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC74++0x03
|
|
line.long 0x00 "SPU_SECUREP157,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SPU_SECUREP158,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC7C++0x03
|
|
line.long 0x00 "SPU_SECUREP159,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SPU_SECUREP160,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC84++0x03
|
|
line.long 0x00 "SPU_SECUREP161,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SPU_SECUREP162,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC8C++0x03
|
|
line.long 0x00 "SPU_SECUREP163,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SPU_SECUREP164,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC94++0x03
|
|
line.long 0x00 "SPU_SECUREP165,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SPU_SECUREP166,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xC9C++0x03
|
|
line.long 0x00 "SPU_SECUREP167,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SPU_SECUREP168,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA4++0x03
|
|
line.long 0x00 "SPU_SECUREP169,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SPU_SECUREP170,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCAC++0x03
|
|
line.long 0x00 "SPU_SECUREP171,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SPU_SECUREP172,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB4++0x03
|
|
line.long 0x00 "SPU_SECUREP173,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SPU_SECUREP174,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCBC++0x03
|
|
line.long 0x00 "SPU_SECUREP175,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SPU_SECUREP176,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC4++0x03
|
|
line.long 0x00 "SPU_SECUREP177,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SPU_SECUREP178,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCCC++0x03
|
|
line.long 0x00 "SPU_SECUREP179,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SPU_SECUREP180,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD4++0x03
|
|
line.long 0x00 "SPU_SECUREP181,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SPU_SECUREP182,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCDC++0x03
|
|
line.long 0x00 "SPU_SECUREP183,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SPU_SECUREP184,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE4++0x03
|
|
line.long 0x00 "SPU_SECUREP185,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SPU_SECUREP186,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCEC++0x03
|
|
line.long 0x00 "SPU_SECUREP187,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SPU_SECUREP188,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SPU_SECUREC0,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "SPU_SECUREC1,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SPU_SECUREC2,SPU Secure Core Register"
|
|
bitfld.long 0x00 0. " CSEC0 ,Core secure" "Disabled,Enabled"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SPU_SECUREP0,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "SPU_SECUREP1,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SPU_SECUREP2,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "SPU_SECUREP3,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SPU_SECUREP4,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "SPU_SECUREP5,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SPU_SECUREP6,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "SPU_SECUREP7,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SPU_SECUREP8,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "SPU_SECUREP9,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SPU_SECUREP10,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "SPU_SECUREP11,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SPU_SECUREP12,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "SPU_SECUREP13,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SPU_SECUREP14,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "SPU_SECUREP15,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SPU_SECUREP16,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "SPU_SECUREP17,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SPU_SECUREP18,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "SPU_SECUREP19,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SPU_SECUREP20,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "SPU_SECUREP21,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SPU_SECUREP22,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "SPU_SECUREP23,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SPU_SECUREP24,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "SPU_SECUREP25,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SPU_SECUREP26,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "SPU_SECUREP27,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SPU_SECUREP28,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "SPU_SECUREP29,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SPU_SECUREP30,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "SPU_SECUREP31,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SPU_SECUREP32,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "SPU_SECUREP33,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SPU_SECUREP34,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "SPU_SECUREP35,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SPU_SECUREP36,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SPU_SECUREP37,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SPU_SECUREP38,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SPU_SECUREP39,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SPU_SECUREP40,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SPU_SECUREP41,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SPU_SECUREP42,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SPU_SECUREP43,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SPU_SECUREP44,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "SPU_SECUREP45,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SPU_SECUREP46,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "SPU_SECUREP47,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SPU_SECUREP48,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "SPU_SECUREP49,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SPU_SECUREP50,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "SPU_SECUREP51,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SPU_SECUREP52,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "SPU_SECUREP53,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SPU_SECUREP54,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "SPU_SECUREP55,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SPU_SECUREP56,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "SPU_SECUREP57,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SPU_SECUREP58,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "SPU_SECUREP59,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SPU_SECUREP60,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "SPU_SECUREP61,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SPU_SECUREP62,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "SPU_SECUREP63,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SPU_SECUREP64,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "SPU_SECUREP65,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SPU_SECUREP66,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "SPU_SECUREP67,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SPU_SECUREP68,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "SPU_SECUREP69,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SPU_SECUREP70,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "SPU_SECUREP71,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SPU_SECUREP72,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "SPU_SECUREP73,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SPU_SECUREP74,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "SPU_SECUREP75,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SPU_SECUREP76,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "SPU_SECUREP77,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SPU_SECUREP78,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "SPU_SECUREP79,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SPU_SECUREP80,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "SPU_SECUREP81,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SPU_SECUREP82,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "SPU_SECUREP83,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SPU_SECUREP84,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "SPU_SECUREP85,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SPU_SECUREP86,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "SPU_SECUREP87,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SPU_SECUREP88,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "SPU_SECUREP89,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SPU_SECUREP90,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "SPU_SECUREP91,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SPU_SECUREP92,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "SPU_SECUREP93,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SPU_SECUREP94,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "SPU_SECUREP95,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SPU_SECUREP96,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "SPU_SECUREP97,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SPU_SECUREP98,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "SPU_SECUREP99,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SPU_SECUREP100,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "SPU_SECUREP101,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SPU_SECUREP102,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "SPU_SECUREP103,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SPU_SECUREP104,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "SPU_SECUREP105,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SPU_SECUREP106,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "SPU_SECUREP107,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SPU_SECUREP108,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "SPU_SECUREP109,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SPU_SECUREP110,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "SPU_SECUREP111,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SPU_SECUREP112,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "SPU_SECUREP113,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SPU_SECUREP114,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "SPU_SECUREP115,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SPU_SECUREP116,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "SPU_SECUREP117,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SPU_SECUREP118,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "SPU_SECUREP119,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SPU_SECUREP120,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "SPU_SECUREP121,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SPU_SECUREP122,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "SPU_SECUREP123,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SPU_SECUREP124,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "SPU_SECUREP125,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SPU_SECUREP126,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xBFC++0x03
|
|
line.long 0x00 "SPU_SECUREP127,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SPU_SECUREP128,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "SPU_SECUREP129,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SPU_SECUREP130,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "SPU_SECUREP131,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SPU_SECUREP132,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "SPU_SECUREP133,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SPU_SECUREP134,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "SPU_SECUREP135,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SPU_SECUREP136,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "SPU_SECUREP137,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SPU_SECUREP138,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "SPU_SECUREP139,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SPU_SECUREP140,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "SPU_SECUREP141,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SPU_SECUREP142,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "SPU_SECUREP143,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SPU_SECUREP144,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "SPU_SECUREP145,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SPU_SECUREP146,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "SPU_SECUREP147,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SPU_SECUREP148,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "SPU_SECUREP149,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SPU_SECUREP150,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "SPU_SECUREP151,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SPU_SECUREP152,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "SPU_SECUREP153,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SPU_SECUREP154,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "SPU_SECUREP155,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SPU_SECUREP156,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "SPU_SECUREP157,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SPU_SECUREP158,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "SPU_SECUREP159,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SPU_SECUREP160,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "SPU_SECUREP161,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SPU_SECUREP162,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "SPU_SECUREP163,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SPU_SECUREP164,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "SPU_SECUREP165,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SPU_SECUREP166,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "SPU_SECUREP167,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SPU_SECUREP168,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "SPU_SECUREP169,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SPU_SECUREP170,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "SPU_SECUREP171,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SPU_SECUREP172,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "SPU_SECUREP173,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SPU_SECUREP174,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "SPU_SECUREP175,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SPU_SECUREP176,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "SPU_SECUREP177,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SPU_SECUREP178,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "SPU_SECUREP179,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SPU_SECUREP180,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "SPU_SECUREP181,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SPU_SECUREP182,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "SPU_SECUREP183,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SPU_SECUREP184,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "SPU_SECUREP185,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SPU_SECUREP186,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "SPU_SECUREP187,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SPU_SECUREP188,SPU Secure Peripheral Register"
|
|
bitfld.long 0x00 1. " MSEC ,Master secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSEC ,Slave secure enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPM (Dynamic Power Management)"
|
|
base ad:0x40017000
|
|
width 25.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 3. " DEEPSLEEP ,Deep sleep" "No action,Deep sleep"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No,Yes"
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No action,Set"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 3. " DEEPSLEEP ,Deep sleep" "No action,Deep sleep"
|
|
bitfld.long 0x00 2. " PLLDIS ,PLL disable" "No,Yes"
|
|
bitfld.long 0x00 1. " PLLBPCL ,PLL bypass clear" "No action,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLLBPST ,PLL bypass set" "No action,Set"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DPM_CTL,DPM Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DPM_STAT,DPM Status Register"
|
|
eventfld.long 0x00 19. " PLLCFGERR ,PLL configuration error" "Inactive,Active"
|
|
eventfld.long 0x00 18. " HVBSYERR ,HV Busy Error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock Write Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ADDRERR ,Address Error" "No error,Error"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HVBSY ,HV busy" "Ready,Busy"
|
|
rbitfld.long 0x00 8. " CCLKDIS ,Core clocks disabled" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " PRVMODE ,Previous Mode" "Reset,Full-On,Active,Active with PLL disabled,Deep sleep,?..."
|
|
rbitfld.long 0x00 0.--3. " CURMODE ,Current Mode" ",Full-On,Active,Active with PLL disabled,?..."
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x00 4.--7. " PRVMODE ,Previous Mode" "Reset,Full-On,?..."
|
|
rbitfld.long 0x00 0.--3. " CURMODE ,Current Mode" ",Full-On,?..."
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DPM0_CCBF_DIS,DPM0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPM0_CCBF_DIS,DPM0 Core Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x0C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DPM0_CCBF_EN,DPM0 Core Clock Buffer Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DPM0_CCBF_EN,DPM0 Core Clock Buffer Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "No action,Buffer disabled"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DPM0_CCBF_STAT,DPM0 Core Clock Buffer Status Register"
|
|
rbitfld.long 0x00 0. " CCBF0 ,Core clock buffer 0 disable" "Buffer Enabled,Buffer Disabled"
|
|
line.long 0x04 "DPM0_CCBF_STAT_STKY,DPM0 Core Clock Buffer Status Sticky Register"
|
|
eventfld.long 0x04 0. " CCBF0 ,Core clock buffer 0 disable" "Buffer Enabled,Buffer Disabled"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x18))&0x80000000)==0x80000000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DPM0_SCBF_DIS,DPM0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--1. " SCBF ,System clock buffer disable" "Buffer enabled,,,Buffer Disabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DPM0_SCBF_DIS,DPM0 System Clock Buffer Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--1. " SCBF ,System clock buffer disable" "Buffer enabled,,,Buffer Disabled"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DPM0_WAKE_EN,DPM0 Wakeup Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DPM0_WAKE_EN,DPM0 Wakeup Enable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DPM0_WAKE_POL,DPM0 Wakeup Polarity Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DPM0_WAKE_POL,DPM0 Wakeup Polarity Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source enable 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source enable 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source enable 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source enable 0" "Low,High"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPM0_WAKE_STAT,DPM0 Wakeup Status Register"
|
|
eventfld.long 0x00 4. " WS[4] ,Wakeup source enable 4" "No action,Enabled"
|
|
eventfld.long 0x00 3. " [3] ,Wakeup source enable 3" "No action,Enabled"
|
|
eventfld.long 0x00 2. " [2] ,Wakeup source enable 2" "No action,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,Wakeup source enable 1" "No action,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Wakeup source enable 0" "No action,Enabled"
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " CAN1 ,CAN1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " CAN0 ,CAN0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SMPU-DMC0 ,SMPU-DMC0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 21. " SMPU-L2CTL-DL2-0 ,SMPU-L2CTL-DL2-0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 20. " SMPU-L2CTL-CL2-0 ,SMPU-L2CTL-CL2-0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SMPU-SMC ,SMPU-SMC Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 17. " EIP-93/PKP ,CRYPTO ACCELERATOR-1 (EIP-93/PKP) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EIP-150/PKP ,CRYPTO ACCELERATOR-0 (EIP-150/PKP) Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLMDMA1 ,DLMDMA1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DLMDMA0 ,DLMDMA0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " MSI0 ,MSI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMAC0 ,EMAC0 (GigE) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " MLB0 ,MLB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DAI0 ,DAI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IIR0 ,IIR0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FIR0 ,FIR0 Value Peripheral Disable" "No,Yes"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " CAN1 ,CAN1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 29. " CAN0 ,CAN0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SMPU-DMC0 ,SMPU-DMC0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 21. " SMPU-L2CTL-DL2-0 ,SMPU-L2CTL-DL2-0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 20. " SMPU-L2CTL-CL2-0 ,SMPU-L2CTL-CL2-0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SMPU-SMC ,SMPU-SMC Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 17. " EIP-93/PKP ,CRYPTO ACCELERATOR-1 (EIP-93/PKP) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EIP-150/PKP ,CRYPTO ACCELERATOR-0 (EIP-150/PKP) Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLMDMA1 ,DLMDMA1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DLMDMA0 ,DLMDMA0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " MSI0 ,MSI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMAC0 ,EMAC0 (GigE) Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " MLB0 ,MLB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DAI0 ,DAI0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IIR0 ,IIR0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FIR0 ,FIR0 Value Peripheral Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--30. 1. " VALUE ,Peripheral Disable"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DPM_PER_DIS0,DPM Peripherals Disable Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long 0x00 0.--30. 1. " VALUE ,Peripheral Disable"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40017000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 15. " C0 ,C0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " C2_L1BK3 ,C2_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " C2_L1BK2 ,C2_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " C2_L1BK1 ,C2_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " C2_L1BK0 ,C2_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2_L1CBTB ,C2_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " C1_L1BK3 ,C1_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " C1_L1BK2 ,C1_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " C1_L1BK1 ,C1_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " C1_L1BK0 ,C1_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " C1_L1CBTB ,C1_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB0 ,USB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TWI2 ,TWI2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TWI1 ,TWI1 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TWI0 ,TWI0 Value Peripheral Disable" "No,Yes"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 15. " C0 ,C0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " C2_L1BK3 ,C2_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " C2_L1BK2 ,C2_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 12. " C2_L1BK1 ,C2_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " C2_L1BK0 ,C2_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2_L1CBTB ,C2_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 9. " C1_L1BK3 ,C1_L1BK3 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " C1_L1BK2 ,C1_L1BK2 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " C1_L1BK1 ,C1_L1BK1 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 6. " C1_L1BK0 ,C1_L1BK0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " C1_L1CBTB ,C1_L1CBTB Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB0 ,USB0 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TWI2 ,TWI2 Value Peripheral Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TWI1 ,TWI1 Value Peripheral Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TWI0 ,TWI0 Value Peripheral Disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " VALUE ,Peripheral Disable"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DPM_PER_DIS1,DPM Peripherals Disable Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock Bit" "Unlocked,Locked"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " VALUE ,Peripheral Disable"
|
|
endif
|
|
endif
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DPM_REVID,DPM Revision ID"
|
|
bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SEC (System Event Controller)"
|
|
base ad:0x40028000
|
|
width 16.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,SEC Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SEC_GCTL,SEC Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SEC_GSTAT,SEC Global Status Register"
|
|
eventfld.long 0x00 31. " LWERR ,Lock Write Error" "No error,Error"
|
|
eventfld.long 0x00 30. " ADRERR ,Address Error" "No error,Error"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " SID ,Source ID for SSI Error"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " SCI ,SCI ID for SCI Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "SFI,,SSI,?..."
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "SFI,SCI,SSI,?..."
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
line.long 0x04 "SEC_RAISE,SEC Global Raise Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SID ,Source ID"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEC_END,SEC Global End Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID IRQ to End"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Active mode,Pending mode"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Active mode,Pending mode"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,SEC Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Fault active,Fault pending"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SEC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SEC_FCTL,SEC Fault Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 13. " TES ,Trigger event select" "Fault active,Fault pending"
|
|
bitfld.long 0x00 12. " CMS ,COP mode select" "Fault,COP"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIEN ,Fault input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SREN ,System reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TOEN ,Trigger output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FOEN ,Fault output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SEC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SEC_FSTAT,SEC Fault Status Register"
|
|
rbitfld.long 0x00 10. " NPND ,Next pending fault" "Not pending,Pending"
|
|
rbitfld.long 0x00 9. " ACT ,Fault active" "Not active,Active"
|
|
rbitfld.long 0x00 8. " PND ,Pending fault" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*")||cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow error,,End error,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",,End error,?..."
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SEC_FSID,SEC Fault Source ID Register"
|
|
bitfld.long 0x00 16. " FEXT ,Fault external" "Internal,External"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SEC_FEND,SEC Fault End Register"
|
|
bitfld.long 0x00 16. " FEXT ,Fault external" "Internal,External"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SEC_FDLY,SEC Fault Delay Register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SEC_FDLY_CUR,SEC Fault Delay Current Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SEC_FSRDLY,SEC Fault System Reset Delay Register"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SEC_FSRDLY_CUR,SEC Fault System Reset Delay Current Register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SEC_FCOPP,SEC Fault COP Period Register"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SEC_FCOPP_CUR,SEC Fault COP Period Current Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x440))&0x80000000)==0x80000000)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x440))&0x80000000)==0x80000000)
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "SEC_CCTL1,SEC SCI Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x440+0x04)++0x03
|
|
line.long 0x00 "SEC_CSTAT1,SEC SCI Status Register 1"
|
|
eventfld.long 0x00 16. " NMI ,NMI" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " WFI ,Wait for idle" "Not waiting,Waiting"
|
|
rbitfld.long 0x00 10. " SIDV ,SID valid" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " ACTV ,ACT valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 8. " PNDV ,PND valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",ACK error,?..."
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long (0x440+0x08)++0x03
|
|
line.long 0x00 "SEC_CPND1,SEC Core Pending Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest pending IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest pending IRQ source ID"
|
|
rgroup.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "SEC_CACT1,SEC SCI Active Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest active IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest active IRQ source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x440+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x440+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x440+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK1,SEC SCI Priority Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x454))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x440+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK1,SEC SCI Group Mask Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x440+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x440+0x18)++0x3
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x440+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x440+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL1,SEC SCI Priority Level Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
endif
|
|
rgroup.long (0x440+0x1C)++0x03
|
|
line.long 0x00 "SEC_CSID1,SEC SCI Source ID Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x480))&0x80000000)==0x80000000)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x480))&0x80000000)==0x80000000)
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "SEC_CCTL2,SEC SCI Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 16. " NMIEN ,NMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WFI ,Wait for idle" "No action,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,SCI enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x480+0x04)++0x03
|
|
line.long 0x00 "SEC_CSTAT2,SEC SCI Status Register 2"
|
|
eventfld.long 0x00 16. " NMI ,NMI" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " WFI ,Wait for idle" "Not waiting,Waiting"
|
|
rbitfld.long 0x00 10. " SIDV ,SID valid" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " ACTV ,ACT valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 8. " PNDV ,PND valid" "Invalid,Valid"
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" ",ACK error,?..."
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
rgroup.long (0x480+0x08)++0x03
|
|
line.long 0x00 "SEC_CPND2,SEC Core Pending Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest pending IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest pending IRQ source ID"
|
|
rgroup.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "SEC_CACT2,SEC SCI Active Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest active IRQ priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest active IRQ source ID"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x480+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x480+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
else
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "SEC_CPMSK2,SEC SCI Priority Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ priority mask"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x454))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x480+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
else
|
|
group.long (0x480+0x14)++0x03
|
|
line.long 0x00 "SEC_CGMSK2,SEC SCI Group Mask Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 8. " UGRP ,Ungrouped mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " GRP[3] ,Grouped mask-group 3" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Grouped mask-group 2" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Grouped mask-group 1" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Grouped mask-group 0" "Unmasked,Masked"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x480+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x480+0x18)++0x3
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x480+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
else
|
|
group.long (0x480+0x18)++0x03
|
|
line.long 0x00 "SEC_CPLVL2,SEC SCI Priority Level Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 0.--2. " PLVL ,Priority levels" "2,4,8,16,32,64,128,256"
|
|
endif
|
|
endif
|
|
rgroup.long (0x480+0x1C)++0x03
|
|
line.long 0x00 "SEC_CSID2,SEC SCI Source ID Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x800+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT0,SEC Source Status Register 0"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x808+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT1,SEC Source Status Register 1"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x810+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT2,SEC Source Status Register 2"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x818+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT3,SEC Source Status Register 3"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x820+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT4,SEC Source Status Register 4"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x828+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT5,SEC Source Status Register 5"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x830+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT6,SEC Source Status Register 6"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x838+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT7,SEC Source Status Register 7"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x840+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT8,SEC Source Status Register 8"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x848+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT9,SEC Source Status Register 9"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x850+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT10,SEC Source Status Register 10"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x858+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT11,SEC Source Status Register 11"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x860+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT12,SEC Source Status Register 12"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x868+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT13,SEC Source Status Register 13"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x870+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT14,SEC Source Status Register 14"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x878+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT15,SEC Source Status Register 15"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x880+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT16,SEC Source Status Register 16"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x888+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT17,SEC Source Status Register 17"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x890+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT18,SEC Source Status Register 18"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x898+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT19,SEC Source Status Register 19"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT20,SEC Source Status Register 20"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT21,SEC Source Status Register 21"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT22,SEC Source Status Register 22"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT23,SEC Source Status Register 23"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT24,SEC Source Status Register 24"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT25,SEC Source Status Register 25"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT26,SEC Source Status Register 26"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT27,SEC Source Status Register 27"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT28,SEC Source Status Register 28"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT29,SEC Source Status Register 29"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT30,SEC Source Status Register 30"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x8F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT31,SEC Source Status Register 31"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x900+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT32,SEC Source Status Register 32"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x908+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT33,SEC Source Status Register 33"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x910+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT34,SEC Source Status Register 34"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x918+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT35,SEC Source Status Register 35"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x920+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT36,SEC Source Status Register 36"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x928+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT37,SEC Source Status Register 37"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x930+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT38,SEC Source Status Register 38"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x938+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT39,SEC Source Status Register 39"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x940+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT40,SEC Source Status Register 40"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x948+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT41,SEC Source Status Register 41"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x950+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT42,SEC Source Status Register 42"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x958+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT43,SEC Source Status Register 43"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x960+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT44,SEC Source Status Register 44"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x968+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT45,SEC Source Status Register 45"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x970+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT46,SEC Source Status Register 46"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x978+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT47,SEC Source Status Register 47"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x980+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT48,SEC Source Status Register 48"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x988+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT49,SEC Source Status Register 49"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x990+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT50,SEC Source Status Register 50"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x998+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT51,SEC Source Status Register 51"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT52,SEC Source Status Register 52"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT53,SEC Source Status Register 53"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT54,SEC Source Status Register 54"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT55,SEC Source Status Register 55"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT56,SEC Source Status Register 56"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT57,SEC Source Status Register 57"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT58,SEC Source Status Register 58"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT59,SEC Source Status Register 59"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT60,SEC Source Status Register 60"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT61,SEC Source Status Register 61"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT62,SEC Source Status Register 62"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x9F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT63,SEC Source Status Register 63"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT64,SEC Source Status Register 64"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT65,SEC Source Status Register 65"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT66,SEC Source Status Register 66"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT67,SEC Source Status Register 67"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT68,SEC Source Status Register 68"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT69,SEC Source Status Register 69"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT70,SEC Source Status Register 70"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT71,SEC Source Status Register 71"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT72,SEC Source Status Register 72"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT73,SEC Source Status Register 73"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT74,SEC Source Status Register 74"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT75,SEC Source Status Register 75"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT76,SEC Source Status Register 76"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT77,SEC Source Status Register 77"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT78,SEC Source Status Register 78"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT79,SEC Source Status Register 79"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT80,SEC Source Status Register 80"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT81,SEC Source Status Register 81"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT82,SEC Source Status Register 82"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT83,SEC Source Status Register 83"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT84,SEC Source Status Register 84"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT85,SEC Source Status Register 85"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT86,SEC Source Status Register 86"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT87,SEC Source Status Register 87"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT88,SEC Source Status Register 88"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT89,SEC Source Status Register 89"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT90,SEC Source Status Register 90"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT91,SEC Source Status Register 91"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT92,SEC Source Status Register 92"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT93,SEC Source Status Register 93"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT94,SEC Source Status Register 94"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xAF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT95,SEC Source Status Register 95"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT96,SEC Source Status Register 96"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT97,SEC Source Status Register 97"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT98,SEC Source Status Register 98"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT99,SEC Source Status Register 99"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT100,SEC Source Status Register 100"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT101,SEC Source Status Register 101"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT102,SEC Source Status Register 102"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT103,SEC Source Status Register 103"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT104,SEC Source Status Register 104"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT105,SEC Source Status Register 105"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT106,SEC Source Status Register 106"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT107,SEC Source Status Register 107"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT108,SEC Source Status Register 108"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT109,SEC Source Status Register 109"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT110,SEC Source Status Register 110"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT111,SEC Source Status Register 111"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT112,SEC Source Status Register 112"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT113,SEC Source Status Register 113"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT114,SEC Source Status Register 114"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT115,SEC Source Status Register 115"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT116,SEC Source Status Register 116"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT117,SEC Source Status Register 117"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT118,SEC Source Status Register 118"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT119,SEC Source Status Register 119"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT120,SEC Source Status Register 120"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT121,SEC Source Status Register 121"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT122,SEC Source Status Register 122"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT123,SEC Source Status Register 123"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT124,SEC Source Status Register 124"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT125,SEC Source Status Register 125"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT126,SEC Source Status Register 126"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xBF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT127,SEC Source Status Register 127"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT128,SEC Source Status Register 128"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
else
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x800))&0x80000000)==0x80000000)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SEC_SCTL0,SEC Source Control Register 0"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x800+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT0,SEC Source Status Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x808))&0x80000000)==0x80000000)
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SEC_SCTL1,SEC Source Control Register 1"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x808+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT1,SEC Source Status Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x810))&0x80000000)==0x80000000)
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "SEC_SCTL2,SEC Source Control Register 2"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x810+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT2,SEC Source Status Register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x818))&0x80000000)==0x80000000)
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "SEC_SCTL3,SEC Source Control Register 3"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x818+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT3,SEC Source Status Register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x820))&0x80000000)==0x80000000)
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SEC_SCTL4,SEC Source Control Register 4"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x820+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT4,SEC Source Status Register 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x828))&0x80000000)==0x80000000)
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SEC_SCTL5,SEC Source Control Register 5"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x828+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT5,SEC Source Status Register 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x830))&0x80000000)==0x80000000)
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "SEC_SCTL6,SEC Source Control Register 6"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x830+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT6,SEC Source Status Register 6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x838))&0x80000000)==0x80000000)
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SEC_SCTL7,SEC Source Control Register 7"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x838+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT7,SEC Source Status Register 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x840))&0x80000000)==0x80000000)
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SEC_SCTL8,SEC Source Control Register 8"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x840+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT8,SEC Source Status Register 8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x848))&0x80000000)==0x80000000)
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "SEC_SCTL9,SEC Source Control Register 9"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x848+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT9,SEC Source Status Register 9"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x850))&0x80000000)==0x80000000)
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SEC_SCTL10,SEC Source Control Register 10"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x850+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT10,SEC Source Status Register 10"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x858))&0x80000000)==0x80000000)
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SEC_SCTL11,SEC Source Control Register 11"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x858+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT11,SEC Source Status Register 11"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x860))&0x80000000)==0x80000000)
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "SEC_SCTL12,SEC Source Control Register 12"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x860+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT12,SEC Source Status Register 12"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x868))&0x80000000)==0x80000000)
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "SEC_SCTL13,SEC Source Control Register 13"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x868+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT13,SEC Source Status Register 13"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x870))&0x80000000)==0x80000000)
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "SEC_SCTL14,SEC Source Control Register 14"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x870+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT14,SEC Source Status Register 14"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x878))&0x80000000)==0x80000000)
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "SEC_SCTL15,SEC Source Control Register 15"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x878+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT15,SEC Source Status Register 15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x880))&0x80000000)==0x80000000)
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "SEC_SCTL16,SEC Source Control Register 16"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x880+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT16,SEC Source Status Register 16"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x888))&0x80000000)==0x80000000)
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "SEC_SCTL17,SEC Source Control Register 17"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x888+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT17,SEC Source Status Register 17"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x890))&0x80000000)==0x80000000)
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "SEC_SCTL18,SEC Source Control Register 18"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x890+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT18,SEC Source Status Register 18"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x898))&0x80000000)==0x80000000)
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "SEC_SCTL19,SEC Source Control Register 19"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x898+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT19,SEC Source Status Register 19"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "SEC_SCTL20,SEC Source Control Register 20"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT20,SEC Source Status Register 20"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "SEC_SCTL21,SEC Source Control Register 21"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT21,SEC Source Status Register 21"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "SEC_SCTL22,SEC Source Control Register 22"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT22,SEC Source Status Register 22"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "SEC_SCTL23,SEC Source Control Register 23"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT23,SEC Source Status Register 23"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "SEC_SCTL24,SEC Source Control Register 24"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT24,SEC Source Status Register 24"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "SEC_SCTL25,SEC Source Control Register 25"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT25,SEC Source Status Register 25"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "SEC_SCTL26,SEC Source Control Register 26"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT26,SEC Source Status Register 26"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "SEC_SCTL27,SEC Source Control Register 27"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT27,SEC Source Status Register 27"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "SEC_SCTL28,SEC Source Control Register 28"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT28,SEC Source Status Register 28"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "SEC_SCTL29,SEC Source Control Register 29"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT29,SEC Source Status Register 29"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "SEC_SCTL30,SEC Source Control Register 30"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT30,SEC Source Status Register 30"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x8F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "SEC_SCTL31,SEC Source Control Register 31"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x8F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT31,SEC Source Status Register 31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x900))&0x80000000)==0x80000000)
|
|
rgroup.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "SEC_SCTL32,SEC Source Control Register 32"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x900+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT32,SEC Source Status Register 32"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x908))&0x80000000)==0x80000000)
|
|
rgroup.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "SEC_SCTL33,SEC Source Control Register 33"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x908+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT33,SEC Source Status Register 33"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x910))&0x80000000)==0x80000000)
|
|
rgroup.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "SEC_SCTL34,SEC Source Control Register 34"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x910+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT34,SEC Source Status Register 34"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x918))&0x80000000)==0x80000000)
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "SEC_SCTL35,SEC Source Control Register 35"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x918+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT35,SEC Source Status Register 35"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x920))&0x80000000)==0x80000000)
|
|
rgroup.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "SEC_SCTL36,SEC Source Control Register 36"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x920+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT36,SEC Source Status Register 36"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x928))&0x80000000)==0x80000000)
|
|
rgroup.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "SEC_SCTL37,SEC Source Control Register 37"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x928+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT37,SEC Source Status Register 37"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x930))&0x80000000)==0x80000000)
|
|
rgroup.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "SEC_SCTL38,SEC Source Control Register 38"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x930+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT38,SEC Source Status Register 38"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x938))&0x80000000)==0x80000000)
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "SEC_SCTL39,SEC Source Control Register 39"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x938+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT39,SEC Source Status Register 39"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x940))&0x80000000)==0x80000000)
|
|
rgroup.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "SEC_SCTL40,SEC Source Control Register 40"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x940+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT40,SEC Source Status Register 40"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x948))&0x80000000)==0x80000000)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "SEC_SCTL41,SEC Source Control Register 41"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x948+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT41,SEC Source Status Register 41"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x950))&0x80000000)==0x80000000)
|
|
rgroup.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "SEC_SCTL42,SEC Source Control Register 42"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x950+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT42,SEC Source Status Register 42"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x958))&0x80000000)==0x80000000)
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "SEC_SCTL43,SEC Source Control Register 43"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x958+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT43,SEC Source Status Register 43"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x960))&0x80000000)==0x80000000)
|
|
rgroup.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "SEC_SCTL44,SEC Source Control Register 44"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x960+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT44,SEC Source Status Register 44"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x968))&0x80000000)==0x80000000)
|
|
rgroup.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "SEC_SCTL45,SEC Source Control Register 45"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x968+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT45,SEC Source Status Register 45"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x970))&0x80000000)==0x80000000)
|
|
rgroup.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "SEC_SCTL46,SEC Source Control Register 46"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x970+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT46,SEC Source Status Register 46"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x978))&0x80000000)==0x80000000)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "SEC_SCTL47,SEC Source Control Register 47"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x978+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT47,SEC Source Status Register 47"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x980))&0x80000000)==0x80000000)
|
|
rgroup.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "SEC_SCTL48,SEC Source Control Register 48"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x980+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT48,SEC Source Status Register 48"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x988))&0x80000000)==0x80000000)
|
|
rgroup.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "SEC_SCTL49,SEC Source Control Register 49"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x988+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT49,SEC Source Status Register 49"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x990))&0x80000000)==0x80000000)
|
|
rgroup.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "SEC_SCTL50,SEC Source Control Register 50"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x990+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT50,SEC Source Status Register 50"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x998))&0x80000000)==0x80000000)
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "SEC_SCTL51,SEC Source Control Register 51"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x998+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT51,SEC Source Status Register 51"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "SEC_SCTL52,SEC Source Control Register 52"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9A0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT52,SEC Source Status Register 52"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "SEC_SCTL53,SEC Source Control Register 53"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9A8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT53,SEC Source Status Register 53"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "SEC_SCTL54,SEC Source Control Register 54"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9B0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT54,SEC Source Status Register 54"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "SEC_SCTL55,SEC Source Control Register 55"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9B8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT55,SEC Source Status Register 55"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "SEC_SCTL56,SEC Source Control Register 56"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9C0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT56,SEC Source Status Register 56"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "SEC_SCTL57,SEC Source Control Register 57"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9C8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT57,SEC Source Status Register 57"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "SEC_SCTL58,SEC Source Control Register 58"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9D0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT58,SEC Source Status Register 58"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "SEC_SCTL59,SEC Source Control Register 59"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9D8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT59,SEC Source Status Register 59"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "SEC_SCTL60,SEC Source Control Register 60"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9E0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT60,SEC Source Status Register 60"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "SEC_SCTL61,SEC Source Control Register 61"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9E8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT61,SEC Source Status Register 61"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9F0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "SEC_SCTL62,SEC Source Control Register 62"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9F0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT62,SEC Source Status Register 62"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x9F8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "SEC_SCTL63,SEC Source Control Register 63"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x9F8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT63,SEC Source Status Register 63"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "SEC_SCTL64,SEC Source Control Register 64"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT64,SEC Source Status Register 64"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "SEC_SCTL65,SEC Source Control Register 65"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT65,SEC Source Status Register 65"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "SEC_SCTL66,SEC Source Control Register 66"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT66,SEC Source Status Register 66"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "SEC_SCTL67,SEC Source Control Register 67"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT67,SEC Source Status Register 67"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "SEC_SCTL68,SEC Source Control Register 68"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT68,SEC Source Status Register 68"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "SEC_SCTL69,SEC Source Control Register 69"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT69,SEC Source Status Register 69"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "SEC_SCTL70,SEC Source Control Register 70"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT70,SEC Source Status Register 70"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "SEC_SCTL71,SEC Source Control Register 71"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT71,SEC Source Status Register 71"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "SEC_SCTL72,SEC Source Control Register 72"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT72,SEC Source Status Register 72"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "SEC_SCTL73,SEC Source Control Register 73"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT73,SEC Source Status Register 73"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "SEC_SCTL74,SEC Source Control Register 74"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT74,SEC Source Status Register 74"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "SEC_SCTL75,SEC Source Control Register 75"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT75,SEC Source Status Register 75"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "SEC_SCTL76,SEC Source Control Register 76"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT76,SEC Source Status Register 76"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "SEC_SCTL77,SEC Source Control Register 77"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT77,SEC Source Status Register 77"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "SEC_SCTL78,SEC Source Control Register 78"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT78,SEC Source Status Register 78"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "SEC_SCTL79,SEC Source Control Register 79"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT79,SEC Source Status Register 79"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "SEC_SCTL80,SEC Source Control Register 80"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT80,SEC Source Status Register 80"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SEC_SCTL81,SEC Source Control Register 81"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT81,SEC Source Status Register 81"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "SEC_SCTL82,SEC Source Control Register 82"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT82,SEC Source Status Register 82"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xA98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SEC_SCTL83,SEC Source Control Register 83"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xA98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT83,SEC Source Status Register 83"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SEC_SCTL84,SEC Source Control Register 84"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT84,SEC Source Status Register 84"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SEC_SCTL85,SEC Source Control Register 85"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT85,SEC Source Status Register 85"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SEC_SCTL86,SEC Source Control Register 86"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT86,SEC Source Status Register 86"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "SEC_SCTL87,SEC Source Control Register 87"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT87,SEC Source Status Register 87"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "SEC_SCTL88,SEC Source Control Register 88"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT88,SEC Source Status Register 88"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "SEC_SCTL89,SEC Source Control Register 89"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT89,SEC Source Status Register 89"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "SEC_SCTL90,SEC Source Control Register 90"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT90,SEC Source Status Register 90"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "SEC_SCTL91,SEC Source Control Register 91"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT91,SEC Source Status Register 91"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "SEC_SCTL92,SEC Source Control Register 92"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT92,SEC Source Status Register 92"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "SEC_SCTL93,SEC Source Control Register 93"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT93,SEC Source Status Register 93"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "SEC_SCTL94,SEC Source Control Register 94"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT94,SEC Source Status Register 94"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xAF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "SEC_SCTL95,SEC Source Control Register 95"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xAF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT95,SEC Source Status Register 95"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "SEC_SCTL96,SEC Source Control Register 96"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT96,SEC Source Status Register 96"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "SEC_SCTL97,SEC Source Control Register 97"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT97,SEC Source Status Register 97"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "SEC_SCTL98,SEC Source Control Register 98"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT98,SEC Source Status Register 98"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "SEC_SCTL99,SEC Source Control Register 99"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT99,SEC Source Status Register 99"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "SEC_SCTL100,SEC Source Control Register 100"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT100,SEC Source Status Register 100"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "SEC_SCTL101,SEC Source Control Register 101"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT101,SEC Source Status Register 101"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "SEC_SCTL102,SEC Source Control Register 102"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT102,SEC Source Status Register 102"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "SEC_SCTL103,SEC Source Control Register 103"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT103,SEC Source Status Register 103"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "SEC_SCTL104,SEC Source Control Register 104"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT104,SEC Source Status Register 104"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "SEC_SCTL105,SEC Source Control Register 105"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT105,SEC Source Status Register 105"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "SEC_SCTL106,SEC Source Control Register 106"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT106,SEC Source Status Register 106"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "SEC_SCTL107,SEC Source Control Register 107"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT107,SEC Source Status Register 107"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "SEC_SCTL108,SEC Source Control Register 108"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT108,SEC Source Status Register 108"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "SEC_SCTL109,SEC Source Control Register 109"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT109,SEC Source Status Register 109"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "SEC_SCTL110,SEC Source Control Register 110"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT110,SEC Source Status Register 110"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "SEC_SCTL111,SEC Source Control Register 111"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT111,SEC Source Status Register 111"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "SEC_SCTL112,SEC Source Control Register 112"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT112,SEC Source Status Register 112"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "SEC_SCTL113,SEC Source Control Register 113"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT113,SEC Source Status Register 113"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "SEC_SCTL114,SEC Source Control Register 114"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT114,SEC Source Status Register 114"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xB98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "SEC_SCTL115,SEC Source Control Register 115"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xB98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT115,SEC Source Status Register 115"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "SEC_SCTL116,SEC Source Control Register 116"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT116,SEC Source Status Register 116"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "SEC_SCTL117,SEC Source Control Register 117"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT117,SEC Source Status Register 117"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "SEC_SCTL118,SEC Source Control Register 118"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT118,SEC Source Status Register 118"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "SEC_SCTL119,SEC Source Control Register 119"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT119,SEC Source Status Register 119"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "SEC_SCTL120,SEC Source Control Register 120"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT120,SEC Source Status Register 120"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "SEC_SCTL121,SEC Source Control Register 121"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT121,SEC Source Status Register 121"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "SEC_SCTL122,SEC Source Control Register 122"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT122,SEC Source Status Register 122"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "SEC_SCTL123,SEC Source Control Register 123"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT123,SEC Source Status Register 123"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "SEC_SCTL124,SEC Source Control Register 124"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT124,SEC Source Status Register 124"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "SEC_SCTL125,SEC Source Control Register 125"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT125,SEC Source Status Register 125"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "SEC_SCTL126,SEC Source Control Register 126"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT126,SEC Source Status Register 126"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xBF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "SEC_SCTL127,SEC Source Control Register 127"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xBF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT127,SEC Source Status Register 127"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "SEC_SCTL128,SEC Source Control Register 128"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT128,SEC Source Status Register 128"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "SEC_SCTL129,SEC Source Control Register 129"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT129,SEC Source Status Register 129"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "SEC_SCTL130,SEC Source Control Register 130"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT130,SEC Source Status Register 130"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "SEC_SCTL131,SEC Source Control Register 131"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT131,SEC Source Status Register 131"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "SEC_SCTL132,SEC Source Control Register 132"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT132,SEC Source Status Register 132"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "SEC_SCTL133,SEC Source Control Register 133"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT133,SEC Source Status Register 133"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "SEC_SCTL134,SEC Source Control Register 134"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT134,SEC Source Status Register 134"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "SEC_SCTL135,SEC Source Control Register 135"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT135,SEC Source Status Register 135"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "SEC_SCTL136,SEC Source Control Register 136"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT136,SEC Source Status Register 136"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "SEC_SCTL137,SEC Source Control Register 137"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT137,SEC Source Status Register 137"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "SEC_SCTL138,SEC Source Control Register 138"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT138,SEC Source Status Register 138"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "SEC_SCTL139,SEC Source Control Register 139"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT139,SEC Source Status Register 139"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "SEC_SCTL140,SEC Source Control Register 140"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT140,SEC Source Status Register 140"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "SEC_SCTL141,SEC Source Control Register 141"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT141,SEC Source Status Register 141"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "SEC_SCTL142,SEC Source Control Register 142"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT142,SEC Source Status Register 142"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "SEC_SCTL143,SEC Source Control Register 143"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT143,SEC Source Status Register 143"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "SEC_SCTL144,SEC Source Control Register 144"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT144,SEC Source Status Register 144"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "SEC_SCTL145,SEC Source Control Register 145"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT145,SEC Source Status Register 145"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "SEC_SCTL146,SEC Source Control Register 146"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT146,SEC Source Status Register 146"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xC98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xC98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "SEC_SCTL147,SEC Source Control Register 147"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT147,SEC Source Status Register 147"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "SEC_SCTL148,SEC Source Control Register 148"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT148,SEC Source Status Register 148"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "SEC_SCTL149,SEC Source Control Register 149"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT149,SEC Source Status Register 149"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "SEC_SCTL150,SEC Source Control Register 150"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT150,SEC Source Status Register 150"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "SEC_SCTL151,SEC Source Control Register 151"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT151,SEC Source Status Register 151"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "SEC_SCTL152,SEC Source Control Register 152"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT152,SEC Source Status Register 152"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "SEC_SCTL153,SEC Source Control Register 153"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT153,SEC Source Status Register 153"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "SEC_SCTL154,SEC Source Control Register 154"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT154,SEC Source Status Register 154"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "SEC_SCTL155,SEC Source Control Register 155"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT155,SEC Source Status Register 155"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "SEC_SCTL156,SEC Source Control Register 156"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT156,SEC Source Status Register 156"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "SEC_SCTL157,SEC Source Control Register 157"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT157,SEC Source Status Register 157"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "SEC_SCTL158,SEC Source Control Register 158"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT158,SEC Source Status Register 158"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xCF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xCF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "SEC_SCTL159,SEC Source Control Register 159"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xCF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT159,SEC Source Status Register 159"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "SEC_SCTL160,SEC Source Control Register 160"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT160,SEC Source Status Register 160"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "SEC_SCTL161,SEC Source Control Register 161"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT161,SEC Source Status Register 161"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SEC_SCTL162,SEC Source Control Register 162"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT162,SEC Source Status Register 162"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SEC_SCTL163,SEC Source Control Register 163"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT163,SEC Source Status Register 163"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SEC_SCTL164,SEC Source Control Register 164"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT164,SEC Source Status Register 164"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD28++0x03
|
|
line.long 0x00 "SEC_SCTL165,SEC Source Control Register 165"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT165,SEC Source Status Register 165"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "SEC_SCTL166,SEC Source Control Register 166"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT166,SEC Source Status Register 166"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD38++0x03
|
|
line.long 0x00 "SEC_SCTL167,SEC Source Control Register 167"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT167,SEC Source Status Register 167"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "SEC_SCTL168,SEC Source Control Register 168"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT168,SEC Source Status Register 168"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD48++0x03
|
|
line.long 0x00 "SEC_SCTL169,SEC Source Control Register 169"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT169,SEC Source Status Register 169"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD50++0x03
|
|
line.long 0x00 "SEC_SCTL170,SEC Source Control Register 170"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT170,SEC Source Status Register 170"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD58++0x03
|
|
line.long 0x00 "SEC_SCTL171,SEC Source Control Register 171"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT171,SEC Source Status Register 171"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD60++0x03
|
|
line.long 0x00 "SEC_SCTL172,SEC Source Control Register 172"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT172,SEC Source Status Register 172"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD68++0x03
|
|
line.long 0x00 "SEC_SCTL173,SEC Source Control Register 173"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT173,SEC Source Status Register 173"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD70++0x03
|
|
line.long 0x00 "SEC_SCTL174,SEC Source Control Register 174"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT174,SEC Source Status Register 174"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD78++0x03
|
|
line.long 0x00 "SEC_SCTL175,SEC Source Control Register 175"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT175,SEC Source Status Register 175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD80++0x03
|
|
line.long 0x00 "SEC_SCTL176,SEC Source Control Register 176"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT176,SEC Source Status Register 176"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "SEC_SCTL177,SEC Source Control Register 177"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT177,SEC Source Status Register 177"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD90++0x03
|
|
line.long 0x00 "SEC_SCTL178,SEC Source Control Register 178"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT178,SEC Source Status Register 178"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xD98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xD98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "SEC_SCTL179,SEC Source Control Register 179"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xD98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT179,SEC Source Status Register 179"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA0++0x03
|
|
line.long 0x00 "SEC_SCTL180,SEC Source Control Register 180"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDA0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT180,SEC Source Status Register 180"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDA8++0x03
|
|
line.long 0x00 "SEC_SCTL181,SEC Source Control Register 181"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDA8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT181,SEC Source Status Register 181"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB0++0x03
|
|
line.long 0x00 "SEC_SCTL182,SEC Source Control Register 182"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDB0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT182,SEC Source Status Register 182"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDB8++0x03
|
|
line.long 0x00 "SEC_SCTL183,SEC Source Control Register 183"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDB8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT183,SEC Source Status Register 183"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC0++0x03
|
|
line.long 0x00 "SEC_SCTL184,SEC Source Control Register 184"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDC0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT184,SEC Source Status Register 184"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDC8++0x03
|
|
line.long 0x00 "SEC_SCTL185,SEC Source Control Register 185"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDC8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT185,SEC Source Status Register 185"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SEC_SCTL186,SEC Source Control Register 186"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDD0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT186,SEC Source Status Register 186"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SEC_SCTL187,SEC Source Control Register 187"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDD8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT187,SEC Source Status Register 187"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "SEC_SCTL188,SEC Source Control Register 188"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDE0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT188,SEC Source Status Register 188"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SEC_SCTL189,SEC Source Control Register 189"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDE8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT189,SEC Source Status Register 189"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "SEC_SCTL190,SEC Source Control Register 190"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDF0+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT190,SEC Source Status Register 190"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xDF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xDF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "SEC_SCTL191,SEC Source Control Register 191"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xDF8+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT191,SEC Source Status Register 191"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE00))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "SEC_SCTL192,SEC Source Control Register 192"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE00+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT192,SEC Source Status Register 192"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE08))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "SEC_SCTL193,SEC Source Control Register 193"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE08+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT193,SEC Source Status Register 193"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE10))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "SEC_SCTL194,SEC Source Control Register 194"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE10+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT194,SEC Source Status Register 194"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE18))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "SEC_SCTL195,SEC Source Control Register 195"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE18+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT195,SEC Source Status Register 195"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE20))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "SEC_SCTL196,SEC Source Control Register 196"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE20+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT196,SEC Source Status Register 196"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE28))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE28++0x03
|
|
line.long 0x00 "SEC_SCTL197,SEC Source Control Register 197"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE28+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT197,SEC Source Status Register 197"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE30))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "SEC_SCTL198,SEC Source Control Register 198"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE30+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT198,SEC Source Status Register 198"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE38))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "SEC_SCTL199,SEC Source Control Register 199"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE38+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT199,SEC Source Status Register 199"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE40))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "SEC_SCTL200,SEC Source Control Register 200"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE40+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT200,SEC Source Status Register 200"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE48))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE48++0x03
|
|
line.long 0x00 "SEC_SCTL201,SEC Source Control Register 201"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE48+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT201,SEC Source Status Register 201"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE50))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "SEC_SCTL202,SEC Source Control Register 202"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE50+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT202,SEC Source Status Register 202"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE58))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE58++0x03
|
|
line.long 0x00 "SEC_SCTL203,SEC Source Control Register 203"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE58+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT203,SEC Source Status Register 203"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE60))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE60++0x03
|
|
line.long 0x00 "SEC_SCTL204,SEC Source Control Register 204"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE60+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT204,SEC Source Status Register 204"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE68))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE68++0x03
|
|
line.long 0x00 "SEC_SCTL205,SEC Source Control Register 205"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE68+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT205,SEC Source Status Register 205"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE70))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "SEC_SCTL206,SEC Source Control Register 206"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE70+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT206,SEC Source Status Register 206"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE78))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE78++0x03
|
|
line.long 0x00 "SEC_SCTL207,SEC Source Control Register 207"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE78+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT207,SEC Source Status Register 207"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE80))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "SEC_SCTL208,SEC Source Control Register 208"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE80+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT208,SEC Source Status Register 208"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE88))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "SEC_SCTL209,SEC Source Control Register 209"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE88+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT209,SEC Source Status Register 209"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE90))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "SEC_SCTL210,SEC Source Control Register 210"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE90+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT210,SEC Source Status Register 210"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40028000+0xE98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0xE98))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "SEC_SCTL211,SEC Source Control Register 211"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 24.--27. " CTG ,Core target select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GRP ,Group select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority level select"
|
|
bitfld.long 0x00 4. " ERREN ,Error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ES ,Edge select" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEN ,Source (signal) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FEN ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xE98+0x04)++0x03
|
|
line.long 0x00 "SEC_SSTAT211,SEC Source Status Register 211"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID"
|
|
eventfld.long 0x00 9. " ACT ,Active source" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PND ,Pending source" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " ERRC ,Error cause" "Source overflow,,End error,?..."
|
|
eventfld.long 0x00 1. " ERR ,Error" "No error,Error"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRU (Trigger Routing Unit)"
|
|
base ad:0x40015000
|
|
width 13.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
else
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TRU_SSR0,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR0 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR0 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TRU_SSR1,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR1 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR1 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TRU_SSR2,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR2 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR2 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TRU_SSR3,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR3 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR3 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRU_SSR4,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR4 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR4 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x14))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRU_SSR5,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR5 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR5 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x18))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRU_SSR6,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR6 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR6 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRU_SSR7,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR7 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR7 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x20))&0x80000000)==0x80000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRU_SSR8,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR8 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR8 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TRU_SSR9,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR9 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR9 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRU_SSR10,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR10 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR10 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x2C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRU_SSR11,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR11 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR11 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x30))&0x80000000)==0x80000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRU_SSR12,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR12 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR12 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x34))&0x80000000)==0x80000000)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRU_SSR13,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR13 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR13 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x38))&0x80000000)==0x80000000)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRU_SSR14,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR14 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR14 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x3C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRU_SSR15,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR15 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR15 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x40))&0x80000000)==0x80000000)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TRU_SSR16,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR16 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR16 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x44))&0x80000000)==0x80000000)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRU_SSR17,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR17 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR17 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x48))&0x80000000)==0x80000000)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRU_SSR18,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR18 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR18 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x4C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRU_SSR19,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR19 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR19 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x50))&0x80000000)==0x80000000)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRU_SSR20,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR20 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR20 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x54))&0x80000000)==0x80000000)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRU_SSR21,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR21 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR21 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x58))&0x80000000)==0x80000000)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRU_SSR22,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR22 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR22 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x5C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRU_SSR23,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR23 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR23 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x60))&0x80000000)==0x80000000)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRU_SSR24,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR24 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR24 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x64))&0x80000000)==0x80000000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRU_SSR25,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR25 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR25 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x68))&0x80000000)==0x80000000)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TRU_SSR26,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR26 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR26 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x6C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRU_SSR27,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR27 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR27 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x70))&0x80000000)==0x80000000)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRU_SSR28,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR28 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR28 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x74))&0x80000000)==0x80000000)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRU_SSR29,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR29 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR29 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x78))&0x80000000)==0x80000000)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRU_SSR30,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR30 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR30 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x7C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRU_SSR31,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR31 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR31 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x80))&0x80000000)==0x80000000)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRU_SSR32,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR32 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR32 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x84))&0x80000000)==0x80000000)
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TRU_SSR33,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR33 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR33 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x88))&0x80000000)==0x80000000)
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TRU_SSR34,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR34 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR34 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x8C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TRU_SSR35,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR35 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR35 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x90))&0x80000000)==0x80000000)
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TRU_SSR36,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR36 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR36 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x94))&0x80000000)==0x80000000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TRU_SSR37,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR37 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR37 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x98))&0x80000000)==0x80000000)
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRU_SSR38,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR38 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR38 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x9C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TRU_SSR39,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR39 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR39 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xA0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRU_SSR40,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR40 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR40 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xA4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TRU_SSR41,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR41 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR41 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xA8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TRU_SSR42,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR42 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR42 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xAC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TRU_SSR43,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR43 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR43 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xB0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TRU_SSR44,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR44 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR44 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xB4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TRU_SSR45,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR45 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR45 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xB8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TRU_SSR46,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR46 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR46 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xBC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TRU_SSR47,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR47 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR47 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xC0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TRU_SSR48,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR48 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR48 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xC4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TRU_SSR49,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR49 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR49 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xC8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
else
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TRU_SSR50,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR50 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR50 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xCC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TRU_SSR51,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR51 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR51 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xD0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TRU_SSR52,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR52 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR52 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xD4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
else
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TRU_SSR53,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR53 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR53 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xD8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TRU_SSR54,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR54 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR54 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xDC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
else
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TRU_SSR55,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR55 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR55 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xE0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TRU_SSR56,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR56 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR56 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xE4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TRU_SSR57,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR57 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR57 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xE8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
else
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TRU_SSR58,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR58 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR58 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xEC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
else
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TRU_SSR59,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR59 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR59 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xF0))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TRU_SSR60,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR60 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR60 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xF4))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TRU_SSR61,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR61 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR61 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xF8))&0x80000000)==0x80000000)
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TRU_SSR62,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR62 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR62 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0xFC))&0x80000000)==0x80000000)
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TRU_SSR63,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR63 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR63 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x100))&0x80000000)==0x80000000)
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TRU_SSR64,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR64 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR64 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x104))&0x80000000)==0x80000000)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TRU_SSR65,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR65 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR65 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x108))&0x80000000)==0x80000000)
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TRU_SSR66,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR66 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR66 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x10C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TRU_SSR67,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR67 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR67 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x110))&0x80000000)==0x80000000)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TRU_SSR68,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR68 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR68 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x114))&0x80000000)==0x80000000)
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x114))&0x80000000)==0x80000000)
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TRU_SSR69,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR69 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR69 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x118))&0x80000000)==0x80000000)
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x118))&0x80000000)==0x80000000)
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TRU_SSR70,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR70 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR70 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x11C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x11C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TRU_SSR71,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR71 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR71 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x120))&0x80000000)==0x80000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x120))&0x80000000)==0x80000000)
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TRU_SSR72,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR72 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR72 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x124))&0x80000000)==0x80000000)
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x124))&0x80000000)==0x80000000)
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TRU_SSR73,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR73 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR73 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x128))&0x80000000)==0x80000000)
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x128))&0x80000000)==0x80000000)
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TRU_SSR74,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR74 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR74 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x12C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x12C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TRU_SSR75,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR75 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR75 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x130))&0x80000000)==0x80000000)
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x130))&0x80000000)==0x80000000)
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TRU_SSR76,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR76 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR76 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x134))&0x80000000)==0x80000000)
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x134))&0x80000000)==0x80000000)
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TRU_SSR77,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR77 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR77 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x138))&0x80000000)==0x80000000)
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x138))&0x80000000)==0x80000000)
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TRU_SSR78,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR78 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR78 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x13C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x13C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
else
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TRU_SSR79,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR79 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR79 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x140))&0x80000000)==0x80000000)
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TRU_SSR80,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR80 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR80 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x144))&0x80000000)==0x80000000)
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x144))&0x80000000)==0x80000000)
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TRU_SSR81,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR81 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR81 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x148))&0x80000000)==0x80000000)
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x148))&0x80000000)==0x80000000)
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
else
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TRU_SSR82,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR82 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR82 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x14C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x14C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TRU_SSR83,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR83 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR83 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x150))&0x80000000)==0x80000000)
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x150))&0x80000000)==0x80000000)
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TRU_SSR84,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR84 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR84 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x154))&0x80000000)==0x80000000)
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x154))&0x80000000)==0x80000000)
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TRU_SSR85,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR85 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR85 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x158))&0x80000000)==0x80000000)
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x158))&0x80000000)==0x80000000)
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TRU_SSR86,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR86 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR86 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x15C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x15C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TRU_SSR87,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR87 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR87 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x160))&0x80000000)==0x80000000)
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x160))&0x80000000)==0x80000000)
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
else
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TRU_SSR88,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR88 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR88 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x164))&0x80000000)==0x80000000)
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x164))&0x80000000)==0x80000000)
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TRU_SSR89,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR89 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR89 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x168))&0x80000000)==0x80000000)
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x168))&0x80000000)==0x80000000)
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TRU_SSR90,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR90 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR90 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x16C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x16C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
else
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TRU_SSR91,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR91 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR91 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x170))&0x80000000)==0x80000000)
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
else
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x170))&0x80000000)==0x80000000)
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
else
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TRU_SSR92,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR92 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR92 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x174))&0x80000000)==0x80000000)
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x174))&0x80000000)==0x80000000)
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TRU_SSR93,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR93 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR93 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x178))&0x80000000)==0x80000000)
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
else
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x178))&0x80000000)==0x80000000)
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
else
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TRU_SSR94,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR94 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR94 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x17C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
else
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x17C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
else
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TRU_SSR95,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR95 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR95 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x180))&0x80000000)==0x80000000)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x180))&0x80000000)==0x80000000)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TRU_SSR96,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR96 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR96 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x184))&0x80000000)==0x80000000)
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
else
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x184))&0x80000000)==0x80000000)
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
else
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TRU_SSR97,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR97 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR97 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x188))&0x80000000)==0x80000000)
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x188))&0x80000000)==0x80000000)
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TRU_SSR98,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR98 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR98 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x18C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x18C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRU_SSR99,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR99 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR99 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x190))&0x80000000)==0x80000000)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x190))&0x80000000)==0x80000000)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRU_SSR100,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR100 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR100 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x194))&0x80000000)==0x80000000)
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x194))&0x80000000)==0x80000000)
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
else
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRU_SSR101,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR101 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR101 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x198))&0x80000000)==0x80000000)
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x198))&0x80000000)==0x80000000)
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TRU_SSR102,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR102 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR102 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x19C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
else
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x19C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
else
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TRU_SSR103,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR103 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR103 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TRU_SSR104,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR104 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR104 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1A4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1A4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TRU_SSR105,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR105 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR105 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
else
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1A8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
else
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TRU_SSR106,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR106 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR106 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1AC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1AC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
else
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TRU_SSR107,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR107 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR107 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
else
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1B0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
else
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TRU_SSR108,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR108 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR108 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1B4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1B4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TRU_SSR109,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR109 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR109 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
else
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1B8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
else
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TRU_SSR110,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR110 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR110 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1BC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
else
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1BC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
else
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TRU_SSR111,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR111 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR111 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1C0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TRU_SSR112,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR112 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR112 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1C4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1C4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TRU_SSR113,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR113 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR113 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
else
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1C8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
else
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TRU_SSR114,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR114 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR114 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1CC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1CC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
else
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TRU_SSR115,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR115 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR115 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
else
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1D0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
else
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TRU_SSR116,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR116 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR116 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1D4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1D4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
else
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TRU_SSR117,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR117 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR117 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
else
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1D8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
else
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TRU_SSR118,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR118 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR118 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1DC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
else
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1DC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
else
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TRU_SSR119,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR119 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR119 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1E0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TRU_SSR120,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR120 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR120 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1E4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1E4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TRU_SSR121,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR121 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR121 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
else
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1E8))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
else
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TRU_SSR122,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR122 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR122 slave select"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x1EC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
else
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x1EC))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
else
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TRU_SSR123,TRU Slave Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,SSR123 lock" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSR123 slave select"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40015000+0x7F4))&0x04)==0x04)
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x7F4))&0x04)==0x04)
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,TRU Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
else
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "TRU_MTR,TRU Master Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master trigger register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master trigger register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master trigger register 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master trigger register 0"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long 0x7E8++0x07
|
|
line.long 0x00 "TRU_ERRADDR,TRU Error Address Register"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " ADDR ,Error address"
|
|
line.long 0x04 "TRU_STAT,TRU Status Information Register"
|
|
eventfld.long 0x04 1. " ADDRERR ,Address error status" "No error,Error"
|
|
eventfld.long 0x04 0. " LWERR ,Lock write error status" "No error,Error"
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40015000))&0xFF)!=0xAD)&&(((per.l(ad:0x40027000+0x7F4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015000+0x7F4))&0x80000000)==0x80000000)
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "TRU_GCTL,TRU Global Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,GCTL lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " MTRL ,MTR lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " RESET ,Soft reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Non-MMR enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC (Static Memory Controller)"
|
|
base ad:0x4000700C
|
|
width 13.
|
|
group.long 0x0++0x0B "BANK 0"
|
|
line.long 0x00 "SMC_B0CTL,SMC Bank 0 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS0,AMS0 ORed with ARE,AMS0 ORed with AOE,AMS0 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B0TIM,SMC Bank 0 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B0ETIM,SMC Bank 0 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x10++0x0B "BANK 1"
|
|
line.long 0x00 "SMC_B1CTL,SMC Bank 1 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS1,AMS1 ORed with ARE,AMS1 ORed with AOE,AMS1 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B1TIM,SMC Bank 1 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B1ETIM,SMC Bank 1 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x20++0x0B "BANK 2"
|
|
line.long 0x00 "SMC_B2CTL,SMC Bank 2 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS2,AMS2 ORed with ARE,AMS2 ORed with AOE,AMS2 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B2TIM,SMC Bank 2 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B2ETIM,SMC Bank 2 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
group.long 0x30++0x0B "BANK 3"
|
|
line.long 0x00 "SMC_B3CTL,SMC Bank 3 Control Register"
|
|
bitfld.long 0x00 20.--21. " PGSZ ,Flash page size" "4 words,8 words,16 words,16 words"
|
|
bitfld.long 0x00 14. " RDYABTEN ,ARDY abort enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RDYPOL ,ARDY polarity" "Low active,High active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RDYEN ,ARDY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SELCTRL ,Select control" "AMS3,AMS3 ORed with ARE,AMS3 ORed with AOE,AMS3 ORed with AWE"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE ,Memory access mode" "A sync SRAM,A sync flash,A sync flash page,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Bank 3 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMC_B3TIM,SMC Bank 3 Timing Register"
|
|
bitfld.long 0x04 24.--29. " RAT ,Read access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " RHT ,Read hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " RST ,Read setup time" "8,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " WAT ,Write access time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 4.--6. " WHT ,Write hold time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " WST ,Write setup time" "8,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SMC_B3ETIM,SMC Bank 3 Extended Timing Register"
|
|
bitfld.long 0x08 16.--19. " PGWS ,Page wait states" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--14. " IT ,Idle time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " TT ,Transition time" "Off,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " PREAT ,Pre access time" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " PREST ,Pre setup time" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40001C00
|
|
width 20.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CRC0_CTL,CRC Control Register"
|
|
bitfld.long 0x00 22. " CMPMIRR ,COMPARE register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLYMIRR ,Polynomial register mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " RSLTMIRR ,Result register mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FDSEL ,FIFO data select" "Unmodified,Modified"
|
|
bitfld.long 0x00 18. " W16SWP ,Word16 swapping" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BYTMIRR ,Byte mirroring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BITMIRR ,Bit mirroring" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IRRSTALL ,Intermediate result ready stall" "Do not stall,Stall on IRR"
|
|
bitfld.long 0x00 12. " OBRSTALL ,Output buffer ready stall" "Do not stall,Stall on OBR"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTOCLRF ,Auto clear to one" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 8. " AUTOCLRZ ,Auto clear to zero" "Not Cleared,Cleared"
|
|
bitfld.long 0x00 4.--7. " OPMODE ,Operation mode" ",CRC compute/compare memory transfer,Data fill memory transfer,CRC compute/compare memory scan,Data verify memory scan,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " BLKEN ,Block enable" "Disabled,Enabled"
|
|
line.long 0x04 "CRC0_DCNT,CRC Data Word Count Register"
|
|
line.long 0x08 "CRC0_DCNTRLD,CRC Data Word Count Reload Register"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CRC0_COMP,CRC Data Compare Register"
|
|
line.long 0x04 "CRC0_FILLVAL,CRC Fill Value Register"
|
|
sif (cpuis("ADSPCM40*"))
|
|
if ((((per.l(ad:0x40001C00+0x00))&0xF0)==0x10)||(((per.l(ad:0x40001C00+0x00))&0xF0)==0x20))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRC0_DFIFO,CRC Data FIFO Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC0_INEN,CRC Interrupt Enable Register"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DCNTEXP_set/clr ,Data count expired (status) interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CMPERR_set/clr ,Compare error interrupt enable" "Masked,Unmasked"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRC0_POLY,CRC Polynomial Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRC0_STAT,CRC Status Register"
|
|
rbitfld.long 0x00 20.--22. " FSTAT ,FIFO status" "Empty,1 data,2 data,3 data,Full,?..."
|
|
rbitfld.long 0x00 19. " LUTDONE ,Look up table done" "No status,LUT Generation done"
|
|
rbitfld.long 0x00 18. " IRR ,Intermediate result ready" "No status,Intermediate results ready"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " OBR ,Output buffer ready" "No status,Output buffer ready"
|
|
rbitfld.long 0x00 16. " IBR ,Input buffer ready" "No status,Input buffer ready"
|
|
eventfld.long 0x00 4. " DCNTEXP ,Data count expired" "No status,Data counter expired"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CMPERR ,Compare error" "No status,Compare error"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRC0_DCNTCAP,CRC Data Count Capture Register"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "CRC0_RESULT_FIN,CRC CRC Final Result Register"
|
|
line.long 0x04 "CRC0_RESULT_CUR,CRC CRC Current Result Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
tree "DMA0"
|
|
base ad:0x40011000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA0_CFG,DMA0 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA0_ADDRSTART,DMA0 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA0_CFG,DMA0 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA0_DSCPTR_PRV,DMA0 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA0_ADDR_CUR,DMA0 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA0_ADDR_CUR,DMA0 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA0_STAT,DMA0 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA0_XCNT_CUR,DMA0 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA0_YCNT_CUR,DMA0 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA0_XCNT_CUR,DMA0 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA0_YCNT_CUR,DMA0 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA0_BWLCNT,DMA0 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA0_BWLCNT_CUR,DMA0 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA0_BWMCNT,DMA0 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_BWMCNT_CUR,DMA0 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x40011080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA1_CFG,DMA1 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA1_ADDRSTART,DMA1 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA1_CFG,DMA1 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA1_DSCPTR_PRV,DMA1 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA1_ADDR_CUR,DMA1 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA1_ADDR_CUR,DMA1 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA1_STAT,DMA1 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA1_XCNT_CUR,DMA1 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA1_YCNT_CUR,DMA1 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA1_XCNT_CUR,DMA1 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA1_YCNT_CUR,DMA1 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA1_BWLCNT,DMA1 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA1_BWLCNT_CUR,DMA1 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA1_BWMCNT,DMA1 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA1_BWMCNT_CUR,DMA1 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x40011100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA2_CFG,DMA2 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA2_ADDRSTART,DMA2 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA2_CFG,DMA2 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA2_DSCPTR_PRV,DMA2 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA2_ADDR_CUR,DMA2 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA2_ADDR_CUR,DMA2 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA2_STAT,DMA2 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA2_XCNT_CUR,DMA2 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA2_YCNT_CUR,DMA2 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA2_XCNT_CUR,DMA2 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA2_YCNT_CUR,DMA2 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA2_BWLCNT,DMA2 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA2_BWLCNT_CUR,DMA2 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA2_BWMCNT,DMA2 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA2_BWMCNT_CUR,DMA2 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA3"
|
|
base ad:0x40011180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA3_CFG,DMA3 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA3_ADDRSTART,DMA3 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA3_CFG,DMA3 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA3_DSCPTR_PRV,DMA3 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA3_ADDR_CUR,DMA3 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA3_ADDR_CUR,DMA3 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA3_STAT,DMA3 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA3_XCNT_CUR,DMA3 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA3_YCNT_CUR,DMA3 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA3_XCNT_CUR,DMA3 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA3_YCNT_CUR,DMA3 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA3_BWLCNT,DMA3 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA3_BWLCNT_CUR,DMA3 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA3_BWMCNT,DMA3 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA3_BWMCNT_CUR,DMA3 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA4"
|
|
base ad:0x40011200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA4_CFG,DMA4 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA4_ADDRSTART,DMA4 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA4_CFG,DMA4 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA4_DSCPTR_PRV,DMA4 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA4_ADDR_CUR,DMA4 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA4_ADDR_CUR,DMA4 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA4_STAT,DMA4 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA4_XCNT_CUR,DMA4 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA4_YCNT_CUR,DMA4 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA4_XCNT_CUR,DMA4 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA4_YCNT_CUR,DMA4 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA4_BWLCNT,DMA4 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA4_BWLCNT_CUR,DMA4 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA4_BWMCNT,DMA4 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA4_BWMCNT_CUR,DMA4 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA5"
|
|
base ad:0x40011280
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40011280+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40011280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011280+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40011280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40011280+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011280+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA5_CFG,DMA5 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA5_ADDRSTART,DMA5 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA5_CFG,DMA5 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA5_DSCPTR_PRV,DMA5 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40011280+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA5_ADDR_CUR,DMA5 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA5_ADDR_CUR,DMA5 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA5_STAT,DMA5 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40011280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA5_XCNT_CUR,DMA5 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA5_YCNT_CUR,DMA5 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA5_XCNT_CUR,DMA5 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA5_YCNT_CUR,DMA5 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA5_BWLCNT,DMA5 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA5_BWLCNT_CUR,DMA5 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA5_BWMCNT,DMA5 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA5_BWMCNT_CUR,DMA5 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA6"
|
|
base ad:0x40013000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40013000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40013000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40013000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40013000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA6_CFG,DMA6 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA6_ADDRSTART,DMA6 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA6_CFG,DMA6 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA6_DSCPTR_PRV,DMA6 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40013000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA6_ADDR_CUR,DMA6 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA6_ADDR_CUR,DMA6 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA6_STAT,DMA6 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40013000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA6_XCNT_CUR,DMA6 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA6_YCNT_CUR,DMA6 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA6_XCNT_CUR,DMA6 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA6_YCNT_CUR,DMA6 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA6_BWLCNT,DMA6 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA6_BWLCNT_CUR,DMA6 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA6_BWMCNT,DMA6 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA6_BWMCNT_CUR,DMA6 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA7"
|
|
base ad:0x40013080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40013080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40013080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40013080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40013080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA7_CFG,DMA7 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA7_ADDRSTART,DMA7 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA7_CFG,DMA7 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA7_DSCPTR_PRV,DMA7 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40013080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA7_ADDR_CUR,DMA7 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA7_ADDR_CUR,DMA7 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA7_STAT,DMA7 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40013080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA7_XCNT_CUR,DMA7 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA7_YCNT_CUR,DMA7 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA7_XCNT_CUR,DMA7 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA7_YCNT_CUR,DMA7 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA7_BWLCNT,DMA7 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA7_BWLCNT_CUR,DMA7 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA7_BWMCNT,DMA7 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA7_BWMCNT_CUR,DMA7 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA8"
|
|
base ad:0x40013100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40013100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40013100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40013100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40013100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA8_CFG,DMA8 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA8_ADDRSTART,DMA8 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA8_CFG,DMA8 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA8_DSCPTR_PRV,DMA8 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40013100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA8_ADDR_CUR,DMA8 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA8_ADDR_CUR,DMA8 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA8_STAT,DMA8 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40013100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA8_XCNT_CUR,DMA8 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA8_YCNT_CUR,DMA8 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA8_XCNT_CUR,DMA8 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA8_YCNT_CUR,DMA8 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA8_BWLCNT,DMA8 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA8_BWLCNT_CUR,DMA8 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA8_BWMCNT,DMA8 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA8_BWMCNT_CUR,DMA8 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA8_BWLCNT,DMA8 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA8_BWLCNT_CUR,DMA8 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA8_BWMCNT,DMA8 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA8_BWMCNT_CUR,DMA8 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA9"
|
|
base ad:0x40013180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40013180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40013180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40013180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40013180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40013180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA9_CFG,DMA9 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA9_ADDRSTART,DMA9 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA9_CFG,DMA9 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA9_DSCPTR_PRV,DMA9 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40013180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA9_ADDR_CUR,DMA9 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA9_ADDR_CUR,DMA9 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA9_STAT,DMA9 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40013180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA9_XCNT_CUR,DMA9 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA9_YCNT_CUR,DMA9 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA9_XCNT_CUR,DMA9 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA9_YCNT_CUR,DMA9 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA9_BWLCNT,DMA9 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA9_BWLCNT_CUR,DMA9 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA9_BWMCNT,DMA9 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA9_BWMCNT_CUR,DMA9 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA9_BWLCNT,DMA9 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA9_BWLCNT_CUR,DMA9 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA9_BWMCNT,DMA9 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA9_BWMCNT_CUR,DMA9 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA10"
|
|
base ad:0x40010000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA10_ADDRSTART,DMA10 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA10_CFG,DMA10 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA10_ADDRSTART,DMA10 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA10_CFG,DMA10 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA10_ADDRSTART,DMA10 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA10_CFG,DMA10 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA10_CFG,DMA10 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA10_ADDRSTART,DMA10 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA10_CFG,DMA10 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA10_ADDRSTART,DMA10 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA10_CFG,DMA10 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA10_DSCPTR_PRV,DMA10 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA10_ADDR_CUR,DMA10 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA10_ADDR_CUR,DMA10 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA10_STAT,DMA10 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA10_XCNT_CUR,DMA10 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA10_YCNT_CUR,DMA10 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA10_XCNT_CUR,DMA10 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA10_YCNT_CUR,DMA10 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA10_BWLCNT,DMA10 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA10_BWLCNT_CUR,DMA10 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA10_BWMCNT,DMA10 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA10_BWMCNT_CUR,DMA10 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA11"
|
|
base ad:0x40010080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA11_ADDRSTART,DMA11 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA11_CFG,DMA11 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA11_ADDRSTART,DMA11 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA11_CFG,DMA11 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA11_ADDRSTART,DMA11 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA11_CFG,DMA11 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA11_CFG,DMA11 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA11_ADDRSTART,DMA11 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA11_CFG,DMA11 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA11_ADDRSTART,DMA11 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA11_CFG,DMA11 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA11_DSCPTR_PRV,DMA11 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA11_ADDR_CUR,DMA11 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA11_ADDR_CUR,DMA11 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA11_STAT,DMA11 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA11_XCNT_CUR,DMA11 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA11_YCNT_CUR,DMA11 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA11_XCNT_CUR,DMA11 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA11_YCNT_CUR,DMA11 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA11_BWLCNT,DMA11 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA11_BWLCNT_CUR,DMA11 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA11_BWMCNT,DMA11 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA11_BWMCNT_CUR,DMA11 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA12"
|
|
base ad:0x40010100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA12_ADDRSTART,DMA12 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA12_CFG,DMA12 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA12_ADDRSTART,DMA12 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA12_CFG,DMA12 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA12_ADDRSTART,DMA12 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA12_CFG,DMA12 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA12_CFG,DMA12 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA12_ADDRSTART,DMA12 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA12_CFG,DMA12 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA12_ADDRSTART,DMA12 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA12_CFG,DMA12 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA12_DSCPTR_PRV,DMA12 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA12_ADDR_CUR,DMA12 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA12_ADDR_CUR,DMA12 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA12_STAT,DMA12 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA12_XCNT_CUR,DMA12 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA12_YCNT_CUR,DMA12 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA12_XCNT_CUR,DMA12 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA12_YCNT_CUR,DMA12 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA12_BWLCNT,DMA12 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA12_BWLCNT_CUR,DMA12 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA12_BWMCNT,DMA12 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA12_BWMCNT_CUR,DMA12 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA13"
|
|
base ad:0x40010180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA13_ADDRSTART,DMA13 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA13_CFG,DMA13 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA13_ADDRSTART,DMA13 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA13_CFG,DMA13 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA13_ADDRSTART,DMA13 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA13_CFG,DMA13 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA13_CFG,DMA13 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA13_ADDRSTART,DMA13 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA13_CFG,DMA13 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA13_ADDRSTART,DMA13 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA13_CFG,DMA13 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA13_DSCPTR_PRV,DMA13 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA13_ADDR_CUR,DMA13 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA13_ADDR_CUR,DMA13 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA13_STAT,DMA13 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA13_XCNT_CUR,DMA13 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA13_YCNT_CUR,DMA13 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA13_XCNT_CUR,DMA13 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA13_YCNT_CUR,DMA13 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA13_BWLCNT,DMA13 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA13_BWLCNT_CUR,DMA13 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA13_BWMCNT,DMA13 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA13_BWMCNT_CUR,DMA13 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA14"
|
|
base ad:0x40010200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA14_ADDRSTART,DMA14 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA14_CFG,DMA14 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA14_ADDRSTART,DMA14 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA14_CFG,DMA14 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA14_ADDRSTART,DMA14 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA14_CFG,DMA14 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA14_CFG,DMA14 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA14_ADDRSTART,DMA14 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA14_CFG,DMA14 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA14_ADDRSTART,DMA14 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA14_CFG,DMA14 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA14_DSCPTR_PRV,DMA14 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA14_ADDR_CUR,DMA14 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA14_ADDR_CUR,DMA14 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA14_STAT,DMA14 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA14_XCNT_CUR,DMA14 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA14_YCNT_CUR,DMA14 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA14_XCNT_CUR,DMA14 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA14_YCNT_CUR,DMA14 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA14_BWLCNT,DMA14 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA14_BWLCNT_CUR,DMA14 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA14_BWMCNT,DMA14 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA14_BWMCNT_CUR,DMA14 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA15"
|
|
base ad:0x40010280
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40010280+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40010280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010280+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA15_ADDRSTART,DMA15 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA15_CFG,DMA15 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA15_ADDRSTART,DMA15 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA15_CFG,DMA15 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA15_ADDRSTART,DMA15 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40010280+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40010280+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA15_CFG,DMA15 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA15_CFG,DMA15 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010280+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA15_ADDRSTART,DMA15 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA15_CFG,DMA15 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA15_ADDRSTART,DMA15 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA15_CFG,DMA15 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA15_DSCPTR_PRV,DMA15 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40010280+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA15_ADDR_CUR,DMA15 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA15_ADDR_CUR,DMA15 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA15_STAT,DMA15 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40010280+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA15_XCNT_CUR,DMA15 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA15_YCNT_CUR,DMA15 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA15_XCNT_CUR,DMA15 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA15_YCNT_CUR,DMA15 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA15_BWLCNT,DMA15 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA15_BWLCNT_CUR,DMA15 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA15_BWMCNT,DMA15 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA15_BWMCNT_CUR,DMA15 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA16"
|
|
base ad:0x40012000
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40012000+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40012000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012000+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA16_ADDRSTART,DMA16 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA16_CFG,DMA16 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA16_ADDRSTART,DMA16 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA16_CFG,DMA16 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA16_ADDRSTART,DMA16 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40012000+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012000+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA16_CFG,DMA16 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA16_CFG,DMA16 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012000+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA16_ADDRSTART,DMA16 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA16_CFG,DMA16 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA16_ADDRSTART,DMA16 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA16_CFG,DMA16 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA16_DSCPTR_PRV,DMA16 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40012000+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA16_ADDR_CUR,DMA16 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA16_ADDR_CUR,DMA16 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA16_STAT,DMA16 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40012000+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA16_XCNT_CUR,DMA16 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA16_YCNT_CUR,DMA16 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA16_XCNT_CUR,DMA16 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA16_YCNT_CUR,DMA16 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA16_BWLCNT,DMA16 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA16_BWLCNT_CUR,DMA16 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA16_BWMCNT,DMA16 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA16_BWMCNT_CUR,DMA16 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA17"
|
|
base ad:0x40012080
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40012080+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40012080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012080+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA17_ADDRSTART,DMA17 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA17_CFG,DMA17 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA17_ADDRSTART,DMA17 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA17_CFG,DMA17 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA17_ADDRSTART,DMA17 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40012080+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012080+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA17_CFG,DMA17 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA17_CFG,DMA17 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012080+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA17_ADDRSTART,DMA17 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA17_CFG,DMA17 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA17_ADDRSTART,DMA17 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA17_CFG,DMA17 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA17_DSCPTR_PRV,DMA17 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40012080+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA17_ADDR_CUR,DMA17 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA17_ADDR_CUR,DMA17 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA17_STAT,DMA17 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40012080+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA17_XCNT_CUR,DMA17 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA17_YCNT_CUR,DMA17 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA17_XCNT_CUR,DMA17 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA17_YCNT_CUR,DMA17 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA17_BWLCNT,DMA17 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA17_BWLCNT_CUR,DMA17 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA17_BWMCNT,DMA17 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA17_BWMCNT_CUR,DMA17 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA18"
|
|
base ad:0x40012100
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40012100+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40012100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012100+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40012100+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012100+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012100+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA18_CFG,DMA18 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA18_ADDRSTART,DMA18 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA18_CFG,DMA18 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA18_DSCPTR_PRV,DMA18 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40012100+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA18_ADDR_CUR,DMA18 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA18_ADDR_CUR,DMA18 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA18_STAT,DMA18 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40012100+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA18_XCNT_CUR,DMA18 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA18_YCNT_CUR,DMA18 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA18_XCNT_CUR,DMA18 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA18_YCNT_CUR,DMA18 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA18_BWLCNT,DMA18 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA18_BWLCNT_CUR,DMA18 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA18_BWMCNT,DMA18 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA18_BWMCNT_CUR,DMA18 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA18_BWLCNT,DMA18 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA18_BWLCNT_CUR,DMA18 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA18_BWMCNT,DMA18 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA18_BWMCNT_CUR,DMA18 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA19"
|
|
base ad:0x40012180
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40012180+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40012180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012180+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40012180+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012180+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012180+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA19_CFG,DMA19 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA19_ADDRSTART,DMA19 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA19_CFG,DMA19 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA19_DSCPTR_PRV,DMA19 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40012180+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA19_ADDR_CUR,DMA19 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA19_ADDR_CUR,DMA19 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA19_STAT,DMA19 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40012180+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA19_XCNT_CUR,DMA19 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA19_YCNT_CUR,DMA19 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA19_XCNT_CUR,DMA19 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA19_YCNT_CUR,DMA19 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA19_BWLCNT,DMA19 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA19_BWLCNT_CUR,DMA19 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA19_BWMCNT,DMA19 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA19_BWMCNT_CUR,DMA19 Bandwidth Monitor Count Current Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA19_BWLCNT,DMA19 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA19_BWLCNT_CUR,DMA19 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA19_BWMCNT,DMA19 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA19_BWMCNT_CUR,DMA19 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA20"
|
|
base ad:0x40012200
|
|
width 20.
|
|
sif (cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40012200+0x08))&0x01)==0x00)
|
|
if ((((per.l(ad:0x40012200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012200+0x08))&0x2)==0x0))
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
if ((((per.l(ad:0x40012200+0x08))&0x7000)==0x0)&&(((per.l(ad:0x40012200+0x08))&0x2)==0x0))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" "1,2,3,8,16,32,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" "1,2,4,8,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012200+0x08))&0x01)==0x00)
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
line.long 0x08 "DMA20_CFG,DMA20 Configuration Register"
|
|
bitfld.long 0x08 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
bitfld.long 0x08 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
bitfld.long 0x08 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
bitfld.long 0x08 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x08 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x08 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
bitfld.long 0x08 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
bitfld.long 0x08 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x08 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
line.long 0x0C "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x10 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer To Next Initial Descriptor Register"
|
|
line.long 0x04 "DMA20_ADDRSTART,DMA20 Start Address Of Current Buffer Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMA20_CFG,DMA20 Configuration Register"
|
|
rbitfld.long 0x00 28. " PDRF ,Peripheral data request forward" "Not forwarded,Forwarded"
|
|
rbitfld.long 0x00 26. " TWOD ,Two dimension addressing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID copy control" "Never copy,Copy"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " TOVEN ,Trigger overrun error enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. " TRIG ,Generate outgoing trigger" "Never asserted,XCNTCUR reached 0,YCNTCUR reached 0,?..."
|
|
rbitfld.long 0x00 20.--21. " INT ,Generate interrupt" "Never asserted,X count expired,Y count expired,Peripheral"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--18. " NDSIZE ,Next descriptor set size" "1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 15. " TWAIT ,Wait for trigger" "Not wait,Wait"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--14. " FLOW ,Next operation" "Stop,Auto buffer,,,Descriptor list,Descriptor array,Descriptor On-Demand list,Descriptor on demand array"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--10. " MSIZE ,Memory transfer word size" ",,4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
rbitfld.long 0x00 4.--6. " PSIZE ,Peripheral transfer word size" ",,4 bytes,8 bytes,?..."
|
|
rbitfld.long 0x00 3. " CADDR ,Use current address" "Load starting address,Use current address"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SYNC ,Synchronize work unit transitions" "No synchronization,Synchronization"
|
|
rbitfld.long 0x00 1. " WNR ,Write/read channel direction" "Transmit,Receive"
|
|
bitfld.long 0x00 0. " EN ,DMA channel enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register"
|
|
line.long 0x04 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
line.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
else
|
|
hgroup.long 0x14++0x07
|
|
hide.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D Only) Register"
|
|
hide.long 0x04 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D Only) Register"
|
|
endif
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register"
|
|
endif
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DMA20_DSCPTR_PRV,DMA20 Previous Initial Descriptor Pointer Register"
|
|
hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor pointer for previous element"
|
|
bitfld.long 0x00 0. " PDPO ,Previous descriptor pointer overrun" "No error,Error"
|
|
if (((per.l(ad:0x40012200+0x08))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMA20_ADDR_CUR,DMA20 Current Address Register"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DMA20_ADDR_CUR,DMA20 Current Address Register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA20_STAT,DMA20 Status Register"
|
|
rbitfld.long 0x00 20. " TWAIT ,Trigger wait status" "No trigger,Trigger"
|
|
rbitfld.long 0x00 16.--18. " FIFOFILL ,FIFO fill status" "Empty,1/4,1/2,3/4,Full,,,Full"
|
|
rbitfld.long 0x00 14.--15. " MBWID ,Memory bus width" "2 bytes,4 bytes,8 bytes,16 bytes"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " PBWID ,Peripheral bus width" "1 byte,2 bytes,4 bytes,8 bytes"
|
|
rbitfld.long 0x00 8.--10. " RUN ,Run status" "Idle,Descriptor fetch,Data transfer,Waiting for trigger,Waiting for write ACK/FIFO,?..."
|
|
rbitfld.long 0x00 4.--6. " ERRC ,Error cause" "Configuration,Illegal write occurred while channel running,Address alignment,Memory access or fabric,,Trigger overrun,Bandwidth monitor,?..."
|
|
textline " "
|
|
eventfld.long 0x00 2. " PIRQ ,Peripheral interrupt request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " IRQERR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQDONE ,Work unit/row done interrupt" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0x40012200+0x08))&0x4000000)==0x4000000)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "DMA20_XCNT_CUR,DMA20 Intra-row XCNT (2D) Register"
|
|
line.long 0x04 "DMA20_YCNT_CUR,DMA20 Current Row Count (2D Only) Register"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA20_XCNT_CUR,DMA20 Current Count(1d) Register"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "DMA20_YCNT_CUR,DMA20 Current Row Count (2D Only) Register"
|
|
endif
|
|
sif (cpuis("ADSP-SC57?"))
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA20_BWLCNT,DMA20 Bandwidth Limit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DMA20_BWLCNT_CUR,DMA20 Bandwidth Limit Count Current Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth limit count current"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA20_BWMCNT,DMA20 Bandwidth Monitor Count Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DMA20_BWMCNT_CUR,DMA20 Bandwidth Monitor Count Current Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "PORT (General-Purpose Ports)"
|
|
tree "PORT A"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTA_FER_SET/CLR,Port A Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTA_DATA_SET/CLR,Port A GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTA_DIR_SET/CLR,Port A GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTA_INEN_SET/CLR,Port A GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTA_MUX,Port A Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port A bit 15" "PWM1_BL,TM0_TMR3,SMC0_D07,?..."
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port A bit 14" "PWM1_BH,TM0_TMR6,SMC0_D06,?..."
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port A bit 13" "PWM1_AL,TM0_TMR5,SMC0_D05,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port A bit 12" "PWM1_AH,TM0_TMR4,SMC0_D04,?..."
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port A bit 11" "PWM1_TRIP0,UART1_CTS,SMC0_D03,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port A bit 10" "PWM1_SYNC,,SMC0_D02,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port A bit 9" "PWM1_CL,,SMC0_D01,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port A bit 8" "PWM1_CH,,SMC0_D00,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port A bit 7" "PWM0_CL,SMC0_AMS2,SPT1_BD1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port A bit 6" "PWM0_CH,,SPT_BD0,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port A bit 5" "PWM0_BL,,SPT1_BFS,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port A bit 4" "PWM0_BH,,SPT1_BCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port A bit 3" "PWM0_AL,,SPT1_AD1,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port A bit 2" "PWM_AH,,SPT1_AD0,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port A bit 1" "PWM0_TRIP0,,SPT1_AFS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port A bit 0" "PWM0_SYNC,,SPT1_ACLK,?..."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTA_DATA_TGL,Port A GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 15. " PX15 ,Port A bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port A bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port A bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port A bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port A bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port A bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port A bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port A bit 8 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PX7 ,Port A bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port A bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port A bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port A bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port A bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port A bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port A bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port A bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " PX15 ,Port A bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port A bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port A bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port A bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port A bit 11 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PX10 ,Port A bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port A bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port A bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port A bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port A bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port A bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port A bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port A bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port A bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port A bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port A bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTA_POL_SET/CLR,Port A GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port A bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port A bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port A bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port A bit 12 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port A bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port A bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port A bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port A bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port A bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port A bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port A bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port A bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port A bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port A bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port A bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port A bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTA_LOCK,Port A GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT B"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTB_FER_SET/CLR,Port B Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTB_DATA_SET/CLR,Port B GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTB_DIR_SET/CLR,Port B GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTB_INEN_SET/CLR,Port B GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTB_MUX,Port B Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port B bit 15" "CAN0_RX,SPT1_ATDV,UART1_RX,SMC0_A03"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port B bit 14" "SINC0_D3,CNT0_OUTB,SPI0_SEL3,SMC0_A02"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port B bit 13" "SINC0_D2,CNT0_OUTA,SPI0_SEL2,SMC0_A01"
|
|
textline " "
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port B bit 12" "SINC0_D1,,UART2_RX,SMC0_AOE"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port B bit 11" "SINC0_D0,SPI0_D3,CAN1_TX,SMC0_AMS0"
|
|
else
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port B bit 12" "SINC0_D1,SPT0_BTDV,UART2_RX,SMC0_AOE"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port B bit 11" "SINC0_D0,SPI0_D3,CAN1_TX,SMC0_AMS0"
|
|
endif
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port B bit 10" "SINC0_CLK0,SPI0_D2,CAN1_RX,SMC0_AWE"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port B bit 9" "PWM2_BL,TM0_TMR2,UART1_TX,SMC0_ARE"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port B bit 8" "PWM2_BH,TM0_TMR1,UART1_RX,SMC0_ARDY"
|
|
sif (cpuis("ADSPCM407F")||cpuis("ADSPCM408F")||cpuis("ADSPCM409F"))
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port B bit 7" "PWM2_AL,TMO_TMR0,SPI1_SEL3,SMC0_D15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port B bit 6" "PWM2_AH,TMO0_CLK,SPI1_SEL2,SMC0_D14"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port B bit 7" "PWM2_AL,TMO_TMR0,,SMC0_D15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port B bit 6" "PWM2_AH,TMO0_CLK,,SMC0_D14"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port B bit 5" "PWM_TRIP0,UART0_CTS,TMO0_TMR7,SMC0_D13"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port B bit 4" "PWM2_SYNC,UART0_RTS,SPT0_ATDV,SMC0_D12"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port B bit 3" "PWM1_DL,TRACE_D02,SPT0_AD1,SMC0_D11"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port B bit 2" "PWM1_DH,TRACED_01,SPT0_AD0,SMC0_D10"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port B bit 1" "PWM0_DL,TRACE_D00,SPT0_AFS,SMC0_D09"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port B bit 0" "PWM0_DH,TRACE_CLK,SPT0_ACLK,SMC0_D08"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTB_DATA_TGL,Port B GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 15. " PX15 ,Port B bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port B bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port B bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port B bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port B bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port B bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port B bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port B bit 8 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PX7 ,Port B bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port B bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port B bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port B bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port B bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port B bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port B bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port B bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " PX15 ,Port B bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port B bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port B bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port B bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port B bit 11 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PX10 ,Port B bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port B bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port B bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port B bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port B bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port B bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port B bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port B bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port B bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port B bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port B bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTB_POL_SET/CLR,Port B GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port B bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port B bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port B bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port B bit 12 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port B bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port B bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port B bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port B bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port B bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port B bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port B bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port B bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port B bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port B bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port B bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port B bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTB_LOCK,Port B GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT C"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTC_FER_SET/CLR,Port C Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTC_DATA_SET/CLR,Port C GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTC_DIR_SET/CLR,Port C GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTC_INEN_SET/CLR,Port C GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTC_MUX,Port C Multiplexer Control Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port C bit 7" "SINC0_CLK1,UART2_TX,UART1_RTS,?..."
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port C bit 6" "SPI0_SEL1,PWM2_DL,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port C bit 5" "SPI0_MOSI,PWM2_DH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port C bit 4" "SPI0_MISO,PWM2_CL,?..."
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port C bit 3" "SPI0_CLK,PWM2_CH,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port C bit 2" "UART0_TX,TRACE_D03,SPI0_RDY,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port C bit 1" "UART0_RX,,,SMC0_A05"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port C bit 0" "CAN0_TX,SPT1_BTDV,UART1_TX,SMC0_A04"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port C bit 15" ",SPI1_SEL1,SMC0_D07,?..."
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port C bit 14" ",SPI1_MOSI,SMC0_D06,?..."
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port C bit 13" ",SPI_MISO,SMC0_D05,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port C bit 12" ",SPI1_CLK,SMC0_D04,?..."
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port C bit 11" "SMC0_AMS3,SPT0_BD1,SMC0_D03,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port C bit 10" ",SPT0_BD0,SMC0_D02,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port C bit 9" ",SPT0_BFS,SMC0_D01,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port C bit 8" ",SPT0_BCLK,SMC0_D00,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port C bit 7" "SINC0_CLK1,UART2_TX,UART1_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port C bit 6" "SPI0_SEL1,PWM2_DL,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port C bit 5" "SPI0_MOSI,PWM2_DH,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port C bit 4" "SPI0_MISO,PWM2_CL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port C bit 3" "SPI0_CLK,PWM2_CH,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port C bit 2" "UART0_TX,TRACE_D03,SPI0_RDY,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port C bit 1" "UART0_RX,,,SMC0_A05"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port C bit 0" "CAN0_TX,SPT1_BTDV,UART1_TX,SMC0_A04"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTC_DATA_TGL,Port C GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 7. " PX7 ,Port C bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port C bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port C bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port C bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port C bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port C bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port C bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port C bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " PX15 ,Port C bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port C bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port C bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port C bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port C bit 11 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PX10 ,Port C bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port C bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port C bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port C bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port C bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port C bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port C bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port C bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port C bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port C bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port C bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTC_POL_SET/CLR,Port C GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port C bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port C bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port C bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port C bit 12 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port C bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port C bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port C bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port C bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port C bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port C bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port C bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port C bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port C bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port C bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port C bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port C bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTC_LOCK,Port C GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("ADSPCM407F")||cpuis("ADSPCM408F")||cpuis("ADSPCM409F"))
|
|
tree "PORT D"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTD_FER_SET/CLR,Port D Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTD_DATA_SET/CLR,Port D GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTD_DIR_SET/CLR,Port D GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTD_INEN_SET/CLR,Port D GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTD_MUX,Port D Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port D bit 15" ",,SMC0_A13,?..."
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port D bit 14" ",,SMC0_A12,?..."
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port D bit 13" ",,SMC0_A11,TM0_ACI1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port D bit 12" ",,SMC0_A10,TM0_ACI2"
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port D bit 11" ",,SMC0_A09,TM0_ACI3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port D bit 10" ",,SMC0_A08,TM0_ACI4"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port D bit 9" ",,SMC0_A07,TM0_ACI5"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port D bit 8" ",,SMC0_A06,TM0_CLK"
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port D bit 7" ",,SMC0_D15,TM0_TMR7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port D bit 6" ",,SMC0_D14,TM0_TMR6"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port D bit 5" ",,SMC0_D13,TM0_TMR5"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port D bit 4" ",,SMC0_D12,TM0_TMR4"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port D bit 3" ",,SMC0_D11,TM0_TMR3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port D bit 2" ",,SMC0_D10,TM0_TMR2"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port D bit 1" ",,SMC0_D09,TM0_TMR1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port D bit 0" ",,SMC0_D08,TM0_TMR0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTD_DATA_TGL,Port D GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 15. " PX15 ,Port D bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port D bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port D bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port D bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port D bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port D bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port D bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port D bit 8 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PX7 ,Port D bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port D bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port D bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port D bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port D bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port D bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port D bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port D bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " PX15 ,Port D bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port D bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port D bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port D bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port D bit 11 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PX10 ,Port D bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port D bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port D bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port D bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port D bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port D bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port D bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port D bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port D bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port D bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port D bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTD_POL_SET/CLR,Port D GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port D bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port D bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port D bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port D bit 12 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port D bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port D bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port D bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port D bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port D bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port D bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port D bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port D bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port D bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port D bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port D bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port D bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTD_LOCK,Port D GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT E"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTE_FER_SET/CLR,Port E Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTE_DATA_SET/CLR,Port E GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTE_DIR_SET/CLR,Port E GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTE_INEN_SET/CLR,Port E GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTE_MUX,Port E Multiplexer Control Register"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux for port E bit 15" "ETH0_REFCLK,CNT1_OUTB,?..."
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux for port E bit 14" "ETH0_TXEN,CNT1_OUTA,?..."
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux for port E bit 13" "ETH0_TXD1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux for port E bit 12" "ETH0_TXD0,?..."
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux for port E bit 11" "ETH0_MDC,,SMC0_A24,?..."
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port E bit 10" ",ETH0_MDIO,SMC0_AMS1,?.."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port E bit 9" ",ETH0_CRS,SMC0_A23,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port E bit 8" ",ETH0_PTPPPS,SMC0_A22,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port E bit 7" ",ETH0_PTPAUXIN,SMC0_A21,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port E bit 6" ",ETH0_PTPCLKIN,SMC0_A20,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port E bit 5" ",,SMC0_A19,?..."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port E Bit 4" ",,SMC0_A18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port E bit 3" ",,SMC0_A17,SPT0_AD1"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port E bit 2" ",,SMC0_A16,SPT0_AD0"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port E bit 1" ",,SMC0_A15,SPT0_AFS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port E bit 0" ",,SMC0_A14,SPT0_ACLK"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTE_DATA_TGL,Port E GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 15. " PX15 ,Port E bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port E bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port E bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port E bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port E bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port E bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port E bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port E bit 8 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PX7 ,Port E bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port E bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port E bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port E bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port E bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port E bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port E bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port E bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 15. " PX15 ,Port E bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port E bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port E bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port E bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port E bit 11 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PX10 ,Port E bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port E bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port E bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port E bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port E bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port E bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port E bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port E bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port E bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port E bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port E bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTE_POL_SET/CLR,Port E GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port E bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port E bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port E bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port E bit 12 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port E bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port E bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port E bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port E bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port E bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port E bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port E bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port E bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port E bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port E bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port E bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port E bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTE_LOCK,Port E GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PORT F"
|
|
base ad:0x40005000
|
|
width 23.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORTF_FER_SET/CLR,Port F Function Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port F bit 15 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port F bit 14 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port F bit 13 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port F bit 12 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 mode" "Peripheral,GPIO"
|
|
else
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 mode" "Peripheral,GPIO"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 mode" "Peripheral,GPIO"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 mode" "Peripheral,GPIO"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PORTF_DATA_SET/CLR,Port F GPIO Data Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port F bit 15 data" "Set,Clear"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port F bit 14 data" "Set,Clear"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port F bit 13 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port F bit 12 data" "Set,Clear"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 data" "Set,Clear"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 data" "Set,Clear"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 data" "Set,Clear"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 data" "Set,Clear"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 data" "Set,Clear"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 data" "Set,Clear"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 data" "Set,Clear"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 data" "Set,Clear"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 data" "Set,Clear"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PORTF_DIR_SET/CLR,Port F GPIO Direction Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port F bit 15 direction" "Input,Output"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port F bit 14 direction" "Input,Output"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port F bit 13 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port F bit 12 direction" "Input,Output"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 direction" "Input,Output"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 direction" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 direction" "Input,Output"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 direction" "Input,Output"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 direction" "Input,Output"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 direction" "Input,Output"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 direction" "Input,Output"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 direction" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 direction" "Input,Output"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORTF_INEN_SET/CLR,Port F GPIO Input Enable Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port F bit 15 input enable" "Disable,Enable"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port F bit 14 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port F bit 13 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port F bit 12 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 input enable" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 input enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORTF_MUX,Port F Multiplexer Control Register"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux for port F bit 10" ",,SMC0_ABE0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux for port F bit 9" ",,SMC0_A05,?..."
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux for port F bit 8" ",,SMC0_A04,?..."
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux for port F bit 7" ",,SMC0_A03,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux for port F bit 6" ",,SMC0_A02,?..."
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux for port F bit 5" ",,SMC0_A01,?.."
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux for port F bit 4" ",,SMC0_ARDY,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux for port F bit 3" ",,SMC0_AOE,?..."
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux for port F " "USB0_VBC,TRACE_D03,SMC0_ABE1,?..."
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux for port F bit 1" "ETH0_RXD1,CNT0_OUTB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux for port F bit 0" "ETH0_RXD0,CNT0_OUTA,?..."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PORTF_DATA_TGL,Port F GPIO Output Toggle Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
bitfld.long 0x00 15. " PX15 ,Port F bit 15 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PX14 ,Port F bit 14 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PX13 ,Port F bit 13 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PX12 ,Port F bit 12 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PX11 ,Port F bit 11 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PX10 ,Port F bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port F bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port F bit 8 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PX7 ,Port F bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port F bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port F bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port F bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port F bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port F bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port F bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port F bit 0 toggle" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 10. " PX10 ,Port F bit 10 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PX9 ,Port F bit 9 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PX8 ,Port F bit 8 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PX7 ,Port F bit 7 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PX6 ,Port F bit 6 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PX5 ,Port F bit 5 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PX4 ,Port F bit 4 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PX3 ,Port F bit 3 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PX2 ,Port F bit 2 toggle" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PX1 ,Port F bit 1 toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PX0 ,Port F bit 0 toggle" "No effect,Toggle"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PORTF_POL_SET/CLR,Port F GPIO Polarity Invert Register"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PX15 ,Port F bit 15 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PX14 ,Port F bit 14 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PX13 ,Port F bit 13 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PX12 ,Port F bit 12 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 polarity invert" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PX11 ,Port F bit 11 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PX10 ,Port F bit 10 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PX9 ,Port F bit 9 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PX8 ,Port F bit 8 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PX7 ,Port F bit 7 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PX6 ,Port F bit 6 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PX5 ,Port F bit 5 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PX4 ,Port F bit 4 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PX3 ,Port F bit 3 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PX2 ,Port F bit 2 polarity invert" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PX1 ,Port F bit 1 polarity invert" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PX0 ,Port F bit 0 polarity invert" "Enabled,Disabled"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PORTF_LOCK,Port F GPIO Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 5. " POLAR ,Polarity lock" "Unlock POL,Lock POL"
|
|
bitfld.long 0x00 4. " INEN ,Input enable lock" "Unlock INEN,Lock INEN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIR ,Direction lock" "Lock DIR,Unlock DIR"
|
|
bitfld.long 0x00 2. " DATA ,Data TGL lock" "Unlock DATA,Lock DATA"
|
|
bitfld.long 0x00 1. " MUX ,Function multiplexer lock" "Unlock MUX,Lock MUX"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FER ,Function enable lock" "Unlock FER,Lock FER"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "TIMER (General-Purpose Timer)"
|
|
base ad:0x40000804
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIMER0_RUN,TIMER0 Run Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
setclrfld.word 0x00 7. 0x04 7. 0x08 7. " TMR07 ,Start/stop timer 7" "Stop,Start"
|
|
setclrfld.word 0x00 6. 0x04 6. 0x08 6. " TMR06 ,Start/stop timer 6" "Stop,Start"
|
|
setclrfld.word 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Start/stop timer 5" "Stop,Start"
|
|
textline " "
|
|
setclrfld.word 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Start/stop timer 4" "Stop,Start"
|
|
else
|
|
textline " "
|
|
setclrfld.word 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Start/stop timer 5" "Stop,Start"
|
|
setclrfld.word 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Start/stop timer 4" "Stop,Start"
|
|
endif
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x04 3. 0x08 3. " TMR03 ,Start/stop timer 3" "Stop,Start"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x08 2. " TMR02 ,Start/stop timer 2" "Stop,Start"
|
|
setclrfld.word 0x00 1. 0x04 1. 0x08 1. " TMR01 ,Start/stop timer 1" "Stop,Start"
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x04 0. 0x08 0. " TMR00 ,Start/stop timer 0" "Stop,Start"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIMER0_STOP_CFG,TIMER0 Stop Configuration Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
setclrfld.word 0x00 7. 0x04 7. 0x08 7. " TMR07 ,Stop mode select" "Graceful,Abrupt"
|
|
setclrfld.word 0x00 6. 0x04 6. 0x08 6. " TMR06 ,Stop mode select" "Graceful,Abrupt"
|
|
setclrfld.word 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Stop mode select" "Graceful,Abrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Stop mode select" "Graceful,Abrupt"
|
|
else
|
|
textline " "
|
|
setclrfld.word 0x00 5. 0x04 5. 0x08 5. " TMR05 ,Stop mode select" "Graceful,Abrupt"
|
|
setclrfld.word 0x00 4. 0x04 4. 0x08 4. " TMR04 ,Stop mode select" "Graceful,Abrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x04 3. 0x08 3. " TMR03 ,Stop mode select" "Graceful,Abrupt"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x08 2. " TMR02 ,Stop mode select" "Graceful,Abrupt"
|
|
setclrfld.word 0x00 1. 0x04 1. 0x08 1. " TMR01 ,Stop mode select" "Graceful,Abrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x04 0. 0x08 0. " TMR00 ,Stop mode select" "Graceful,Abrupt"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIMER0_DATA_IMSK,TIMER0 Data Interrupt Mask Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
bitfld.word 0x00 7. " TMR07 ,Data interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 6. " TMR06 ,Data interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 5. " TMR05 ,Data interrupt mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TMR04 ,Data interrupt mask" "Unmasked,Masked"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 5. " TMR05 ,Data interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 4. " TMR04 ,Data interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 3. " TMR03 ,Data interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 2. " TMR02 ,Data interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 1. " TMR01 ,Data interrupt mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMR00 ,Data interrupt mask" "Unmasked,Masked"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIMER0_STAT_IMSK,TIMER0 Status Interrupt Mask Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
bitfld.word 0x00 7. " TMR07 ,Status interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 6. " TMR06 ,Status interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 5. " TMR05 ,Status interrupt mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TMR04 ,Status interrupt mask" "Unmasked,Masked"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 5. " TMR05 ,Status interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 4. " TMR04 ,Status interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 3. " TMR03 ,Status interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 2. " TMR02 ,Status interrupt mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 1. " TMR01 ,Status interrupt mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMR00 ,Status interrupt mask" "Unmasked,Masked"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIMER0_TRG_MSK,TIMER0 Trigger Master Mask Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
bitfld.word 0x00 7. " TMR07 ,Trigger output mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 6. " TMR06 ,Trigger output mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 5. " TMR05 ,Trigger output mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TMR04 ,Trigger output mask" "Unmasked,Masked"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 5. " TMR05 ,Trigger output mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 4. " TMR04 ,Trigger output mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 3. " TMR03 ,Trigger output mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 2. " TMR02 ,Trigger output mask" "Unmasked,Masked"
|
|
bitfld.word 0x00 1. " TMR01 ,Trigger output mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMR00 ,Trigger output mask" "Unmasked,Masked"
|
|
group.word 0x24++0x03
|
|
line.word 0x00 "TIMER0_TRG_IE,TIMER0 Trigger Slave Enable Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
bitfld.word 0x00 7. " TMR07 ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TMR06 ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TMR05 ,Trigger input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TMR04 ,Trigger input enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.word 0x00 5. " TMR05 ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TMR04 ,Trigger input enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 3. " TMR03 ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " TMR02 ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TMR01 ,Trigger input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMR00 ,Trigger input enable" "Disabled,Enabled"
|
|
line.word 0x02 "TIMER0_DATA_ILAT,TIMER0 Data Interrupt Latch Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
eventfld.word 0x02 7. " TMR07 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 6. " TMR06 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 5. " TMR05 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x02 4. " TMR04 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
eventfld.word 0x02 5. " TMR05 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 4. " TMR04 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.word 0x02 3. " TMR03 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 2. " TMR02 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x02 1. " TMR01 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x02 0. " TMR00 ,Data interrupt latch" "No interrupt,Interrupt"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIMER0_STAT_ILAT,TIMER0 Status Interrupt Latch Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
eventfld.word 0x00 7. " TMR07 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 6. " TMR06 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 5. " TMR05 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 4. " TMR04 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
eventfld.word 0x00 5. " TMR05 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " TMR04 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.word 0x00 3. " TMR03 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " TMR02 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " TMR01 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " TMR00 ,Status interrupt latch" "No interrupt,Interrupt"
|
|
textline " "
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TIMER0_ERR_TYPE,TIMER0 Error Type Status Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 14.--15. " TERR7 ,Error type for timer 7" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 12.--13. " TERR6 ,Error type for timer 6" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 10.--11. " TERR5 ,Error type for timer 5" "No Error,Counter Overflow,PER,WID or DLY"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TERR4 ,Error type for timer 4" "No Error,Counter Overflow,PER,WID or DLY"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TERR5 ,Error type for timer 5" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 8.--9. " TERR4 ,Error type for timer 4" "No Error,Counter Overflow,PER,WID or DLY"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TERR3 ,Error type for timer 3" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 4.--5. " TERR2 ,Error type for timer 2" "No Error,Counter Overflow,PER,WID or DLY"
|
|
bitfld.long 0x00 2.--3. " TERR1 ,Error type for timer 1" "No Error,Counter Overflow,PER,WID or DLY"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TERR0 ,Error type for timer 0" "No Error,Counter Overflow,PER,WID or DLY"
|
|
wgroup.long 0x34++0x0B
|
|
line.long 0x00 "TIMER0_BCAST_PER,TIMER0 Broadcast Period Register"
|
|
line.long 0x04 "TIMER0_BCAST_WID,TIMER0 Broadcast Width Register"
|
|
line.long 0x08 "TIMER0_BCAST_DLY,TIMER0 Broadcast Delay Register"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSP-SC589")||cpuis("ADSPCM40*"))
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "TIMER0_TMR0_CFG,TIMER0 Timer 0 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x5C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR0_CNT,TIMER0 Timer 0 Counter Register"
|
|
group.long (0x5C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR0_PER,TIMER0 Timer 0 Period Register"
|
|
line.long 0x04 "TIMER0_TMR0_WID,TIMER0 Timer 0 Width Register"
|
|
line.long 0x08 "TIMER0_TMR0_DLY,TIMER0 Timer 0 Delay Register"
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "TIMER0_TMR1_CFG,TIMER0 Timer 1 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x7C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR1_CNT,TIMER0 Timer 1 Counter Register"
|
|
group.long (0x7C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR1_PER,TIMER0 Timer 1 Period Register"
|
|
line.long 0x04 "TIMER0_TMR1_WID,TIMER0 Timer 1 Width Register"
|
|
line.long 0x08 "TIMER0_TMR1_DLY,TIMER0 Timer 1 Delay Register"
|
|
group.word 0x9C++0x01
|
|
line.word 0x00 "TIMER0_TMR2_CFG,TIMER0 Timer 2 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x9C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR2_CNT,TIMER0 Timer 2 Counter Register"
|
|
group.long (0x9C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR2_PER,TIMER0 Timer 2 Period Register"
|
|
line.long 0x04 "TIMER0_TMR2_WID,TIMER0 Timer 2 Width Register"
|
|
line.long 0x08 "TIMER0_TMR2_DLY,TIMER0 Timer 2 Delay Register"
|
|
group.word 0xBC++0x01
|
|
line.word 0x00 "TIMER0_TMR3_CFG,TIMER0 Timer 3 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xBC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR3_CNT,TIMER0 Timer 3 Counter Register"
|
|
group.long (0xBC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR3_PER,TIMER0 Timer 3 Period Register"
|
|
line.long 0x04 "TIMER0_TMR3_WID,TIMER0 Timer 3 Width Register"
|
|
line.long 0x08 "TIMER0_TMR3_DLY,TIMER0 Timer 3 Delay Register"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "TIMER0_TMR4_CFG,TIMER0 Timer 4 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xDC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR4_CNT,TIMER0 Timer 4 Counter Register"
|
|
group.long (0xDC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR4_PER,TIMER0 Timer 4 Period Register"
|
|
line.long 0x04 "TIMER0_TMR4_WID,TIMER0 Timer 4 Width Register"
|
|
line.long 0x08 "TIMER0_TMR4_DLY,TIMER0 Timer 4 Delay Register"
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "TIMER0_TMR5_CFG,TIMER0 Timer 5 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xFC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR5_CNT,TIMER0 Timer 5 Counter Register"
|
|
group.long (0xFC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR5_PER,TIMER0 Timer 5 Period Register"
|
|
line.long 0x04 "TIMER0_TMR5_WID,TIMER0 Timer 5 Width Register"
|
|
line.long 0x08 "TIMER0_TMR5_DLY,TIMER0 Timer 5 Delay Register"
|
|
group.word 0x11C++0x01
|
|
line.word 0x00 "TIMER0_TMR6_CFG,TIMER0 Timer 6 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x11C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR6_CNT,TIMER0 Timer 6 Counter Register"
|
|
group.long (0x11C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR6_PER,TIMER0 Timer 6 Period Register"
|
|
line.long 0x04 "TIMER0_TMR6_WID,TIMER0 Timer 6 Width Register"
|
|
line.long 0x08 "TIMER0_TMR6_DLY,TIMER0 Timer 6 Delay Register"
|
|
group.word 0x13C++0x01
|
|
line.word 0x00 "TIMER0_TMR7_CFG,TIMER0 Timer 7 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate Capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active Edge,Delay Expired,Width Plus Delay Expired,Period Expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period Watchdog,Width Watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x13C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR7_CNT,TIMER0 Timer 7 Counter Register"
|
|
group.long (0x13C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR7_PER,TIMER0 Timer 7 Period Register"
|
|
line.long 0x04 "TIMER0_TMR7_WID,TIMER0 Timer 7 Width Register"
|
|
line.long 0x08 "TIMER0_TMR7_DLY,TIMER0 Timer 7 Delay Register"
|
|
else
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "TIMER0_TMR0_CFG,TIMER0 Timer 0 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x5C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR0_CNT,TIMER0 Timer 0 Counter Register"
|
|
group.long (0x5C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR0_PER,TIMER0 Timer 0 Period Register"
|
|
line.long 0x04 "TIMER0_TMR0_WID,TIMER0 Timer 0 Width Register"
|
|
line.long 0x08 "TIMER0_TMR0_DLY,TIMER0 Timer 0 Delay Register"
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "TIMER0_TMR1_CFG,TIMER0 Timer 1 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x7C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR1_CNT,TIMER0 Timer 1 Counter Register"
|
|
group.long (0x7C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR1_PER,TIMER0 Timer 1 Period Register"
|
|
line.long 0x04 "TIMER0_TMR1_WID,TIMER0 Timer 1 Width Register"
|
|
line.long 0x08 "TIMER0_TMR1_DLY,TIMER0 Timer 1 Delay Register"
|
|
group.word 0x9C++0x01
|
|
line.word 0x00 "TIMER0_TMR2_CFG,TIMER0 Timer 2 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0x9C+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR2_CNT,TIMER0 Timer 2 Counter Register"
|
|
group.long (0x9C+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR2_PER,TIMER0 Timer 2 Period Register"
|
|
line.long 0x04 "TIMER0_TMR2_WID,TIMER0 Timer 2 Width Register"
|
|
line.long 0x08 "TIMER0_TMR2_DLY,TIMER0 Timer 2 Delay Register"
|
|
group.word 0xBC++0x01
|
|
line.word 0x00 "TIMER0_TMR3_CFG,TIMER0 Timer 3 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xBC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR3_CNT,TIMER0 Timer 3 Counter Register"
|
|
group.long (0xBC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR3_PER,TIMER0 Timer 3 Period Register"
|
|
line.long 0x04 "TIMER0_TMR3_WID,TIMER0 Timer 3 Width Register"
|
|
line.long 0x08 "TIMER0_TMR3_DLY,TIMER0 Timer 3 Delay Register"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "TIMER0_TMR4_CFG,TIMER0 Timer 4 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xDC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR4_CNT,TIMER0 Timer 4 Counter Register"
|
|
group.long (0xDC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR4_PER,TIMER0 Timer 4 Period Register"
|
|
line.long 0x04 "TIMER0_TMR4_WID,TIMER0 Timer 4 Width Register"
|
|
line.long 0x08 "TIMER0_TMR4_DLY,TIMER0 Timer 4 Delay Register"
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "TIMER0_TMR5_CFG,TIMER0 Timer 5 Configuration Register"
|
|
bitfld.word 0x00 15. " EMURUN ,Emulation run" "Stop,Run"
|
|
bitfld.word 0x00 14. " BPEREN ,Broadcast period enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BWIDEN ,Broadcast width enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BDLYEN ,Broadcast delay enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OUTDIS ,Output disable" "No,Yes"
|
|
bitfld.word 0x00 10. " TINSEL ,Timer input select (for WIDCAP)" "TMR,TMR Alternate capture"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CLKSEL ,Clock select" "SCLK,TMR_ALT_CLK0,,TMR_ALT_CLK1"
|
|
bitfld.word 0x00 7. " PULSEHI ,Polarity response select" "Negative,Positive"
|
|
bitfld.word 0x00 6. " SLAVETRIG ,Slave trigger response" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " IRQMODE ,Interrupt modes" "Active edge,Delay expired,Width plus delay expired,Period expired"
|
|
bitfld.word 0x00 0.--3. " TMODE ,Timer mode select" "Idle,Idle,Idle,Idle,Idle,Idle,Idle,Idle,Period watchdog,Width watchdog,Asserting edge of waveform,De-asserting edge of waveform,Continuous PWMOUT,Single pulse PWMOUT,EXTCLK,PININT"
|
|
rgroup.long (0xFC+0x04)++0x03
|
|
line.long 0x00 "TIMER0_TMR5_CNT,TIMER0 Timer 5 Counter Register"
|
|
group.long (0xFC+0x08)++0x0B
|
|
line.long 0x00 "TIMER0_TMR5_PER,TIMER0 Timer 5 Period Register"
|
|
line.long 0x04 "TIMER0_TMR5_WID,TIMER0 Timer 5 Width Register"
|
|
line.long 0x08 "TIMER0_TMR5_DLY,TIMER0 Timer 5 Delay Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CPTMR (Capture Timer)"
|
|
base ad:0x4002E004
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RUN,Run Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CPT[2] ,Timer 2 start" "Stopped,Started"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Timer 1 start" "Stopped,Started"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Timer 0 start" "Stopped,Started"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DATA_IMASK,Data Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CPT[2] ,Data interrupt mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Data Interrupt mask 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Data interrupt mask 0" "Masked,Not masked"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STAT_IMASK,Status Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CPT[2] ,Status interrupt mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Status interrupt mask 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Status interrupt mask 0" "Masked,Not masked"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DATA_ILAT,Data Interrupt Latch Status Register"
|
|
eventfld.long 0x00 2. " CPT[2] ,Data interrupt latch 2" "Not latched,Latched"
|
|
eventfld.long 0x00 1. " [1] ,Data interrupt latch 1" "Not latched,Latched"
|
|
eventfld.long 0x00 0. " [0] ,Data interrupt latch 0" "Not latched,Latched"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "STAT_ILAT,Interrupt Latch Status Register"
|
|
eventfld.long 0x00 2. " CPT[2] ,Counter overflow 2" "No Overflow,Overflow"
|
|
eventfld.long 0x00 1. " [1] ,Counter overflow 1" "No Overflow,Overflow"
|
|
eventfld.long 0x00 0. " [0] ,Counter overflow 0" "No Overflow,Overflow"
|
|
textline " "
|
|
group.long 0x7FC++0x03
|
|
line.long 0x00 "CFG0,Configuration 0 Register"
|
|
bitfld.long 0x00 6. " TRIG_INEN ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIN_INEN ,Timer input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TRIGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TINPOL ,Input polarity" "Active high,Active low"
|
|
rgroup.long (0x7FC+0x04)++0x07
|
|
line.long 0x00 "CNT0,Counter 0 Register"
|
|
line.long 0x04 "TON0,On-time Capture 0 Register"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "CFG1,Configuration 1 Register"
|
|
bitfld.long 0x00 6. " TRIG_INEN ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIN_INEN ,Timer input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TRIGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TINPOL ,Input polarity" "Active high,Active low"
|
|
rgroup.long (0x87C+0x04)++0x07
|
|
line.long 0x00 "CNT1,Counter 1 Register"
|
|
line.long 0x04 "TON1,On-time Capture 1 Register"
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "CFG2,Configuration 2 Register"
|
|
bitfld.long 0x00 6. " TRIG_INEN ,Trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIN_INEN ,Timer input enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TRIGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TINPOL ,Input polarity" "Active high,Active low"
|
|
rgroup.long (0x8FC+0x04)++0x07
|
|
line.long 0x00 "CNT2,Counter 2 Register"
|
|
line.long 0x04 "TON2,On-time Capture 2 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x4002D000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDOG0_CTL,WDOG0 Control Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 16. " WDWE ,Watchdog window event" "Not occurred,Occurred"
|
|
endif
|
|
eventfld.long 0x00 15. " WDRO ,Watch dog roll-over" "Not expired,Expired"
|
|
hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch dog enable"
|
|
if (((per.l(ad:0x4002D000))&0xFF0)==0xAD0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDOG0_CNT,WDOG0 Count Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "WDOG0_CNT,WDOG0 Count Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WDOG0_STAT,WDOG0 Watchdog Timer Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WDOG0_WIN,WDOG0 Watchdog Timer Window Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CNT (General-Purpose Counter)"
|
|
tree "CNT0"
|
|
base ad:0x40009000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CNT0_CFG,CNT0 Configuration Register"
|
|
bitfld.long 0x00 15. " INPDIS ,CUD and CDG pin input disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BNDMODE ,Boundary register mode" "BND_COMP,BND_ZERO,BND_CAPT,BND_AEXT"
|
|
bitfld.long 0x00 11. " ZMZC ,CZM zeros counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CNTMODE ,Counter operating mode" "QUAD_ENC,BIN_ENC,UD_CNT,,DIR_CNT,DIR_TMR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIVMODE ,Divider mode" "Weighted,Non weighted"
|
|
bitfld.long 0x00 6. " CZMINV ,CZM pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 5. " CUDINV ,CUD pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 4. " CDGINV ,CDG pin polarity invert" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIVNTV ,Non-debounced inputs to divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DIVEN ,Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBEN ,Debounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT0_IMSK,CNT0 Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " DCHNG ,Direction change interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " DERR ,Direction error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MERR ,M value programming error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 11. " STP ,Stop detect interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CZMZ ,Counter zeroed by zero marker interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " CZME ,Zero marker error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CZM ,CZM pin/pushbutton interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " CZERO ,CNT_CNTR counts to zero interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " COV15 ,Bit 15 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " COV31 ,Bit 31 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " MAXC ,Max count interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " MINC ,Min count interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DC ,Downcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " UC ,Upcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " IC ,Illegal Gray/binary code interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "CNT0_STAT,CNT0 Status Register"
|
|
eventfld.long 0x08 14. " DCHNG ,Direction change interrupt enable" "0,1"
|
|
eventfld.long 0x08 13. " DERR ,Direction error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " MERR ,M value programming error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 11. " STP ,Stop detect interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CZMZ ,Counter zeroed by zero marker interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " CZME ,Zero marker error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " CZM ,CZM pin/pushbutton interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " CZERO ,CNT_CNTR counts to zero interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " COV15 ,Bit 15 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " COV31 ,Bit 31 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " MAXC ,Max count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " MINC ,Min count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 2. " DC ,Down count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " UC ,Up count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " IC ,Illegal Gray/binary code interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "CNT0_CMD,CNT0 Command Register"
|
|
bitfld.long 0x0C 12. " W1ZMONCE ,Write 1 zero marker clear once enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " W1LMAXMIN ,Write 1 MAX copy from MIN" "No effect,Copy"
|
|
bitfld.long 0x0C 9. " W1LMAXCNT ,Write 1 MAX capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 8. " W1LMAXZERO ,Write 1 MAX to zero" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " W1LMINMAX ,Write 1 MIN copy from MAX" "No effect,Copy"
|
|
bitfld.long 0x0C 5. " W1LMINCNT ,Write 1 MIN capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 4. " W1LMINZERO ,Write 1 MIN to zero" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " W1LCNTMAX ,Write 1 CNTR load from MAX" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " W1LCNTMIN ,Write 1 CNTR load from MIN" "No effect,Load"
|
|
bitfld.long 0x0C 0. " W1LCNTZERO ,Write 1 CNTR to zero" "No effect,Clear"
|
|
line.long 0x10 "CNT0_DEBNCE,CNT0 Debounce Register"
|
|
bitfld.long 0x10 0.--4. " DPRESCALE ,Debounce prescale" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,?..."
|
|
line.long 0x14 "CNT0_CNTR,CNT0 Counter Register"
|
|
line.long 0x18 "CNT0_MAX,CNT0 Maximum Count Register"
|
|
line.long 0x1C "CNT0_MIN,CNT0 Minimum Count Register"
|
|
line.long 0x20 "CNT0_MDIV,CNT0 M Value For Divider"
|
|
hexmask.long.word 0x20 0.--15. 1. " MDIV ,M value for divider"
|
|
line.long 0x24 "CNT0_NDIV,CNT0 N Value For Divider"
|
|
hexmask.long.word 0x24 0.--15. 1. " NDIV ,N value for divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT1"
|
|
base ad:0x4000A000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CNT1_CFG,CNT1 Configuration Register"
|
|
bitfld.long 0x00 15. " INPDIS ,CUD and CDG pin input disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BNDMODE ,Boundary register mode" "BND_COMP,BND_ZERO,BND_CAPT,BND_AEXT"
|
|
bitfld.long 0x00 11. " ZMZC ,CZM zeros counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CNTMODE ,Counter operating mode" "QUAD_ENC,BIN_ENC,UD_CNT,,DIR_CNT,DIR_TMR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIVMODE ,Divider mode" "Weighted,Non weighted"
|
|
bitfld.long 0x00 6. " CZMINV ,CZM pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 5. " CUDINV ,CUD pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 4. " CDGINV ,CDG pin polarity invert" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIVNTV ,Non-debounced inputs to divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DIVEN ,Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBEN ,Debounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT1_IMSK,CNT1 Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " DCHNG ,Direction change interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " DERR ,Direction error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MERR ,M value programming error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 11. " STP ,Stop detect interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CZMZ ,Counter zeroed by zero marker interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " CZME ,Zero marker error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CZM ,CZM pin/pushbutton interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " CZERO ,CNT_CNTR counts to zero interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " COV15 ,Bit 15 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " COV31 ,Bit 31 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " MAXC ,Max count interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " MINC ,Min count interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DC ,Downcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " UC ,Upcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " IC ,Illegal Gray/binary code interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "CNT1_STAT,CNT1 Status Register"
|
|
eventfld.long 0x08 14. " DCHNG ,Direction change interrupt enable" "0,1"
|
|
eventfld.long 0x08 13. " DERR ,Direction error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " MERR ,M value programming error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 11. " STP ,Stop detect interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CZMZ ,Counter zeroed by zero marker interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " CZME ,Zero marker error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " CZM ,CZM pin/pushbutton interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " CZERO ,CNT_CNTR counts to zero interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " COV15 ,Bit 15 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " COV31 ,Bit 31 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " MAXC ,Max count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " MINC ,Min count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 2. " DC ,Down count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " UC ,Up count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " IC ,Illegal Gray/binary code interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "CNT1_CMD,CNT1 Command Register"
|
|
bitfld.long 0x0C 12. " W1ZMONCE ,Write 1 zero marker clear once enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " W1LMAXMIN ,Write 1 MAX copy from MIN" "No effect,Copy"
|
|
bitfld.long 0x0C 9. " W1LMAXCNT ,Write 1 MAX capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 8. " W1LMAXZERO ,Write 1 MAX to zero" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " W1LMINMAX ,Write 1 MIN copy from MAX" "No effect,Copy"
|
|
bitfld.long 0x0C 5. " W1LMINCNT ,Write 1 MIN capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 4. " W1LMINZERO ,Write 1 MIN to zero" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " W1LCNTMAX ,Write 1 CNTR load from MAX" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " W1LCNTMIN ,Write 1 CNTR load from MIN" "No effect,Load"
|
|
bitfld.long 0x0C 0. " W1LCNTZERO ,Write 1 CNTR to zero" "No effect,Clear"
|
|
line.long 0x10 "CNT1_DEBNCE,CNT1 Debounce Register"
|
|
bitfld.long 0x10 0.--4. " DPRESCALE ,Debounce prescale" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,?..."
|
|
line.long 0x14 "CNT1_CNTR,CNT1 Counter Register"
|
|
line.long 0x18 "CNT1_MAX,CNT1 Maximum Count Register"
|
|
line.long 0x1C "CNT1_MIN,CNT1 Minimum Count Register"
|
|
line.long 0x20 "CNT1_MDIV,CNT1 M Value For Divider"
|
|
hexmask.long.word 0x20 0.--15. 1. " MDIV ,M value for divider"
|
|
line.long 0x24 "CNT1_NDIV,CNT1 N Value For Divider"
|
|
hexmask.long.word 0x24 0.--15. 1. " NDIV ,N value for divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT2"
|
|
base ad:0x4000B000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CNT2_CFG,CNT2 Configuration Register"
|
|
bitfld.long 0x00 15. " INPDIS ,CUD and CDG pin input disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BNDMODE ,Boundary register mode" "BND_COMP,BND_ZERO,BND_CAPT,BND_AEXT"
|
|
bitfld.long 0x00 11. " ZMZC ,CZM zeros counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CNTMODE ,Counter operating mode" "QUAD_ENC,BIN_ENC,UD_CNT,,DIR_CNT,DIR_TMR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIVMODE ,Divider mode" "Weighted,Non weighted"
|
|
bitfld.long 0x00 6. " CZMINV ,CZM pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 5. " CUDINV ,CUD pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 4. " CDGINV ,CDG pin polarity invert" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIVNTV ,Non-debounced inputs to divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DIVEN ,Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBEN ,Debounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT2_IMSK,CNT2 Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " DCHNG ,Direction change interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " DERR ,Direction error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MERR ,M value programming error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 11. " STP ,Stop detect interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CZMZ ,Counter zeroed by zero marker interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " CZME ,Zero marker error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CZM ,CZM pin/pushbutton interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " CZERO ,CNT_CNTR counts to zero interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " COV15 ,Bit 15 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " COV31 ,Bit 31 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " MAXC ,Max count interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " MINC ,Min count interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DC ,Downcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " UC ,Upcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " IC ,Illegal Gray/binary code interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "CNT2_STAT,CNT2 Status Register"
|
|
eventfld.long 0x08 14. " DCHNG ,Direction change interrupt enable" "0,1"
|
|
eventfld.long 0x08 13. " DERR ,Direction error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " MERR ,M value programming error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 11. " STP ,Stop detect interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CZMZ ,Counter zeroed by zero marker interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " CZME ,Zero marker error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " CZM ,CZM pin/pushbutton interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " CZERO ,CNT_CNTR counts to zero interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " COV15 ,Bit 15 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " COV31 ,Bit 31 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " MAXC ,Max count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " MINC ,Min count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 2. " DC ,Down count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " UC ,Up count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " IC ,Illegal Gray/binary code interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "CNT2_CMD,CNT2 Command Register"
|
|
bitfld.long 0x0C 12. " W1ZMONCE ,Write 1 zero marker clear once enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " W1LMAXMIN ,Write 1 MAX copy from MIN" "No effect,Copy"
|
|
bitfld.long 0x0C 9. " W1LMAXCNT ,Write 1 MAX capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 8. " W1LMAXZERO ,Write 1 MAX to zero" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " W1LMINMAX ,Write 1 MIN copy from MAX" "No effect,Copy"
|
|
bitfld.long 0x0C 5. " W1LMINCNT ,Write 1 MIN capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 4. " W1LMINZERO ,Write 1 MIN to zero" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " W1LCNTMAX ,Write 1 CNTR load from MAX" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " W1LCNTMIN ,Write 1 CNTR load from MIN" "No effect,Load"
|
|
bitfld.long 0x0C 0. " W1LCNTZERO ,Write 1 CNTR to zero" "No effect,Clear"
|
|
line.long 0x10 "CNT2_DEBNCE,CNT2 Debounce Register"
|
|
bitfld.long 0x10 0.--4. " DPRESCALE ,Debounce prescale" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,?..."
|
|
line.long 0x14 "CNT2_CNTR,CNT2 Counter Register"
|
|
line.long 0x18 "CNT2_MAX,CNT2 Maximum Count Register"
|
|
line.long 0x1C "CNT2_MIN,CNT2 Minimum Count Register"
|
|
line.long 0x20 "CNT2_MDIV,CNT2 M Value For Divider"
|
|
hexmask.long.word 0x20 0.--15. 1. " MDIV ,M value for divider"
|
|
line.long 0x24 "CNT2_NDIV,CNT2 N Value For Divider"
|
|
hexmask.long.word 0x24 0.--15. 1. " NDIV ,N value for divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT3"
|
|
base ad:0x4000C000
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CNT3_CFG,CNT3 Configuration Register"
|
|
bitfld.long 0x00 15. " INPDIS ,CUD and CDG pin input disable" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " BNDMODE ,Boundary register mode" "BND_COMP,BND_ZERO,BND_CAPT,BND_AEXT"
|
|
bitfld.long 0x00 11. " ZMZC ,CZM zeros counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " CNTMODE ,Counter operating mode" "QUAD_ENC,BIN_ENC,UD_CNT,,DIR_CNT,DIR_TMR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIVMODE ,Divider mode" "Weighted,Non weighted"
|
|
bitfld.long 0x00 6. " CZMINV ,CZM pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 5. " CUDINV ,CUD pin polarity invert" "Rising,Falling"
|
|
bitfld.long 0x00 4. " CDGINV ,CDG pin polarity invert" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIVNTV ,Non-debounced inputs to divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DIVEN ,Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DEBEN ,Debounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT3_IMSK,CNT3 Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " DCHNG ,Direction change interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " DERR ,Direction error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MERR ,M value programming error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 11. " STP ,Stop detect interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CZMZ ,Counter zeroed by zero marker interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " CZME ,Zero marker error interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CZM ,CZM pin/pushbutton interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " CZERO ,CNT_CNTR counts to zero interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " COV15 ,Bit 15 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " COV31 ,Bit 31 overflow interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " MAXC ,Max count interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " MINC ,Min count interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DC ,Downcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " UC ,Upcount interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " IC ,Illegal Gray/binary code interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "CNT3_STAT,CNT3 Status Register"
|
|
eventfld.long 0x08 14. " DCHNG ,Direction change interrupt enable" "0,1"
|
|
eventfld.long 0x08 13. " DERR ,Direction error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " MERR ,M value programming error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 11. " STP ,Stop detect interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CZMZ ,Counter zeroed by zero marker interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " CZME ,Zero marker error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " CZM ,CZM pin/pushbutton interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " CZERO ,CNT_CNTR counts to zero interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " COV15 ,Bit 15 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " COV31 ,Bit 31 overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " MAXC ,Max count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " MINC ,Min count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 2. " DC ,Down count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " UC ,Up count interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " IC ,Illegal Gray/binary code interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "CNT3_CMD,CNT3 Command Register"
|
|
bitfld.long 0x0C 12. " W1ZMONCE ,Write 1 zero marker clear once enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " W1LMAXMIN ,Write 1 MAX copy from MIN" "No effect,Copy"
|
|
bitfld.long 0x0C 9. " W1LMAXCNT ,Write 1 MAX capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 8. " W1LMAXZERO ,Write 1 MAX to zero" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " W1LMINMAX ,Write 1 MIN copy from MAX" "No effect,Copy"
|
|
bitfld.long 0x0C 5. " W1LMINCNT ,Write 1 MIN capture from CNTR" "No effect,Capture"
|
|
bitfld.long 0x0C 4. " W1LMINZERO ,Write 1 MIN to zero" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " W1LCNTMAX ,Write 1 CNTR load from MAX" "No effect,Load"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " W1LCNTMIN ,Write 1 CNTR load from MIN" "No effect,Load"
|
|
bitfld.long 0x0C 0. " W1LCNTZERO ,Write 1 CNTR to zero" "No effect,Clear"
|
|
line.long 0x10 "CNT3_DEBNCE,CNT3 Debounce Register"
|
|
bitfld.long 0x10 0.--4. " DPRESCALE ,Debounce prescale" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,?..."
|
|
line.long 0x14 "CNT3_CNTR,CNT3 Counter Register"
|
|
line.long 0x18 "CNT3_MAX,CNT3 Maximum Count Register"
|
|
line.long 0x1C "CNT3_MIN,CNT3 Minimum Count Register"
|
|
line.long 0x20 "CNT3_MDIV,CNT3 M Value For Divider"
|
|
hexmask.long.word 0x20 0.--15. 1. " MDIV ,M value for divider"
|
|
line.long 0x24 "CNT3_NDIV,CNT3 N Value For Divider"
|
|
hexmask.long.word 0x24 0.--15. 1. " NDIV ,N value for divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "PWM (Pulse Width Modulator)"
|
|
tree "PWM0"
|
|
base ad:0x40008000
|
|
width 19.
|
|
if (((per.l(ad:0x40008000))&0x01)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PWM0_CTL,PWM0 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWM0_CHANCFG,PWM0 Channel Configuration Register"
|
|
bitfld.long 0x04 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x04 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x04 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x04 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x04 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x04 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x04 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM0_CTL,PWM0 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
rbitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PWM0_CHANCFG,PWM0 Channel Configuration Register"
|
|
bitfld.long 0x00 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x00 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x00 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x00 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x00 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x00 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x00 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWM0_TRIPCFG,PWM0 Trip Configuration Register"
|
|
bitfld.long 0x00 27. " MODE1D ,Mode of TRIP1 for channel D" "Fault trip,Self restart"
|
|
bitfld.long 0x00 26. " EN1D ,Enable TRIP1 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MODE0D ,Mode of TRIP0 for channel D" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 24. " EN0D ,Enable TRIP0 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MODE1C ,Mode of TRIP1 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 18. " EN1C ,Enable TRIP1 as a trip source for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE0C ,Mode of TRIP0 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 16. " EN0C ,Enable TRIP0 as a trip source for channel C" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MODE1B ,Mode of TRIP1 for channel B" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN1B ,Enable TRIP1 as a trip source for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE0B ,Mode of TRIP0 for channel B" "Fault trip,Self restart"
|
|
bitfld.long 0x00 8. " EN0B ,Enable TRIP0 as a trip source for channel B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MODE1A ,Mode of TRIP1 for channel A" "Fault trip,Self restart"
|
|
bitfld.long 0x00 2. " EN1A ,Enable TRIP1 as a trip source for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MODE0A ,Mode of TRIP0 for channel A" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN0A ,Enable TRIP0 as a trip source for channel A" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "PWM0_STAT,PWM0 Status Register"
|
|
rbitfld.long 0x00 31. " HPRDY ,Heightened-Precision ready status" "Not ready,Ready"
|
|
sif cpuis("ADSPCM40*")
|
|
textline " "
|
|
eventfld.long 0x00 30. " EMU ,Emulator Status" "0,1"
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
else
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 26. " TMR2PHASE ,PWMTMR2 phase status" "First,Second"
|
|
eventfld.long 0x00 25. " TMR1PHASE ,PWMTMR1 phase status" "First,Second"
|
|
eventfld.long 0x00 24. " TMR0PHASE ,PWMTMR0 phase status" "First,Second"
|
|
textline " "
|
|
eventfld.long 0x00 20. " TMR4PER ,PWMTMR4 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 19. " TMR3PER ,PWMTMR3 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 18. " TMR2PER ,PWMTMR2 period boundary status" "Not reached,Reached"
|
|
textline " "
|
|
eventfld.long 0x00 17. " TMR1PER ,PWMTMR1 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 16. " TMR0PER ,PWMTMR0 period boundary status" "Not reached,Reached"
|
|
rbitfld.long 0x00 11. " SRTRIPD ,Self-Restart trip status for channel D" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 10. " FLTTRIPD ,Fault trip status for channel D" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 9. " SRTRIPC ,Self-Restart trip status for channel C" "Not tripped,Tripped"
|
|
eventfld.long 0x00 8. " FLTTRIPC ,Fault trip status for channel C" "Not tripped,Tripped"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SRTRIPB ,Self-Restart trip status for channel B" "Not tripped,Tripped"
|
|
eventfld.long 0x00 6. " FLTTRIPB ,Fault trip status for channel B" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 5. " SRTRIPA ,Self-Restart trip status for channel A" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 4. " FLTTRIPA ,Fault trip status for channel A" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 3. " RAWTRIP1 ,Raw trip 1 status" "Low,High"
|
|
rbitfld.long 0x00 2. " RAWTRIP0 ,Raw trip 0 status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRIP1 ,Status bit set when TRIP1 is active low" "Not tripped,Tripped"
|
|
eventfld.long 0x00 0. " TRIP0 ,Status bit set when TRIP0 is active low" "Not tripped,Tripped"
|
|
line.long 0x04 "PWM0_IMSK,PWM0 Interrupt Mask Register"
|
|
bitfld.long 0x04 20. " TMR4PER ,PWMTMR4 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 19. " TMR3PER ,PWMTMR3 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " TMR2PER ,PWMTMR2 period boundary interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TMR1PER ,PWMTMR1 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " TMR0PER ,PWMTMR0 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " TRIP1 ,TRIP1 interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIP0 ,TRIP0 interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "PWM0_ILAT,PWM0 Interrupt Latch Register"
|
|
eventfld.long 0x08 20. " TMR4PER ,PWMTMR4 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " TMR3PER ,PWMTMR3 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " TMR2PER ,PWMTMR2 period latched interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " TMR1PER ,PWMTMR1 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " TMR0PER ,PWMTMR0 period boundary interrupt latched status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " TRIP1 ,TRIP1 interrupt latched status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " TRIP0 ,TRIP0 interrupt latched status" "No interrupt,Interrupt"
|
|
line.long 0x0C "PWM0_CHOPCFG,PWM0 Chop Configuration Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VALUE ,Gate chopping divisor"
|
|
sif cpuis("ADSPCM40*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PWM0_DT,PWM0 Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PWM0_SYNC_WID,PWM0 Sync Pulse Width Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Sync pulse width"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PWM0_TM0,PWM0 Timer 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PWM0_TM1,PWM0 Timer 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PWM0_TM2,PWM0 Timer 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PWM0_TM3,PWM0 Timer 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWM0_TM4,PWM0 Timer 4 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
tree "Channels Registers"
|
|
group.long 0x38++0x03 "Channel A"
|
|
line.long 0x00 "PWM0_DLYA,PWM0 Channel A Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel A delay value"
|
|
group.long 0x48++0x23
|
|
line.long 0x00 "PWM0_ACTL,PWM0 Channel A Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM0_AH0,PWM0 Channel A-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM0_AH1,PWM0 Channel A-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM0_AH0_HP,PWM0 Channel A-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM0_AH1_HP,PWM0 Channel A-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM0_AL0,PWM0 Channel A-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM0_AL1,PWM0 Channel A-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM0_AL0_HP,PWM0 Channel A-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM0_AL1_HP,PWM0 Channel A-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "PWM0_AH_DUTY0,PWM0 Channel A-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM0_AH_DUTY1,PWM0 Channel A-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM0_AL_DUTY0,PWM0 Channel A-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM0_AL_DUTY1,PWM0 Channel A-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PWM0_CHA_DT,PWM0 Channel A Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x3C++0x03 "Channel B"
|
|
line.long 0x00 "PWM0_DLYB,PWM0 Channel B Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel B delay value"
|
|
group.long 0x6C++0x23
|
|
line.long 0x00 "PWM0_BCTL,PWM0 Channel B Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM0_BH0,PWM0 Channel B-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM0_BH1,PWM0 Channel B-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM0_BH0_HP,PWM0 Channel B-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM0_BH1_HP,PWM0 Channel B-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM0_BL0,PWM0 Channel B-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM0_BL1,PWM0 Channel B-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM0_BL0_HP,PWM0 Channel B-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM0_BL1_HP,PWM0 Channel B-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xE8++0x0F
|
|
line.long 0x00 "PWM0_BH_DUTY0,PWM0 Channel B-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM0_BH_DUTY1,PWM0 Channel B-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM0_BL_DUTY0,PWM0 Channel B-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM0_BL_DUTY1,PWM0 Channel B-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PWM0_CHB_DT,PWM0 Channel B Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x40++0x03 "Channel C"
|
|
line.long 0x00 "PWM0_DLYC,PWM0 Channel C Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel C delay value"
|
|
group.long 0x90++0x23
|
|
line.long 0x00 "PWM0_CCTL,PWM0 Channel C Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM0_CH0,PWM0 Channel C-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM0_CH1,PWM0 Channel C-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM0_CH0_HP,PWM0 Channel C-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM0_CH1_HP,PWM0 Channel C-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM0_CL0,PWM0 Channel C-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM0_CL1,PWM0 Channel C-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM0_CL0_HP,PWM0 Channel C-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM0_CL1_HP,PWM0 Channel C-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xF8++0x0F
|
|
line.long 0x00 "PWM0_CH_DUTY0,PWM0 Channel C-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM0_CH_DUTY1,PWM0 Channel C-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM0_CL_DUTY0,PWM0 Channel C-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM0_CL_DUTY1,PWM0 Channel C-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PWM0_CHC_DT,PWM0 Channel C Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x44++0x03 "Channel D"
|
|
line.long 0x00 "PWM0_DLYD,PWM0 Channel D Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel D delay value"
|
|
group.long 0xB4++0x23
|
|
line.long 0x00 "PWM0_DCTL,PWM0 Channel D Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM0_DH0,PWM0 Channel D-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM0_DH1,PWM0 Channel D-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM0_DH0_HP,PWM0 Channel D-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM0_DH1_HP,PWM0 Channel D-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM0_DL0,PWM0 Channel D-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM0_DL1,PWM0 Channel D-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM0_DL0_HP,PWM0 Channel D-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM0_DL1_HP,PWM0 Channel D-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "PWM0_DH_DUTY0,PWM0 Channel D-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM0_DH_DUTY1,PWM0 Channel D-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM0_DL_DUTY0,PWM0 Channel D-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM0_DL_DUTY1,PWM0 Channel D-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PWM0_CHD_DT,PWM0 Channel D Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM1"
|
|
base ad:0x40008400
|
|
width 19.
|
|
if (((per.l(ad:0x40008400))&0x01)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PWM1_CTL,PWM1 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWM1_CHANCFG,PWM1 Channel Configuration Register"
|
|
bitfld.long 0x04 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x04 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x04 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x04 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x04 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x04 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x04 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM1_CTL,PWM1 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
rbitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PWM1_CHANCFG,PWM1 Channel Configuration Register"
|
|
bitfld.long 0x00 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x00 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x00 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x00 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x00 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x00 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x00 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWM1_TRIPCFG,PWM1 Trip Configuration Register"
|
|
bitfld.long 0x00 27. " MODE1D ,Mode of TRIP1 for channel D" "Fault trip,Self restart"
|
|
bitfld.long 0x00 26. " EN1D ,Enable TRIP1 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MODE0D ,Mode of TRIP0 for channel D" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 24. " EN0D ,Enable TRIP0 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MODE1C ,Mode of TRIP1 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 18. " EN1C ,Enable TRIP1 as a trip source for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE0C ,Mode of TRIP0 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 16. " EN0C ,Enable TRIP0 as a trip source for channel C" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MODE1B ,Mode of TRIP1 for channel B" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN1B ,Enable TRIP1 as a trip source for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE0B ,Mode of TRIP0 for channel B" "Fault trip,Self restart"
|
|
bitfld.long 0x00 8. " EN0B ,Enable TRIP0 as a trip source for channel B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MODE1A ,Mode of TRIP1 for channel A" "Fault trip,Self restart"
|
|
bitfld.long 0x00 2. " EN1A ,Enable TRIP1 as a trip source for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MODE0A ,Mode of TRIP0 for channel A" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN0A ,Enable TRIP0 as a trip source for channel A" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "PWM1_STAT,PWM1 Status Register"
|
|
rbitfld.long 0x00 31. " HPRDY ,Heightened-Precision ready status" "Not ready,Ready"
|
|
sif cpuis("ADSPCM40*")
|
|
textline " "
|
|
eventfld.long 0x00 30. " EMU ,Emulator Status" "0,1"
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
else
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 26. " TMR2PHASE ,PWMTMR2 phase status" "First,Second"
|
|
eventfld.long 0x00 25. " TMR1PHASE ,PWMTMR1 phase status" "First,Second"
|
|
eventfld.long 0x00 24. " TMR0PHASE ,PWMTMR0 phase status" "First,Second"
|
|
textline " "
|
|
eventfld.long 0x00 20. " TMR4PER ,PWMTMR4 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 19. " TMR3PER ,PWMTMR3 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 18. " TMR2PER ,PWMTMR2 period boundary status" "Not reached,Reached"
|
|
textline " "
|
|
eventfld.long 0x00 17. " TMR1PER ,PWMTMR1 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 16. " TMR0PER ,PWMTMR0 period boundary status" "Not reached,Reached"
|
|
rbitfld.long 0x00 11. " SRTRIPD ,Self-Restart trip status for channel D" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 10. " FLTTRIPD ,Fault trip status for channel D" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 9. " SRTRIPC ,Self-Restart trip status for channel C" "Not tripped,Tripped"
|
|
eventfld.long 0x00 8. " FLTTRIPC ,Fault trip status for channel C" "Not tripped,Tripped"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SRTRIPB ,Self-Restart trip status for channel B" "Not tripped,Tripped"
|
|
eventfld.long 0x00 6. " FLTTRIPB ,Fault trip status for channel B" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 5. " SRTRIPA ,Self-Restart trip status for channel A" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 4. " FLTTRIPA ,Fault trip status for channel A" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 3. " RAWTRIP1 ,Raw trip 1 status" "Low,High"
|
|
rbitfld.long 0x00 2. " RAWTRIP0 ,Raw trip 0 status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRIP1 ,Status bit set when TRIP1 is active low" "Not tripped,Tripped"
|
|
eventfld.long 0x00 0. " TRIP0 ,Status bit set when TRIP0 is active low" "Not tripped,Tripped"
|
|
line.long 0x04 "PWM1_IMSK,PWM1 Interrupt Mask Register"
|
|
bitfld.long 0x04 20. " TMR4PER ,PWMTMR4 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 19. " TMR3PER ,PWMTMR3 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " TMR2PER ,PWMTMR2 period boundary interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TMR1PER ,PWMTMR1 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " TMR0PER ,PWMTMR0 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " TRIP1 ,TRIP1 interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIP0 ,TRIP0 interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "PWM1_ILAT,PWM1 Interrupt Latch Register"
|
|
eventfld.long 0x08 20. " TMR4PER ,PWMTMR4 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " TMR3PER ,PWMTMR3 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " TMR2PER ,PWMTMR2 period latched interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " TMR1PER ,PWMTMR1 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " TMR0PER ,PWMTMR0 period boundary interrupt latched status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " TRIP1 ,TRIP1 interrupt latched status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " TRIP0 ,TRIP0 interrupt latched status" "No interrupt,Interrupt"
|
|
line.long 0x0C "PWM1_CHOPCFG,PWM1 Chop Configuration Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VALUE ,Gate chopping divisor"
|
|
sif cpuis("ADSPCM40*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PWM1_DT,PWM1 Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PWM1_SYNC_WID,PWM1 Sync Pulse Width Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Sync pulse width"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PWM1_TM0,PWM1 Timer 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PWM1_TM1,PWM1 Timer 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PWM1_TM2,PWM1 Timer 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PWM1_TM3,PWM1 Timer 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWM1_TM4,PWM1 Timer 4 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
tree "Channels Registers"
|
|
group.long 0x38++0x03 "Channel A"
|
|
line.long 0x00 "PWM1_DLYA,PWM1 Channel A Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel A delay value"
|
|
group.long 0x48++0x23
|
|
line.long 0x00 "PWM1_ACTL,PWM1 Channel A Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM1_AH0,PWM1 Channel A-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM1_AH1,PWM1 Channel A-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM1_AH0_HP,PWM1 Channel A-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM1_AH1_HP,PWM1 Channel A-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM1_AL0,PWM1 Channel A-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM1_AL1,PWM1 Channel A-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM1_AL0_HP,PWM1 Channel A-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM1_AL1_HP,PWM1 Channel A-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "PWM1_AH_DUTY0,PWM1 Channel A-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM1_AH_DUTY1,PWM1 Channel A-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM1_AL_DUTY0,PWM1 Channel A-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM1_AL_DUTY1,PWM1 Channel A-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PWM1_CHA_DT,PWM1 Channel A Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x3C++0x03 "Channel B"
|
|
line.long 0x00 "PWM1_DLYB,PWM1 Channel B Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel B delay value"
|
|
group.long 0x6C++0x23
|
|
line.long 0x00 "PWM1_BCTL,PWM1 Channel B Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM1_BH0,PWM1 Channel B-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM1_BH1,PWM1 Channel B-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM1_BH0_HP,PWM1 Channel B-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM1_BH1_HP,PWM1 Channel B-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM1_BL0,PWM1 Channel B-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM1_BL1,PWM1 Channel B-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM1_BL0_HP,PWM1 Channel B-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM1_BL1_HP,PWM1 Channel B-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xE8++0x0F
|
|
line.long 0x00 "PWM1_BH_DUTY0,PWM1 Channel B-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM1_BH_DUTY1,PWM1 Channel B-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM1_BL_DUTY0,PWM1 Channel B-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM1_BL_DUTY1,PWM1 Channel B-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PWM1_CHB_DT,PWM1 Channel B Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x40++0x03 "Channel C"
|
|
line.long 0x00 "PWM1_DLYC,PWM1 Channel C Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel C delay value"
|
|
group.long 0x90++0x23
|
|
line.long 0x00 "PWM1_CCTL,PWM1 Channel C Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM1_CH0,PWM1 Channel C-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM1_CH1,PWM1 Channel C-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM1_CH0_HP,PWM1 Channel C-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM1_CH1_HP,PWM1 Channel C-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM1_CL0,PWM1 Channel C-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM1_CL1,PWM1 Channel C-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM1_CL0_HP,PWM1 Channel C-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM1_CL1_HP,PWM1 Channel C-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xF8++0x0F
|
|
line.long 0x00 "PWM1_CH_DUTY0,PWM1 Channel C-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM1_CH_DUTY1,PWM1 Channel C-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM1_CL_DUTY0,PWM1 Channel C-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM1_CL_DUTY1,PWM1 Channel C-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PWM1_CHC_DT,PWM1 Channel C Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x44++0x03 "Channel D"
|
|
line.long 0x00 "PWM1_DLYD,PWM1 Channel D Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel D delay value"
|
|
group.long 0xB4++0x23
|
|
line.long 0x00 "PWM1_DCTL,PWM1 Channel D Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM1_DH0,PWM1 Channel D-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM1_DH1,PWM1 Channel D-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM1_DH0_HP,PWM1 Channel D-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM1_DH1_HP,PWM1 Channel D-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM1_DL0,PWM1 Channel D-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM1_DL1,PWM1 Channel D-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM1_DL0_HP,PWM1 Channel D-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM1_DL1_HP,PWM1 Channel D-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "PWM1_DH_DUTY0,PWM1 Channel D-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM1_DH_DUTY1,PWM1 Channel D-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM1_DL_DUTY0,PWM1 Channel D-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM1_DL_DUTY1,PWM1 Channel D-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PWM1_CHD_DT,PWM1 Channel D Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM2"
|
|
base ad:0x40008800
|
|
width 19.
|
|
if (((per.l(ad:0x40008800))&0x01)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PWM2_CTL,PWM2 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWM2_CHANCFG,PWM2 Channel Configuration Register"
|
|
bitfld.long 0x04 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x04 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x04 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x04 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x04 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x04 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x04 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x04 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x04 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM2_CTL,PWM2 Control Register"
|
|
bitfld.long 0x00 18.--20. " INTSYNCREF ,Timer reference for internal sync" "PWMTMR0,PWMTMR1,PWMTMR2,PWMTMR3,PWMTMR4,?..."
|
|
bitfld.long 0x00 17. " EXTSYNCSEL ,External sync select" "Asynchronous,Synchronous"
|
|
rbitfld.long 0x00 16. " EXTSYNC ,External sync" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADEN ,Asymmetric Dead-time enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " DLYDEN ,Enable delay counter for channel D" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DLYCEN ,Enable delay counter for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " DLYBEN ,Enable delay counter for channel B" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DLYAEN ,Enable delay counter for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DUEN ,Double update mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " SWTRIP ,Software trip" "Not force,Force"
|
|
bitfld.long 0x00 1. " EMURUN ,Output behaviour during emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GLOBEN ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PWM2_CHANCFG,PWM2 Channel Configuration Register"
|
|
bitfld.long 0x00 30. " ENCHOPDL ,Channel D gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " POLDL ,Channel D low side polarity" "Low,High"
|
|
bitfld.long 0x00 28. " ENHPDH ,Channel D heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENCHOPDH ,Channel D gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " POLDH ,Channel D high side polarity" "Low,High"
|
|
bitfld.long 0x00 25. " MODELSD ,Channel D mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 24. " REFTMRD ,Channel D timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 22. " ENCHOPCL ,Channel C gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " POLCL ,Channel C low side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENHPCH ,Channel C heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCHOPCH ,Channel C gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " POLCH ,Channel C high side polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODELSC ,Channel C mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 16. " REFTMRC ,Channel C timer reference" "PWMTMR0,PWMTMR1"
|
|
bitfld.long 0x00 14. " ENCHOPBL ,Channel B gate chopping enable low side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POLBL ,Channel B low side polarity" "Low,High"
|
|
bitfld.long 0x00 12. " ENHPBH ,Channel B heightened-precision enable for high side output" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENCHOPBH ,Channel B gate chopping enable high side" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POLBH ,Channel B high side polarity" "Low,High"
|
|
bitfld.long 0x00 9. " MODELSB ,Channel B mode of low side output" "Inverted,Independent"
|
|
bitfld.long 0x00 8. " REFTMRB ,Channel B timer reference" "PWMTMR0,PWMTMR1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENCHOPAL ,Channel A gate chopping enable low side" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " POLAL ,Channel A low side polarity" "Low,High"
|
|
bitfld.long 0x00 4. " ENHPAH ,Channel A heightened-precision enable for high side output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENCHOPAH ,Channel A gate chopping enable high side" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " POLAH ,Channel A high side polarity" "Low,High"
|
|
bitfld.long 0x00 1. " MODELSA ,Channel A mode of low side output" "Inverted,Independent"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REFTMRA ,Channel A timer reference" "PWMTMR0,PWMTMR1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWM2_TRIPCFG,PWM2 Trip Configuration Register"
|
|
bitfld.long 0x00 27. " MODE1D ,Mode of TRIP1 for channel D" "Fault trip,Self restart"
|
|
bitfld.long 0x00 26. " EN1D ,Enable TRIP1 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MODE0D ,Mode of TRIP0 for channel D" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 24. " EN0D ,Enable TRIP0 as a trip source for channel D" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MODE1C ,Mode of TRIP1 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 18. " EN1C ,Enable TRIP1 as a trip source for channel C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MODE0C ,Mode of TRIP0 for channel C" "Fault trip,Self restart"
|
|
bitfld.long 0x00 16. " EN0C ,Enable TRIP0 as a trip source for channel C" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MODE1B ,Mode of TRIP1 for channel B" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN1B ,Enable TRIP1 as a trip source for channel B" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE0B ,Mode of TRIP0 for channel B" "Fault trip,Self restart"
|
|
bitfld.long 0x00 8. " EN0B ,Enable TRIP0 as a trip source for channel B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MODE1A ,Mode of TRIP1 for channel A" "Fault trip,Self restart"
|
|
bitfld.long 0x00 2. " EN1A ,Enable TRIP1 as a trip source for channel A" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MODE0A ,Mode of TRIP0 for channel A" "Fault trip,Self restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN0A ,Enable TRIP0 as a trip source for channel A" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "PWM2_STAT,PWM2 Status Register"
|
|
rbitfld.long 0x00 31. " HPRDY ,Heightened-Precision ready status" "Not ready,Ready"
|
|
sif cpuis("ADSPCM40*")
|
|
textline " "
|
|
eventfld.long 0x00 30. " EMU ,Emulator Status" "0,1"
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
else
|
|
eventfld.long 0x00 28. " TMR4PHASE ,PWMTMR4 phase status" "First,Second"
|
|
eventfld.long 0x00 27. " TMR3PHASE ,PWMTMR3 phase status" "First,Second"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 26. " TMR2PHASE ,PWMTMR2 phase status" "First,Second"
|
|
eventfld.long 0x00 25. " TMR1PHASE ,PWMTMR1 phase status" "First,Second"
|
|
eventfld.long 0x00 24. " TMR0PHASE ,PWMTMR0 phase status" "First,Second"
|
|
textline " "
|
|
eventfld.long 0x00 20. " TMR4PER ,PWMTMR4 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 19. " TMR3PER ,PWMTMR3 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 18. " TMR2PER ,PWMTMR2 period boundary status" "Not reached,Reached"
|
|
textline " "
|
|
eventfld.long 0x00 17. " TMR1PER ,PWMTMR1 period boundary status" "Not reached,Reached"
|
|
eventfld.long 0x00 16. " TMR0PER ,PWMTMR0 period boundary status" "Not reached,Reached"
|
|
rbitfld.long 0x00 11. " SRTRIPD ,Self-Restart trip status for channel D" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 10. " FLTTRIPD ,Fault trip status for channel D" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 9. " SRTRIPC ,Self-Restart trip status for channel C" "Not tripped,Tripped"
|
|
eventfld.long 0x00 8. " FLTTRIPC ,Fault trip status for channel C" "Not tripped,Tripped"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SRTRIPB ,Self-Restart trip status for channel B" "Not tripped,Tripped"
|
|
eventfld.long 0x00 6. " FLTTRIPB ,Fault trip status for channel B" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 5. " SRTRIPA ,Self-Restart trip status for channel A" "Not tripped,Tripped"
|
|
textline " "
|
|
eventfld.long 0x00 4. " FLTTRIPA ,Fault trip status for channel A" "Not tripped,Tripped"
|
|
rbitfld.long 0x00 3. " RAWTRIP1 ,Raw trip 1 status" "Low,High"
|
|
rbitfld.long 0x00 2. " RAWTRIP0 ,Raw trip 0 status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRIP1 ,Status bit set when TRIP1 is active low" "Not tripped,Tripped"
|
|
eventfld.long 0x00 0. " TRIP0 ,Status bit set when TRIP0 is active low" "Not tripped,Tripped"
|
|
line.long 0x04 "PWM2_IMSK,PWM2 Interrupt Mask Register"
|
|
bitfld.long 0x04 20. " TMR4PER ,PWMTMR4 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 19. " TMR3PER ,PWMTMR3 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " TMR2PER ,PWMTMR2 period boundary interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TMR1PER ,PWMTMR1 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " TMR0PER ,PWMTMR0 period boundary interrupt enable" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " TRIP1 ,TRIP1 interrupt enable" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIP0 ,TRIP0 interrupt enable" "Masked,Unmasked"
|
|
line.long 0x08 "PWM2_ILAT,PWM2 Interrupt Latch Register"
|
|
eventfld.long 0x08 20. " TMR4PER ,PWMTMR4 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " TMR3PER ,PWMTMR3 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " TMR2PER ,PWMTMR2 period latched interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " TMR1PER ,PWMTMR1 period latched interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " TMR0PER ,PWMTMR0 period boundary interrupt latched status" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " TRIP1 ,TRIP1 interrupt latched status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " TRIP0 ,TRIP0 interrupt latched status" "No interrupt,Interrupt"
|
|
line.long 0x0C "PWM2_CHOPCFG,PWM2 Chop Configuration Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " VALUE ,Gate chopping divisor"
|
|
sif cpuis("ADSPCM40*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PWM2_DT,PWM2 Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PWM2_SYNC_WID,PWM2 Sync Pulse Width Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Sync pulse width"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PWM2_TM0,PWM2 Timer 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PWM2_TM1,PWM2 Timer 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PWM2_TM2,PWM2 Timer 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PWM2_TM3,PWM2 Timer 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWM2_TM4,PWM2 Timer 4 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Timer PWMTMR$5 period value"
|
|
tree "Channels Registers"
|
|
group.long 0x38++0x03 "Channel A"
|
|
line.long 0x00 "PWM2_DLYA,PWM2 Channel A Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel A delay value"
|
|
group.long 0x48++0x23
|
|
line.long 0x00 "PWM2_ACTL,PWM2 Channel A Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM2_AH0,PWM2 Channel A-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM2_AH1,PWM2 Channel A-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM2_AH0_HP,PWM2 Channel A-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM2_AH1_HP,PWM2 Channel A-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM2_AL0,PWM2 Channel A-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM2_AL1,PWM2 Channel A-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM2_AL0_HP,PWM2 Channel A-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM2_AL1_HP,PWM2 Channel A-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "PWM2_AH_DUTY0,PWM2 Channel A-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM2_AH_DUTY1,PWM2 Channel A-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM2_AL_DUTY0,PWM2 Channel A-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM2_AL_DUTY1,PWM2 Channel A-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PWM2_CHA_DT,PWM2 Channel A Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x3C++0x03 "Channel B"
|
|
line.long 0x00 "PWM2_DLYB,PWM2 Channel B Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel B delay value"
|
|
group.long 0x6C++0x23
|
|
line.long 0x00 "PWM2_BCTL,PWM2 Channel B Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM2_BH0,PWM2 Channel B-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM2_BH1,PWM2 Channel B-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM2_BH0_HP,PWM2 Channel B-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM2_BH1_HP,PWM2 Channel B-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM2_BL0,PWM2 Channel B-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM2_BL1,PWM2 Channel B-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM2_BL0_HP,PWM2 Channel B-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM2_BL1_HP,PWM2 Channel B-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xE8++0x0F
|
|
line.long 0x00 "PWM2_BH_DUTY0,PWM2 Channel B-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM2_BH_DUTY1,PWM2 Channel B-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM2_BL_DUTY0,PWM2 Channel B-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM2_BL_DUTY1,PWM2 Channel B-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PWM2_CHB_DT,PWM2 Channel B Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x40++0x03 "Channel C"
|
|
line.long 0x00 "PWM2_DLYC,PWM2 Channel C Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel C delay value"
|
|
group.long 0x90++0x23
|
|
line.long 0x00 "PWM2_CCTL,PWM2 Channel C Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM2_CH0,PWM2 Channel C-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM2_CH1,PWM2 Channel C-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM2_CH0_HP,PWM2 Channel C-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM2_CH1_HP,PWM2 Channel C-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM2_CL0,PWM2 Channel C-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM2_CL1,PWM2 Channel C-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM2_CL0_HP,PWM2 Channel C-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM2_CL1_HP,PWM2 Channel C-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0xF8++0x0F
|
|
line.long 0x00 "PWM2_CH_DUTY0,PWM2 Channel C-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM2_CH_DUTY1,PWM2 Channel C-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM2_CL_DUTY0,PWM2 Channel C-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM2_CL_DUTY1,PWM2 Channel C-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PWM2_CHC_DT,PWM2 Channel C Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
group.long 0x44++0x03 "Channel D"
|
|
line.long 0x00 "PWM2_DLYD,PWM2 Channel D Delay Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Channel D delay value"
|
|
group.long 0xB4++0x23
|
|
line.long 0x00 "PWM2_DCTL,PWM2 Channel D Control Register"
|
|
bitfld.long 0x00 10.--11. " PULSEMODELO ,Low side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 8.--9. " PULSEMODEHI ,High side output pulse position" "Symmetrical,Asymmetrical,Left half,Right half"
|
|
bitfld.long 0x00 2. " XOVR ,High-low crossover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISLO ,Channel low side output disable" "No,Yes"
|
|
bitfld.long 0x00 0. " DISHI ,Channel high side output disable" "No,Yes"
|
|
line.long 0x04 "PWM2_DH0,PWM2 Channel D-High Duty-0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x08 "PWM2_DH1,PWM2 Channel D-High Duty-1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x0C "PWM2_DH0_HP,PWM2 Channel D-High Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x0C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x10 "PWM2_DH1_HP,PWM2 Channel D-High Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x10 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x14 "PWM2_DL0,PWM2 Channel D-Low Duty-0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " DUTY ,Duty cycle asserted count"
|
|
line.long 0x18 "PWM2_DL1,PWM2 Channel D-Low Duty-1 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " DUTY ,Duty cycle De-Asserted count"
|
|
line.long 0x1C "PWM2_DL0_HP,PWM2 Channel D-Low Heightened-Precision Duty-0 Register"
|
|
bitfld.long 0x1C 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x20 "PWM2_DL1_HP,PWM2 Channel D-Low Heightened-Precision Duty-1 Register"
|
|
bitfld.long 0x20 6.--7. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "PWM2_DH_DUTY0,PWM2 Channel D-High Full Duty0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x00 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x04 "PWM2_DH_DUTY1,PWM2 Channel D-High Full Duty1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x04 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x08 "PWM2_DL_DUTY0,PWM2 Channel D-Low Full Duty0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x08 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
line.long 0x0C "PWM2_DL_DUTY1,PWM2 Channel D-Low Full Duty1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DUTY ,Coarse duty value"
|
|
bitfld.long 0x0C 14.--15. " ENHDIV ,Enhanced precision divider bits" "0,1,2,3"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PWM2_CHD_DT,PWM2 Channel D Dead-time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " VALUE ,Dead-time value"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x40004004
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART0_CTL,UART0 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART0_STAT,UART0 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART0_SCR,UART0 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x40004004))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART0_CLK,UART0 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART0_CLK,UART0 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART0_IMSK_set/clr,UART0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART0_RBR,UART0 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART0_THR,UART0 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART0_THR,UART0 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART0_TAIP,UART0 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART0_TSR,UART0 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART0_RSR,UART0 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART0_TXCNT,UART0 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART0_RXCNT,UART0 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40003004
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART1_CTL,UART1 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART1_STAT,UART1 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART1_SCR,UART1 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x40003004))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART1_CLK,UART1 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART1_CLK,UART1 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART1_IMSK_set/clr,UART1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART1_RBR,UART1 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART1_THR,UART1 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART1_THR,UART1 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART1_TAIP,UART1 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART1_TSR,UART1 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART1_RSR,UART1 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART1_TXCNT,UART1 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART1_RXCNT,UART1 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x40003404
|
|
width 23.
|
|
group.long 0x0++0x0B
|
|
line.long 0x00 "UART2_CTL,UART2 Control Register"
|
|
bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1"
|
|
bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "2,4"
|
|
bitfld.long 0x00 28. " ACTS ,Automatic CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARTS ,Automatic RTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XOFF ,Transmitter off" "No,Yes"
|
|
bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "De-asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "Low,High"
|
|
bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "Low CTS/RTS,High CTS/RTS"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SB ,Set Break" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "Not forced,Forced"
|
|
bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STP ,Sticky Parity" "Not forced,Forced"
|
|
bitfld.long 0x00 15. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 14. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1"
|
|
bitfld.long 0x00 12. " STB ,Stop Bits" "1,2"
|
|
bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "UART,MDB,IrDA SIR,?..."
|
|
bitfld.long 0x00 1. " LOOP_EN ,Loop-back Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable UART" "Disabled,Enabled"
|
|
line.long 0x04 "UART2_STAT,UART2 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "Less than 4,At least 4"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not clear,Clear"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x04 17. " RFCS ,Receive FIFO Count Status" "<,=>"
|
|
rbitfld.long 0x04 16. " CTS ,Clear to Send" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " SCTS ,Sticky CTS" "Not transitioned,Transitioned"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " RO ,Reception On-going" "Waiting,In progress"
|
|
bitfld.long 0x04 10. " ADDR ,Address Bit Status" "Low,High"
|
|
eventfld.long 0x04 9. " ASTKY ,Address Sticky" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 8. " TFI ,Transmission Finished Indicator" "Not finished,Finished"
|
|
rbitfld.long 0x04 7. " TEMT ,TSR and THR Empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 5. " THRE ,Transmit Hold Register Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x04 4. " BI ,Break Indicator" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " FE ,Framing Error" "No error,Error"
|
|
eventfld.long 0x04 2. " PE ,Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " OE ,Overrun Error" "No error,Error"
|
|
rbitfld.long 0x04 0. " DR ,Data Ready" "No new data,New data"
|
|
line.long 0x08 "UART2_SCR,UART2 Scratch Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Stored 8-bit Data"
|
|
if (((per.l(ad:0x40003404))&0x30)==0x20)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART2_CLK,UART2 Clock Rate Register"
|
|
rbitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UART2_CLK,UART2 Clock Rate Register"
|
|
bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "/16,/1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UART2_IMSK_set/clr,UART2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EAWI ,Enable Address Word Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ELSI ,Enable Line Status Interrupt Mask Status" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "Masked,Unmasked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "Masked,Unmasked"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "UART2_RBR,UART2 Receive Buffer Register"
|
|
in
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART2_THR,UART2 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
else
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UART2_THR,UART2 Transmit Hold Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART2_TAIP,UART2 Transmit Address/Insert Pulse Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "UART2_TSR,UART2 Transmit Shift Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "UART2_RSR,UART2 Receive Shift Register"
|
|
in
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "UART2_TXCNT,UART2 Transmit Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
line.long 0x04 "UART2_RXCNT,UART2 Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,16-bit Counter Value"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "TWI (Two-Wire Interface)"
|
|
base ad:0x40000C00
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TWI0_CLKDIV,TWI0 SCL Clock Divider Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL clock high periods"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL clock low periods"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TWI0_CTL,TWI0 Control Register"
|
|
bitfld.word 0x00 9. " SCCB ,SCCB compatibility" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EN ,Enable module" "Disabled,Enabled"
|
|
hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK prescale value"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TWI0_SLVCTL,TWI0 Slave Mode Control Register"
|
|
bitfld.word 0x00 4. " GEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " NAK ,Not acknowledge" "ACK,NAK"
|
|
bitfld.word 0x00 2. " TDVAL ,Transmit data valid for slave" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,Enable slave mode" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "TWI0_SLVSTAT,TWI0 Slave Mode Status Register"
|
|
bitfld.word 0x00 1. " GCALL ,General call" "Not general,General"
|
|
bitfld.word 0x00 0. " DIR ,Transfer direction for slave" "Receive,Transmit"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TWI0_SLVADDR,TWI0 Slave Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave mode address"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "TWI0_MSTRCTL,TWI0 Master Mode Control Registers"
|
|
bitfld.word 0x00 15. " SCLOVR ,Serial clock override" "No override,Override"
|
|
bitfld.word 0x00 14. " SDAOVR ,Serial data override" "No override,Override"
|
|
hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data transfer count"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RSTART ,Repeat start" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STOP ,Issue stop condition" "Normal,Issue"
|
|
bitfld.word 0x00 3. " FAST ,Fast mode" "Standard,Fast"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DIR ,Transfer direction for master" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " EN ,Enable master mode" "Disabled,Enabled"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TWI0_MSTRSTAT,TWI0 Master Mode Status Register"
|
|
rbitfld.word 0x00 8. " BUSBUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.word 0x00 7. " SCLSEN ,Serial clock sense" "Inactive One,Actice Zero"
|
|
rbitfld.word 0x00 6. " SDASEN ,Serial data sense" "Inactive One,Actice 0Zero"
|
|
textline " "
|
|
eventfld.word 0x00 5. " BUFWRERR ,Buffer write error" "No error,Error"
|
|
eventfld.word 0x00 4. " BUFRDERR ,Buffer read error" "No error,Error"
|
|
eventfld.word 0x00 3. " DNAK ,Data not acknowledged" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ANAK ,Address not acknowledged" "Not occurred,Occurred"
|
|
eventfld.word 0x00 1. " LOSTARB ,Lost arbitration" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " MPROG ,Master transfer in progress" "Idle,In progress"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TWI0_MSTRADDR,TWI0 Master Mode Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master mode address"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TWI0_ISTAT,TWI0 Interrupt Status Register"
|
|
eventfld.word 0x00 15. " SCLI ,Serial clock interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 14. " SDAI ,Serial data interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RXSERV ,Rx FIFO service" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 6. " TXSERV ,Tx FIFO service" "Low,High"
|
|
eventfld.word 0x00 5. " MERR ,Master transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " MCOMP ,Master transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 3. " SOVF ,Slave overflow" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " SERR ,Slave transfer error" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 1. " SCOMP ,Slave transfer complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 0. " SINIT ,Slave transfer initiated" "No interrupt,Interrupt"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TWI0_IMSK,TWI0 Interrupt Mask Register"
|
|
bitfld.word 0x00 15. " SCLI ,Serial clock interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 14. " SDAI ,Serial data interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RXSERV ,Rx FIFO service interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TXSERV ,Tx FIFO service interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 5. " MERR ,Master transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " MCOMP ,Master transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SOVF ,Slave overflow interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " SERR ,Slave transfer error interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 1. " SCOMP ,Slave transfer complete interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SINIT ,Slave transfer initiated interrupt mask" "Masked,Unmasked"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TWI0_FIFOCTL,TWI0 FIFO Control Register"
|
|
bitfld.word 0x00 3. " RXILEN ,Rx buffer interrupt Llngth" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 2. " TXILEN ,Tx buffer interrupt length" "1 or 2 bytes,2 bytes"
|
|
bitfld.word 0x00 1. " RXFLUSH ,Rx buffer flush" "Normal,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXFLUSH ,Tx buffer flush" "Normal,Flushed"
|
|
hgroup.word 0x2C++0x01
|
|
hide.word 0x00 "TWI0_FIFOSTAT,TWI0 FIFO Status Register"
|
|
in
|
|
wgroup.word 0x80++0x01
|
|
line.word 0x00 "TWI0_TXDATA8,TWI0 Tx Data Single-Byte Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value"
|
|
wgroup.word 0x84++0x01
|
|
line.word 0x00 "TWI0_TXDATA16,TWI0 Tx Data Double-Byte Register"
|
|
hgroup.word 0x88++0x01
|
|
hide.word 0x00 "TWI0_RXDATA8,TWI0 Rx Data Single-Byte Register"
|
|
in
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "TWI0_RXDATA16,TWI0 Rx Data Double-Byte Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN0"
|
|
base ad:0x40002200
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CAN0_MC1,CAN0 Mailbox Configuration 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 enable/disable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CAN0_MD1,CAN0 Mailbox Direction 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit/receive" "Transmit,Receive"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CAN0_TRS1_SET/CLR,CAN0 Transmission Request Set/Clear 1 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB15 ,Mailbox 15 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB14 ,Mailbox 14 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB13 ,Mailbox 13 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB12 ,Mailbox 12 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB11 ,Mailbox 11 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB10 ,Mailbox 10 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB09 ,Mailbox 9 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB08 ,Mailbox 8 transmit request" "Not requested,Requested"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CAN0_TA1,CAN0 Transmission Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit acknowledge" "Failure,Success"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "CAN0_AA1,CAN0 Abort Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CAN0_RMP1,CAN0 Receive Message Pending 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 message pending" "Not pending,Pending"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CAN0_RML1,CAN0 Receive Message Lost 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 message lost" "Not lost,Lost"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CAN0_MBTIF1,CAN0 Mailbox Transmit Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CAN0_MBRIF1,CAN0 Mailbox Receive Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CAN0_MBIM1,CAN0 Mailbox Interrupt Mask 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CAN0_RFH1,CAN0 Remote Frame Handling 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CAN0_OPSS1,CAN0 Overwrite Protection/Single Shot Transmission 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 overwrite protection enable" "Disabled,Enabled"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CAN0_MC2,CAN0 Mailbox Configuration 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 enable/disable" "Disabled,Enabled"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CAN0_MD2,CAN0 Mailbox Direction 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit/receive" "Transmit,Receive"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CAN0_TRS2_SET/CLR,CAN0 Transmission Request Set/Clear 2 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB31 ,Mailbox 31 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB30 ,Mailbox 30 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB29 ,Mailbox 29 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB28 ,Mailbox 28 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB27 ,Mailbox 27 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB26 ,Mailbox 26 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB25 ,Mailbox 25 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB24 ,Mailbox 24 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x00 7. 0x04 7. " MB23 ,Mailbox 23 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x04 6. " MB22 ,Mailbox 22 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x04 5. " MB21 ,Mailbox 21 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 4. 0x00 4. 0x04 4. " MB20 ,Mailbox 20 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x00 3. 0x04 3. " MB19 ,Mailbox 19 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 2. 0x00 2. 0x04 2. " MB18 ,Mailbox 18 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x04 1. " MB17 ,Mailbox 17 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 0. 0x00 0. 0x04 0. " MB16 ,Mailbox 16 transmit request" "Not requested,Requested"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CAN0_TA2,CAN0 Transmission Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit acknowledge" "Failure,Success"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CAN0_AA2,CAN0 Abort Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "CAN0_RMP2,CAN0 Receive Message Pending 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 message pending" "Not pending,Pending"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "CAN0_RML2,CAN0 Receive Message Lost 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 message lost" "Not lost,Lost"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CAN0_MBTIF2,CAN0 Mailbox Transmit Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "CAN0_MBRIF2,CAN0 Mailbox Receive Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "CAN0_MBIM2,CAN0 Mailbox Interrupt Mask 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "CAN0_RFH2,CAN0 Remote Frame Handling 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "CAN0_OPSS2,CAN0 Overwrite Protection/Single Shot Transmission 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "CAN0_CLK,CAN0 Clock Register"
|
|
hexmask.word 0x00 0.--9. 1. " BRP ,Bit rate prescaler"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "CAN0_TIMING,CAN0 Timing Register"
|
|
bitfld.word 0x00 8.--9. " SJW ,Synchronization jump width" "1,2,3,4"
|
|
bitfld.word 0x00 7. " SAM ,Sampling" "Normal sampling,Over sampling"
|
|
bitfld.word 0x00 4.--6. " TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "CAN0_DBG,CAN0 Debug Register"
|
|
bitfld.word 0x00 15. " CDE ,CAN debug mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MRB ,Mode read back" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MAA ,Mode auto acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DIL ,Disable internal loop" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DTO ,Disable tx output pin" "No,Yes"
|
|
bitfld.word 0x00 1. " DRI ,Disable receive input pin" "No,Yes"
|
|
bitfld.word 0x00 0. " DEC ,Disable transmit and receive error counters" "No,Yes"
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "CAN0_STAT,CAN0 Status Register"
|
|
bitfld.word 0x00 15. " REC ,Receive mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " TRM ,Transmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--12. " MBPTR ,Mailbox pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CCA ,CAN configuration mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CSA ,CAN suspend mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EBO ,CAN error bus off mode (TXECNT)" "Below 256,Above bus off limit"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EP ,CAN error passive mode (TXECNT and/or RXECNT)" "Below 128,Above EP level"
|
|
bitfld.word 0x00 1. " WR ,CAN receive warning flag" "Below limit,At limit"
|
|
bitfld.word 0x00 0. " WT ,CAN transmit warning flag" "Below limit,At limit"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "CAN0_CEC,CAN0 Error Counter Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TXECNT ,Transmit error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXECNT ,Receive error counter"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "CAN0_GIS,CAN0 Global CAN Interrupt Status Register"
|
|
eventfld.word 0x00 10. " ADIS ,Access denied interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 8. " UCEIS ,Universal counter exceeded interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RMLIS ,Receive message lost interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 6. " AAIS ,Abort acknowledge interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 5. " UIAIS ,Unimplemented address interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " WUIS ,Wake up interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 3. " BOIS ,Bus off interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " EPIS ,Error passive interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 1. " EWRIS ,Error warning receive interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 0. " EWTIS ,Error warning transmit interrupt status" "No interrupt,Interrupt"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "CAN0_GIM,CAN0 Global CAN Interrupt Mask Register"
|
|
bitfld.word 0x00 10. " ADIM ,Access denied interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 8. " UCEIM ,Universal counter exceeded interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RMLIM ,Receive message lost interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 6. " AAIM ,Abort acknowledge interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIM ,Unimplemented address interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " WUIM ,Wake up interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 3. " BOIM ,Bus off interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " EPIM ,Error passive interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIM ,Error warning receive interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 0. " EWTIM ,Error warning transmit interrupt mask" "Masked,Unmasked"
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "CAN0_GIF,CAN0 Global CAN Interrupt Flag Register"
|
|
bitfld.word 0x00 10. " ADIF ,Access denied interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 8. " UCEIF ,Universal counter exceeded interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 7. " RMLIF ,Receive message lost interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 6. " AAIF ,Abort acknowledge interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIF ,Unimplemented address interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 4. " WUIF ,Wake up interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 3. " BOIF ,Bus off interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 2. " EPIF ,Error passive interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIF ,Error warning receive interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 0. " EWTIF ,Error warning transmit interrupt flag" "Not latched,Latched"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "CAN0_CTL,CAN0 Master Control Register"
|
|
bitfld.word 0x00 7. " CCR ,CAN configuration mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " CSR ,CAN suspend mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " SMR ,Sleep mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " WBA ,Wake up on CAN bus activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABO ,Auto bus on" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DNM ,Device net mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SRS ,Software reset" "No effect,Reset"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "CAN0_INT,CAN0 Interrupt Pending Register"
|
|
rbitfld.word 0x00 7. " CANRX ,Serial input from transceiver" "Dominant,Recessive"
|
|
rbitfld.word 0x00 6. " CANTX ,Serial input to transceiver" "Dominant,Recessive"
|
|
bitfld.word 0x00 3. " SMACK ,Sleep mode acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " GIRQ ,Global CAN interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 1. " MBTIRQ ,Mailbox transmit interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 0. " MBRIRQ ,Mailbox receive interrupt output" "No flag set,One or more flag set"
|
|
group.word 0xAC++0x01
|
|
line.word 0x00 "CAN0_MBTD,CAN0 Temporary Mailbox Disable Register"
|
|
bitfld.word 0x00 7. " TDR ,Temporary disable request" "No,Yes"
|
|
rbitfld.word 0x00 6. " TDA ,Temporary disable acknowledge" "No,Yes"
|
|
bitfld.word 0x00 0.--4. " TDPTR ,Temporary disable pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "CAN0_EWR,CAN0 Error Counter Warning Level Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " EWLTEC ,Transmit error warning limit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EWLREC ,Receive error warning limit"
|
|
group.word 0xB4++0x01
|
|
line.word 0x00 "CAN0_ESR,CAN0 Error Status Register"
|
|
eventfld.word 0x00 7. " FER ,Form error" "No error,Error"
|
|
eventfld.word 0x00 6. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.word 0x00 5. " SAO ,Stuck at dominant" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 4. " CRCE ,CRC error" "No error,Error"
|
|
eventfld.word 0x00 3. " SER ,Stuff bit error" "No error,Error"
|
|
eventfld.word 0x00 2. " ACKE ,Acknowledge error" "No error,Error"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "CAN0_UCCNT,CAN0 Universal Counter Register"
|
|
group.word 0xC8++0x01
|
|
line.word 0x00 "CAN0_UCRC,CAN0 Universal Counter Reload/Capture Register"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x02)
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN0_UCCNF,CAN0 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Reload"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
else
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN0_UCCNF,CAN0 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Clear"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
endif
|
|
textline " "
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAN0_AM00L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM00H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAN0_AM01L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x108+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM01H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAN0_AM02L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM02H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAN0_AM03L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x118+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM03H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAN0_AM04L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM04H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAN0_AM05L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x128+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM05H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAN0_AM06L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM06H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAN0_AM07L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x138+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM07H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x140++0x01
|
|
line.word 0x00 "CAN0_AM08L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x140+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM08H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "CAN0_AM09L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x148+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM09H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x150++0x01
|
|
line.word 0x00 "CAN0_AM10L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x150+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM10H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x158++0x01
|
|
line.word 0x00 "CAN0_AM11L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x158+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM11H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x160++0x01
|
|
line.word 0x00 "CAN0_AM12L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x160+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM12H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x168++0x01
|
|
line.word 0x00 "CAN0_AM13L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x168+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM13H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x170++0x01
|
|
line.word 0x00 "CAN0_AM14L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x170+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM14H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x178++0x01
|
|
line.word 0x00 "CAN0_AM15L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x178+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM15H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "CAN0_AM16L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x180+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM16H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "CAN0_AM17L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x188+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM17H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "CAN0_AM18L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x190+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM18H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x198++0x01
|
|
line.word 0x00 "CAN0_AM19L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x198+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM19H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A0++0x01
|
|
line.word 0x00 "CAN0_AM20L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM20H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A8++0x01
|
|
line.word 0x00 "CAN0_AM21L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1A8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM21H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B0++0x01
|
|
line.word 0x00 "CAN0_AM22L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1B0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM22H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B8++0x01
|
|
line.word 0x00 "CAN0_AM23L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1B8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM23H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "CAN0_AM24L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM24H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C8++0x01
|
|
line.word 0x00 "CAN0_AM25L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1C8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM25H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "CAN0_AM26L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1D0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM26H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D8++0x01
|
|
line.word 0x00 "CAN0_AM27L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1D8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM27H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "CAN0_AM28L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM28H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "CAN0_AM29L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1E8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM29H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F0++0x01
|
|
line.word 0x00 "CAN0_AM30L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1F0+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM30H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F8++0x01
|
|
line.word 0x00 "CAN0_AM31L,CAN0 Acceptance Mask (L) Register"
|
|
group.word (0x1F8+0x04)++0x01
|
|
line.word 0x00 "CAN0_AM31H,CAN0 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x200+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x200+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB00_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x200+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB00_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB00_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x200+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB00_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x200+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB00_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB00_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x220++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x220+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x220+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x220+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB01_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x220+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB01_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB01_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x220+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB01_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x220+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB01_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB01_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x240++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x240+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x240+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x240+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB02_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x240+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB02_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB02_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x240+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB02_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x240+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB02_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB02_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x260++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x260+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x260+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB03_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x260+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB03_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB03_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x260+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB03_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x260+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB03_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB03_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x280++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x280+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x280+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x280+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB04_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x280+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB04_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB04_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x280+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB04_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x280+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB04_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB04_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2A0++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB05_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB05_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB05_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB05_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB05_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB05_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2C0++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB06_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB06_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB06_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB06_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB06_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB06_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2E0++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB07_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB07_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB07_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB07_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB07_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB07_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x300+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x300+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x300+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB08_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x300+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB08_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB08_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x300+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB08_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x300+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB08_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB08_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x320++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x320+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x320+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB09_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x320+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB09_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB09_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x320+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB09_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x320+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB09_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB09_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x340++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x340+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x340+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x340+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB10_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x340+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB10_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB10_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x340+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB10_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x340+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB10_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB10_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x360+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x360+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x360+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB11_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x360+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB11_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB11_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x360+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB11_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x360+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB11_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB11_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x380++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x380+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x380+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x380+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB12_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x380+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB12_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB12_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x380+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB12_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x380+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB12_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB12_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3A0++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB13_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB13_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB13_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB13_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB13_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB13_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3C0++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB14_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB14_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB14_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB14_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB14_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB14_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3E0++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB15_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB15_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB15_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB15_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB15_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB15_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x400++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x400+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x400+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x400+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB16_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x400+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB16_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x400+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB16_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x400+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB16_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x400+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB16_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x400+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB16_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x420++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x420+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x420+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x420+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB17_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x420+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB17_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x420+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB17_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x420+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB17_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x420+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB17_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x420+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB17_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x440++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x440+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x440+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x440+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB18_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x440+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB18_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x440+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB18_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x440+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB18_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x440+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB18_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x440+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB18_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x460+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x460+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x460+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB19_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x460+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB19_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x460+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB19_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x460+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB19_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x460+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB19_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x460+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB19_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x480+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x480+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x480+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB20_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x480+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB20_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x480+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB20_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x480+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB20_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x480+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB20_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x480+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB20_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4A0++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB21_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB21_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB21_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB21_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB21_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB21_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4C0++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB22_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB22_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB22_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB22_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB22_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB22_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4E0++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB23_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB23_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x4E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB23_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB23_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB23_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x4E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB23_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x500++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x500+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x500+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x500+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB24_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x500+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB24_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x500+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB24_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x500+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB24_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x500+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB24_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x500+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB24_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x520++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x520+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x520+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x520+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB25_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x520+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB25_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x520+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB25_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x520+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB25_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x520+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB25_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x520+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB25_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x540++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x540+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x540+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x540+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB26_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x540+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB26_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x540+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB26_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x540+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB26_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x540+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB26_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x540+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB26_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x560++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x560+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x560+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x560+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB27_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x560+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB27_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x560+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB27_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x560+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB27_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x560+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB27_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x560+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB27_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x580++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x580+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x580+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x580+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB28_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x580+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB28_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x580+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB28_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x580+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB28_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x580+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB28_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x580+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB28_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5A0++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5A0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5A0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5A0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB29_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5A0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB29_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5A0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB29_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5A0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB29_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5A0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB29_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5A0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB29_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5C0++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5C0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5C0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5C0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB30_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5C0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB30_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5C0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB30_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5C0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB30_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5C0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB30_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5C0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB30_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5E0++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA0,CAN0 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5E0+0x04)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA1,CAN0 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5E0+0x08)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA2,CAN0 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5E0+0x0C)++0x01
|
|
line.word 0x00 "CAN0_MB31_DATA3,CAN0 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5E0+0x10)++0x01
|
|
line.word 0x00 "CAN0_MB31_LENGTH,CAN0 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002200+0xCC))&0x0F)==0x01)
|
|
group.word (0x5E0+0x14)++0x01
|
|
line.word 0x00 "CAN0_MB31_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5E0+0x14)++0x01
|
|
hide.word 0x00 "CAN0_MB31_TIMESTAMP,CAN0 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5E0+0x18)++0x01
|
|
line.word 0x00 "CAN0_MB31_ID0,CAN0 Mailbox ID 0 Register"
|
|
group.word (0x5E0+0x1C)++0x01
|
|
line.word 0x00 "CAN0_MB31_ID1,CAN0 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x40002A00
|
|
width 21.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CAN1_MC1,CAN1 Mailbox Configuration 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 enable/disable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CAN1_MD1,CAN1 Mailbox Direction 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit/receive" "Transmit,Receive"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CAN1_TRS1_SET/CLR,CAN1 Transmission Request Set/Clear 1 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB15 ,Mailbox 15 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB14 ,Mailbox 14 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB13 ,Mailbox 13 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB12 ,Mailbox 12 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB11 ,Mailbox 11 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB10 ,Mailbox 10 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB09 ,Mailbox 9 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB08 ,Mailbox 8 transmit request" "Not requested,Requested"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CAN1_TA1,CAN1 Transmission Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit acknowledge" "Failure,Success"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "CAN1_AA1,CAN1 Abort Acknowledge 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CAN1_RMP1,CAN1 Receive Message Pending 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 message pending" "Not pending,Pending"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "CAN1_RML1,CAN1 Receive Message Lost 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 message lost" "Not lost,Lost"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CAN1_MBTIF1,CAN1 Mailbox Transmit Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CAN1_MBRIF1,CAN1 Mailbox Receive Interrupt Flag 1 Register"
|
|
eventfld.word 0x00 15. " MB15 ,Mailbox 15 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB14 ,Mailbox 14 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB13 ,Mailbox 13 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB12 ,Mailbox 12 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB11 ,Mailbox 11 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB10 ,Mailbox 10 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB09 ,Mailbox 9 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB08 ,Mailbox 8 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB07 ,Mailbox 7 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB06 ,Mailbox 6 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB05 ,Mailbox 5 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB04 ,Mailbox 4 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB03 ,Mailbox 3 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB02 ,Mailbox 2 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB01 ,Mailbox 1 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB00 ,Mailbox 0 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "CAN1_MBIM1,CAN1 Mailbox Interrupt Mask 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "CAN1_RFH1,CAN1 Remote Frame Handling 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "CAN1_OPSS1,CAN1 Overwrite Protection/Single Shot Transmission 1 Register"
|
|
bitfld.word 0x00 15. " MB15 ,Mailbox 15 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB14 ,Mailbox 14 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB13 ,Mailbox 13 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB12 ,Mailbox 12 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB11 ,Mailbox 11 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB10 ,Mailbox 10 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB09 ,Mailbox 9 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB08 ,Mailbox 8 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB07 ,Mailbox 7 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB06 ,Mailbox 6 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB05 ,Mailbox 5 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB04 ,Mailbox 4 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB03 ,Mailbox 3 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB02 ,Mailbox 2 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB01 ,Mailbox 1 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB00 ,Mailbox 0 overwrite protection enable" "Disabled,Enabled"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CAN1_MC2,CAN1 Mailbox Configuration 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 enable/disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 enable/disable" "Disabled,Enabled"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "CAN1_MD2,CAN1 Mailbox Direction 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit/receive" "Transmit,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit/receive" "Transmit,Receive"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit/receive" "Transmit,Receive"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "CAN1_TRS2_SET/CLR,CAN1 Transmission Request Set/Clear 2 Register"
|
|
setclrfld.word 0x00 15. 0x00 15. 0x04 15. " MB31 ,Mailbox 31 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 14. 0x00 14. 0x04 14. " MB30 ,Mailbox 30 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 13. 0x00 13. 0x04 13. " MB29 ,Mailbox 29 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 12. 0x00 12. 0x04 12. " MB28 ,Mailbox 28 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 11. 0x00 11. 0x04 11. " MB27 ,Mailbox 27 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 10. 0x00 10. 0x04 10. " MB26 ,Mailbox 26 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 9. 0x00 9. 0x04 9. " MB25 ,Mailbox 25 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 8. 0x00 8. 0x04 8. " MB24 ,Mailbox 24 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x00 7. 0x04 7. " MB23 ,Mailbox 23 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x04 6. " MB22 ,Mailbox 22 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x04 5. " MB21 ,Mailbox 21 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 4. 0x00 4. 0x04 4. " MB20 ,Mailbox 20 transmit request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.word 0x00 3. 0x00 3. 0x04 3. " MB19 ,Mailbox 19 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 2. 0x00 2. 0x04 2. " MB18 ,Mailbox 18 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x04 1. " MB17 ,Mailbox 17 transmit request" "Not requested,Requested"
|
|
setclrfld.word 0x00 0. 0x00 0. 0x04 0. " MB16 ,Mailbox 16 transmit request" "Not requested,Requested"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "CAN1_TA2,CAN1 Transmission Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit acknowledge" "Failure,Success"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit acknowledge" "Failure,Success"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit acknowledge" "Failure,Success"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "CAN1_AA2,CAN1 Abort Acknowledge 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 abort acknowledge" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 abort acknowledge" "Not aborted,Aborted"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 abort acknowledge" "Not aborted,Aborted"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "CAN1_RMP2,CAN1 Receive Message Pending 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 message pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 message pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 message pending" "Not pending,Pending"
|
|
rgroup.word 0x5C++0x01
|
|
line.word 0x00 "CAN1_RML2,CAN1 Receive Message Lost 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 message lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 message lost" "Not lost,Lost"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 message lost" "Not lost,Lost"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "CAN1_MBTIF2,CAN1 Mailbox Transmit Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 15. " MB31 ,Mailbox 31 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 14. " MB30 ,Mailbox 30 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 13. " MB29 ,Mailbox 29 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 12. " MB28 ,Mailbox 28 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 11. " MB27 ,Mailbox 27 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 10. " MB26 ,Mailbox 26 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 9. " MB25 ,Mailbox 25 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 8. " MB24 ,Mailbox 24 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 transmit interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 transmit interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 transmit interrupt pending" "Not pending,Pending"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "CAN1_MBRIF2,CAN1 Mailbox Receive Interrupt Flag 2 Register"
|
|
eventfld.word 0x00 7. " MB23 ,Mailbox 23 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 6. " MB22 ,Mailbox 22 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 5. " MB21 ,Mailbox 21 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 4. " MB20 ,Mailbox 20 receive interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.word 0x00 3. " MB19 ,Mailbox 19 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 2. " MB18 ,Mailbox 18 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 1. " MB17 ,Mailbox 17 receive interrupt pending" "Not pending,Pending"
|
|
eventfld.word 0x00 0. " MB16 ,Mailbox 16 receive interrupt pending" "Not pending,Pending"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "CAN1_MBIM2,CAN1 Mailbox Interrupt Mask 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 transmit and receive interrupt enable" "Disabled,Enabled"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "CAN1_RFH2,CAN1 Remote Frame Handling 2 Register"
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 remote frame handling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 remote frame handling enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 remote frame handling enable" "Disabled,Enabled"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "CAN1_OPSS2,CAN1 Overwrite Protection/Single Shot Transmission 2 Register"
|
|
bitfld.word 0x00 15. " MB31 ,Mailbox 31 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " MB30 ,Mailbox 30 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MB29 ,Mailbox 29 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " MB28 ,Mailbox 28 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MB27 ,Mailbox 27 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MB26 ,Mailbox 26 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MB25 ,Mailbox 25 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " MB24 ,Mailbox 24 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MB23 ,Mailbox 23 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MB22 ,Mailbox 22 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MB21 ,Mailbox 21 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MB20 ,Mailbox 20 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MB19 ,Mailbox 19 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MB18 ,Mailbox 18 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MB17 ,Mailbox 17 overwrite protection enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MB16 ,Mailbox 16 overwrite protection enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "CAN1_CLK,CAN1 Clock Register"
|
|
hexmask.word 0x00 0.--9. 1. " BRP ,Bit rate prescaler"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "CAN1_TIMING,CAN1 Timing Register"
|
|
bitfld.word 0x00 8.--9. " SJW ,Synchronization jump width" "1,2,3,4"
|
|
bitfld.word 0x00 7. " SAM ,Sampling" "Normal sampling,Over sampling"
|
|
bitfld.word 0x00 4.--6. " TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "CAN1_DBG,CAN1 Debug Register"
|
|
bitfld.word 0x00 15. " CDE ,CAN debug mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MRB ,Mode read back" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MAA ,Mode auto acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DIL ,Disable internal loop" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DTO ,Disable tx output pin" "No,Yes"
|
|
bitfld.word 0x00 1. " DRI ,Disable receive input pin" "No,Yes"
|
|
bitfld.word 0x00 0. " DEC ,Disable transmit and receive error counters" "No,Yes"
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "CAN1_STAT,CAN1 Status Register"
|
|
bitfld.word 0x00 15. " REC ,Receive mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " TRM ,Transmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--12. " MBPTR ,Mailbox pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CCA ,CAN configuration mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CSA ,CAN suspend mode acknowledge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EBO ,CAN error bus off mode (TXECNT)" "Below 256,Above bus off limit"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EP ,CAN error passive mode (TXECNT and/or RXECNT)" "Below 128,Above EP level"
|
|
bitfld.word 0x00 1. " WR ,CAN receive warning flag" "Below limit,At limit"
|
|
bitfld.word 0x00 0. " WT ,CAN transmit warning flag" "Below limit,At limit"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "CAN1_CEC,CAN1 Error Counter Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TXECNT ,Transmit error counter"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXECNT ,Receive error counter"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "CAN1_GIS,CAN1 Global CAN Interrupt Status Register"
|
|
eventfld.word 0x00 10. " ADIS ,Access denied interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 8. " UCEIS ,Universal counter exceeded interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 7. " RMLIS ,Receive message lost interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 6. " AAIS ,Abort acknowledge interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 5. " UIAIS ,Unimplemented address interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 4. " WUIS ,Wake up interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 3. " BOIS ,Bus off interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " EPIS ,Error passive interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 1. " EWRIS ,Error warning receive interrupt status" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 0. " EWTIS ,Error warning transmit interrupt status" "No interrupt,Interrupt"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "CAN1_GIM,CAN1 Global CAN Interrupt Mask Register"
|
|
bitfld.word 0x00 10. " ADIM ,Access denied interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 8. " UCEIM ,Universal counter exceeded interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 7. " RMLIM ,Receive message lost interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 6. " AAIM ,Abort acknowledge interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIM ,Unimplemented address interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 4. " WUIM ,Wake up interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 3. " BOIM ,Bus off interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 2. " EPIM ,Error passive interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIM ,Error warning receive interrupt mask" "Masked,Unmasked"
|
|
bitfld.word 0x00 0. " EWTIM ,Error warning transmit interrupt mask" "Masked,Unmasked"
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "CAN1_GIF,CAN1 Global CAN Interrupt Flag Register"
|
|
bitfld.word 0x00 10. " ADIF ,Access denied interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 8. " UCEIF ,Universal counter exceeded interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 7. " RMLIF ,Receive message lost interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 6. " AAIF ,Abort acknowledge interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UIAIF ,Unimplemented address interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 4. " WUIF ,Wake up interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 3. " BOIF ,Bus off interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 2. " EPIF ,Error passive interrupt flag" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EWRIF ,Error warning receive interrupt flag" "Not latched,Latched"
|
|
bitfld.word 0x00 0. " EWTIF ,Error warning transmit interrupt flag" "Not latched,Latched"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "CAN1_CTL,CAN1 Master Control Register"
|
|
bitfld.word 0x00 7. " CCR ,CAN configuration mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 6. " CSR ,CAN suspend mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 5. " SMR ,Sleep mode request" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " WBA ,Wake up on CAN bus activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABO ,Auto bus on" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DNM ,Device net mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " SRS ,Software reset" "No effect,Reset"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "CAN1_INT,CAN1 Interrupt Pending Register"
|
|
rbitfld.word 0x00 7. " CANRX ,Serial input from transceiver" "Dominant,Recessive"
|
|
rbitfld.word 0x00 6. " CANTX ,Serial input to transceiver" "Dominant,Recessive"
|
|
bitfld.word 0x00 3. " SMACK ,Sleep mode acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " GIRQ ,Global CAN interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 1. " MBTIRQ ,Mailbox transmit interrupt output" "No flag set,One or more flag set"
|
|
bitfld.word 0x00 0. " MBRIRQ ,Mailbox receive interrupt output" "No flag set,One or more flag set"
|
|
group.word 0xAC++0x01
|
|
line.word 0x00 "CAN1_MBTD,CAN1 Temporary Mailbox Disable Register"
|
|
bitfld.word 0x00 7. " TDR ,Temporary disable request" "No,Yes"
|
|
rbitfld.word 0x00 6. " TDA ,Temporary disable acknowledge" "No,Yes"
|
|
bitfld.word 0x00 0.--4. " TDPTR ,Temporary disable pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "CAN1_EWR,CAN1 Error Counter Warning Level Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " EWLTEC ,Transmit error warning limit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EWLREC ,Receive error warning limit"
|
|
group.word 0xB4++0x01
|
|
line.word 0x00 "CAN1_ESR,CAN1 Error Status Register"
|
|
eventfld.word 0x00 7. " FER ,Form error" "No error,Error"
|
|
eventfld.word 0x00 6. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.word 0x00 5. " SAO ,Stuck at dominant" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 4. " CRCE ,CRC error" "No error,Error"
|
|
eventfld.word 0x00 3. " SER ,Stuff bit error" "No error,Error"
|
|
eventfld.word 0x00 2. " ACKE ,Acknowledge error" "No error,Error"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "CAN1_UCCNT,CAN1 Universal Counter Register"
|
|
group.word 0xC8++0x01
|
|
line.word 0x00 "CAN1_UCRC,CAN1 Universal Counter Reload/Capture Register"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x02)
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN1_UCCNF,CAN1 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Reload"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
else
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "CAN1_UCCNF,CAN1 Universal Counter Configuration Mode Register"
|
|
bitfld.word 0x00 7. " UCE ,Universal counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " UCCT ,Universal counter CAN trigger" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " UCRC ,Universal counter reload/clear" "No effect,Clear"
|
|
bitfld.word 0x00 0.--3. " UCCNF ,Universal counter configuration" ",Time stamp mode,Watchdog mode,Auto-transmit mode,,,Count error frames,Count overload frames,Count arbitration lost,Count aborted transmissions,Count successful transmissions,Count rejected receive messages,Count receive message lost,Count successful receptions,Count stored receptions,Count valid messages"
|
|
endif
|
|
textline " "
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "CAN1_AM00L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM00H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "CAN1_AM01L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x108+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM01H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x110++0x01
|
|
line.word 0x00 "CAN1_AM02L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM02H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "CAN1_AM03L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x118+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM03H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "CAN1_AM04L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM04H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "CAN1_AM05L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x128+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM05H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "CAN1_AM06L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM06H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "CAN1_AM07L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x138+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM07H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x140++0x01
|
|
line.word 0x00 "CAN1_AM08L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x140+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM08H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "CAN1_AM09L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x148+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM09H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x150++0x01
|
|
line.word 0x00 "CAN1_AM10L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x150+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM10H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x158++0x01
|
|
line.word 0x00 "CAN1_AM11L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x158+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM11H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x160++0x01
|
|
line.word 0x00 "CAN1_AM12L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x160+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM12H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x168++0x01
|
|
line.word 0x00 "CAN1_AM13L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x168+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM13H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x170++0x01
|
|
line.word 0x00 "CAN1_AM14L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x170+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM14H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x178++0x01
|
|
line.word 0x00 "CAN1_AM15L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x178+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM15H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x180++0x01
|
|
line.word 0x00 "CAN1_AM16L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x180+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM16H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x188++0x01
|
|
line.word 0x00 "CAN1_AM17L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x188+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM17H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x190++0x01
|
|
line.word 0x00 "CAN1_AM18L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x190+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM18H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x198++0x01
|
|
line.word 0x00 "CAN1_AM19L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x198+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM19H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A0++0x01
|
|
line.word 0x00 "CAN1_AM20L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM20H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1A8++0x01
|
|
line.word 0x00 "CAN1_AM21L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1A8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM21H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B0++0x01
|
|
line.word 0x00 "CAN1_AM22L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1B0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM22H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1B8++0x01
|
|
line.word 0x00 "CAN1_AM23L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1B8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM23H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "CAN1_AM24L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM24H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1C8++0x01
|
|
line.word 0x00 "CAN1_AM25L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1C8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM25H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "CAN1_AM26L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1D0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM26H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1D8++0x01
|
|
line.word 0x00 "CAN1_AM27L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1D8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM27H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "CAN1_AM28L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM28H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "CAN1_AM29L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1E8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM29H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F0++0x01
|
|
line.word 0x00 "CAN1_AM30L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1F0+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM30H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x1F8++0x01
|
|
line.word 0x00 "CAN1_AM31L,CAN1 Acceptance Mask (L) Register"
|
|
group.word (0x1F8+0x04)++0x01
|
|
line.word 0x00 "CAN1_AM31H,CAN1 Acceptance Mask (H) Register"
|
|
bitfld.word 0x00 15. " FDF ,Filter on delay field" "Data field mask,High bits of EXTID"
|
|
bitfld.word 0x00 14. " FMD ,Full mask data" "0,1"
|
|
bitfld.word 0x00 13. " AMIDE ,Acceptance mask identifier extension" "Disabled,Enabled"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x200+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x200+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB00_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x200+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB00_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x200+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB00_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x200+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB00_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x200+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB00_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x200+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB00_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x220++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x220+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x220+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x220+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB01_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x220+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB01_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x220+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB01_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x220+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB01_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x220+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB01_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x220+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB01_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x240++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x240+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x240+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x240+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB02_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x240+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB02_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x240+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB02_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x240+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB02_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x240+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB02_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x240+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB02_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x260++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x260+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x260+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB03_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x260+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB03_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x260+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB03_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x260+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB03_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x260+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB03_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x260+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB03_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x280++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x280+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x280+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x280+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB04_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x280+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB04_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x280+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB04_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x280+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB04_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x280+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB04_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x280+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB04_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2A0++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB05_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB05_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB05_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB05_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB05_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB05_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2C0++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB06_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB06_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB06_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB06_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB06_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB06_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x2E0++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x2E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x2E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x2E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB07_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x2E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB07_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x2E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB07_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x2E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB07_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x2E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB07_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x2E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB07_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x300+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x300+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x300+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB08_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x300+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB08_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x300+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB08_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x300+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB08_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x300+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB08_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x300+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB08_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x320++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x320+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x320+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB09_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x320+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB09_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x320+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB09_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x320+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB09_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x320+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB09_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x320+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB09_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x340++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x340+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x340+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x340+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB10_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x340+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB10_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x340+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB10_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x340+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB10_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x340+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB10_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x340+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB10_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x360+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x360+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x360+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB11_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x360+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB11_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x360+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB11_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x360+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB11_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x360+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB11_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x360+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB11_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x380++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x380+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x380+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x380+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB12_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x380+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB12_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x380+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB12_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x380+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB12_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x380+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB12_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x380+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB12_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3A0++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB13_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB13_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB13_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB13_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB13_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB13_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3C0++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB14_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB14_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB14_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB14_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB14_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB14_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x3E0++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x3E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x3E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x3E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB15_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x3E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB15_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x3E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB15_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x3E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB15_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x3E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB15_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x3E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB15_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x400++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x400+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x400+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x400+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB16_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x400+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB16_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x400+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB16_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x400+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB16_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x400+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB16_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x400+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB16_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x420++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x420+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x420+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x420+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB17_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x420+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB17_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x420+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB17_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x420+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB17_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x420+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB17_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x420+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB17_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x440++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x440+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x440+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x440+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB18_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x440+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB18_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x440+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB18_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x440+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB18_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x440+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB18_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x440+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB18_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x460+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x460+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x460+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB19_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x460+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB19_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x460+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB19_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x460+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB19_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x460+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB19_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x460+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB19_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x480+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x480+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x480+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB20_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x480+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB20_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x480+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB20_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x480+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB20_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x480+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB20_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x480+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB20_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4A0++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB21_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB21_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB21_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB21_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB21_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB21_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4C0++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB22_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB22_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB22_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB22_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB22_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB22_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x4E0++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x4E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x4E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x4E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB23_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x4E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB23_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x4E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB23_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x4E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB23_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x4E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB23_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x4E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB23_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x500++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x500+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x500+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x500+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB24_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x500+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB24_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x500+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB24_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x500+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB24_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x500+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB24_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x500+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB24_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x520++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x520+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x520+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x520+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB25_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x520+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB25_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x520+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB25_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x520+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB25_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x520+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB25_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x520+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB25_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x540++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x540+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x540+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x540+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB26_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x540+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB26_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x540+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB26_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x540+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB26_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x540+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB26_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x540+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB26_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x560++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x560+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x560+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x560+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB27_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x560+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB27_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x560+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB27_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x560+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB27_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x560+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB27_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x560+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB27_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x580++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x580+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x580+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x580+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB28_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x580+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB28_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x580+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB28_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x580+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB28_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x580+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB28_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x580+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB28_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5A0++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5A0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5A0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5A0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB29_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5A0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB29_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5A0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB29_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5A0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB29_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5A0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB29_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5A0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB29_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5C0++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5C0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5C0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5C0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB30_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5C0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB30_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5C0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB30_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5C0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB30_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5C0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB30_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5C0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB30_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
textline " "
|
|
group.word 0x5E0++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA0,CAN1 Mailbox Word 0 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB6 ,Data field byte 6"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB7 ,Data field byte 7"
|
|
group.word (0x5E0+0x04)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA1,CAN1 Mailbox Word 1 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB4 ,Data field byte 4"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB5 ,Data field byte 5"
|
|
group.word (0x5E0+0x08)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA2,CAN1 Mailbox Word 2 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB2 ,Data field byte 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB3 ,Data field byte 3"
|
|
group.word (0x5E0+0x0C)++0x01
|
|
line.word 0x00 "CAN1_MB31_DATA3,CAN1 Mailbox Word 3 Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " DFB0 ,Data field byte 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DFB1 ,Data field byte 1"
|
|
group.word (0x5E0+0x10)++0x01
|
|
line.word 0x00 "CAN1_MB31_LENGTH,CAN1 Mailbox Length Register"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x40002A00+0xCC))&0x0F)==0x01)
|
|
group.word (0x5E0+0x14)++0x01
|
|
line.word 0x00 "CAN1_MB31_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
else
|
|
hgroup.word (0x5E0+0x14)++0x01
|
|
hide.word 0x00 "CAN1_MB31_TIMESTAMP,CAN1 Mailbox Timestamp Register"
|
|
endif
|
|
group.word (0x5E0+0x18)++0x01
|
|
line.word 0x00 "CAN1_MB31_ID0,CAN1 Mailbox ID 0 Register"
|
|
group.word (0x5E0+0x1C)++0x01
|
|
line.word 0x00 "CAN1_MB31_ID1,CAN1 Mailbox ID 1 Register"
|
|
bitfld.word 0x00 15. " AME ,Acceptance mask enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.word 0x00 13. " IDE ,Identifier extension" "0,1"
|
|
hexmask.word 0x00 2.--12. 1. " BASEID ,Base identifier"
|
|
bitfld.word 0x00 0.--1. " EXTID ,Extended identifier" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()!="ADSPCM402F")&&(cpu()!="ADSPCM403F")
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x40030000
|
|
width 18.
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "USB0_FADDR,USB0 Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,Function address value"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "USB0_POWER,USB0 Power And Device Control Register"
|
|
bitfld.byte 0x00 7. " ISOUPDT ,ISO update enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SOFTCONN ,Soft connect/disconnect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " HSEN ,High speed mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode" "Full speed,High speed"
|
|
rbitfld.byte 0x00 3. " RESET ,Reset USB" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSEN ,SUSPENDM output enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "USB0_FADDR,USB0 Function Address Register"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "USB0_POWER,USB0 Power And Device Control Register"
|
|
bitfld.byte 0x00 5. " HSEN ,High speed mode enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 4. " HSMODE ,High speed mode" "Full speed,High speed"
|
|
bitfld.byte 0x00 3. " RESET ,Reset USB" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RESUME ,Resume mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSEN ,SUSPENDM output enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "USB0_INTRTX,USB0 Transmit Interrupt Register"
|
|
in
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "USB0_INTRRX,USB0 Receive Interrupt Register"
|
|
in
|
|
group.word 0x06++0x03
|
|
line.word 0x00 "USB0_INTRTXE,USB0 Transmit Interrupt Enable Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " EP11 ,End point 11 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " EP10 ,End point 10 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " EP9 ,End point 9 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " EP8 ,End point 8 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " EP7 ,End point 7 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " EP6 ,End point 6 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EP5 ,End point 5 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " EP4 ,End point 4 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " EP3 ,End point 3 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " EP2 ,End point 2 TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EP1 ,End point 1 TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EP0 ,End point 0 TX interrupt enable" "Disabled,Enabled"
|
|
line.word 0x02 "USB0_INTRRXE,USB0 Receive Interrupt Enable Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x02 11. " EP11 ,End point 11 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " EP10 ,End point 10 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 9. " EP9 ,End point 9 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 8. " EP8 ,End point 8 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " EP7 ,End point 7 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " EP6 ,End point 6 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 5. " EP5 ,End point 5 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " EP4 ,End point 4 RX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 3. " EP3 ,End point 3 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " EP2 ,End point 2 RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " EP1 ,End point 1 RX interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "USB0_IRQ,USB0 Common Interrupts Register"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "USB0_IEN,USB0 Common Interrupts Enable Register"
|
|
bitfld.byte 0x00 7. " VBUSERR ,VBUS threshold indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SESSREQ ,Session request indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DISCON ,Disconnect indicator interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CON ,Connection indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SOF ,Start-of-frame indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RSTBABBLE ,Reset/babble indicator interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RESUME ,Resume indicator interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SUSPEND ,Suspend indicator interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "USB0_FRAME,USB0 Frame Number Register"
|
|
hexmask.word 0x00 0.--10. 1. " VALUE ,Frame number value"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "USB0_INDEX,USB0 Index Register"
|
|
bitfld.byte 0x00 0.--3. " EP ,Endpoint index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "USB0_TESTMODE,USB0 Testmode Register"
|
|
bitfld.byte 0x00 6. " FIFOACCESS ,FIFO access" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.byte 0x00 3. " TESTPACKET ,Test_packet mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TESTK ,Test_k mode" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 2. " TESTK ,Test_k mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 1. " TESTJ ,Test_j mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TESTSE0NAK ,Test SE0 NAK" "Disabled,Enabled"
|
|
width 26.
|
|
tree "EPI Registers"
|
|
group.word 0x10++0x01 "Endpoint 0"
|
|
line.word 0x00 "USB0_EPI0_TXMAXP,USB0 EP0 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.w(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0I_CSR0_H,USB0 EP0 Configuration And Status (host) Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " DISPING ,Disable ping" "No,Yes"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " NAKTO ,NAK timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status packet" "No request,Request"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "No request,Request"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TOERR ,Timeout error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,Setup packet" "No request,Request"
|
|
bitfld.word 0x00 2. " RXSTALL ,RX stall" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x10+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0I_CSR0_P,USB0 EP0 Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 7. " SSETUPEND ,Service setup end" "No effect,Clear SETUPEND"
|
|
bitfld.word 0x00 6. " SPKTRDY ,Service RX packet ready" "No effect,Clear RXPKTRDY"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send stall" "No effect,Send"
|
|
rbitfld.word 0x00 4. " SETUPEND ,Setup end" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,Sent stall" "0,1"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x10+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXMAXP,USB0 EP0 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x10+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXCSR_H,USB0 EP0 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x10+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI0_RXCSR_P,USB0 EP0 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x10+0x08)++0x01
|
|
line.word 0x00 "USB0_EP0I_CNT0,USB0 EP0 Number Of Received Bytes Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RXCNT ,RX byte count value"
|
|
group.byte (0x10+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP0I_TYPE0,USB0 EP0 Connection Type Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
group.byte (0x10+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP0I_NAKLIMIT0,USB0 EP0 NAK Limit Register"
|
|
bitfld.byte 0x00 0.--4. " VALUE ,Endpoint 0 timeout value (in frames)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x10+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x10+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
endif
|
|
group.byte (0x10+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI0_RXINTERVAL,USB0 EP0 Receive Polling Interval Register"
|
|
group.byte (0x10+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP0I_CFGDATA0,USB0 EP0 Configuration Information Register"
|
|
rbitfld.byte 0x00 7. " MPRX ,Multi-Packet aggregate for RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " MPTX ,Multi-Packet split for TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " BIGEND ,Big endian data" "Little endian,Big endian"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HBRX ,High bandwidth RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " HBTX ,High bandwidth TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " DYNFIFO ,Dynamic FIFO size enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SOFTCON ,Soft connect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " UTMIWID ,UTMI data width" "8 bit,16 bit"
|
|
group.word 0x20++0x01 "Endpoint 1"
|
|
line.word 0x00 "USB0_EPI1_TXMAXP,USB0 EP1 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x20+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI1_TXCSR_H,USB0 EP1 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x20+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI1_TXCSR_P,USB0 EP1 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x20+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXMAXP,USB0 EP1 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x20+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCSR_H,USB0 EP1 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x20+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCSR_P,USB0 EP1 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x20+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI1_RXCNT,USB0 EP1 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x20+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x20+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
endif
|
|
group.byte (0x20+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI1_TXINTERVAL,USB0 EP1 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x20+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x20+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
endif
|
|
group.byte (0x20+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI1_RXINTERVAL,USB0 EP1 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x20+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP1 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x30++0x01 "Endpoint 2"
|
|
line.word 0x00 "USB0_EPI2_TXMAXP,USB0 EP2 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x30+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI2_TXCSR_H,USB0 EP2 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x30+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI2_TXCSR_P,USB0 EP2 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x30+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXMAXP,USB0 EP2 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x30+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCSR_H,USB0 EP2 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x30+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCSR_P,USB0 EP2 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x30+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI2_RXCNT,USB0 EP2 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x30+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x30+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
endif
|
|
group.byte (0x30+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI2_TXINTERVAL,USB0 EP2 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x30+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x30+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
endif
|
|
group.byte (0x30+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI2_RXINTERVAL,USB0 EP2 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x30+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP2 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x40++0x01 "Endpoint 3"
|
|
line.word 0x00 "USB0_EPI3_TXMAXP,USB0 EP3 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI3_TXCSR_H,USB0 EP3 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x40+0x02)++0x01
|
|
line.word 0x00 "USB0_EPI3_TXCSR_P,USB0 EP3 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x40+0x04)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXMAXP,USB0 EP3 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x40+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCSR_H,USB0 EP3 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x40+0x06)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCSR_P,USB0 EP3 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
rgroup.word (0x40+0x08)++0x01
|
|
line.word 0x00 "USB0_EPI3_RXCNT,USB0 EP3 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x40+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EPI3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x40+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EPI3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
endif
|
|
group.byte (0x40+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EPI3_TXINTERVAL,USB0 EP3 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x40+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EPI3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x40+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EPI3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
endif
|
|
group.byte (0x40+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EPI3_RXINTERVAL,USB0 EP3 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x40+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EPI_FIFOSZ,USB0 EP3 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "FIFO Registers"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "USB0_FIFO0,USB0 FIFO Register"
|
|
in
|
|
tree.end
|
|
width 20.
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "USB0_DEV_CTL,USB0 Device Control Register"
|
|
rbitfld.byte 0x00 7. " BDEVICE ,A or B devices indicator" "A device,B device"
|
|
rbitfld.byte 0x00 6. " FSDEV ,Full or High-Speed indicator" "Not detected,Detected"
|
|
rbitfld.byte 0x00 5. " LSDEV ,Low-Speed indicator" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 3.--4. " VBUS ,VBUS level indicator" "<sessionend,Sessionend-avalid,Avalid-vbusvalid,>vbusvalid"
|
|
rbitfld.byte 0x00 2. " HOSTMODE ,Host mode indicator" "Peripheral,Host"
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host negotiation request" "Completed,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session indicator" "Not detected,Detected"
|
|
else
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "USB0_DEV_CTL,USB0 Device Control Register"
|
|
rbitfld.byte 0x00 7. " BDEVICE ,A or B devices indicator" "A device,B device"
|
|
rbitfld.byte 0x00 3.--4. " VBUS ,VBUS level indicator" "<sessionend,Sessionend-avalid,Avalid-vbusvalid,>vbusvalid"
|
|
rbitfld.byte 0x00 2. " HOSTMODE ,Host mode indicator" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Host negotiation request" "Completed,Requested"
|
|
bitfld.byte 0x00 0. " SESSION ,Session indicator" "Not detected,Detected"
|
|
endif
|
|
sif !cpuis("ADSPCM40*")
|
|
if (((per.b(ad:0x40030000+0x62))&0x10)==0x00)
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "USB0_TXFIFOSZ,USB0 Transmit FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
else
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "USB0_TXFIFOSZ,USB0 Transmit FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "16,32,64,128,256,512,1024,2048,4096,8192,?..."
|
|
endif
|
|
if (((per.b(ad:0x40030000+0x63))&0x10)==0x00)
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "USB0_RXFIFOSZ,USB0 Receive FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
else
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "USB0_RXFIFOSZ,USB0 Receive FIFO Size Register"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size" "16,32,64,128,256,512,1024,2048,4096,8192,?..."
|
|
endif
|
|
group.word 0x64++0x03
|
|
line.word 0x00 "USB0_TXFIFOADDR,USB0 Transmit FIFO Address Register"
|
|
hexmask.word 0x00 0.--12. 1. " VALUE ,TX FIFO start address"
|
|
line.word 0x02 "USB0_RXFIFOADDR,USB0 Receive FIFO Address Register"
|
|
hexmask.word 0x02 0.--12. 1. " VALUE ,RX FIFO start address"
|
|
endif
|
|
rgroup.byte 0x78++0x01
|
|
line.byte 0x00 "USB0_EPINFO,USB0 Endpoint Information Register"
|
|
bitfld.byte 0x00 4.--7. " RXEP ,RX endpoints" ",1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.byte 0x00 0.--3. " TXEP ,TX endpoints" ",1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.byte 0x01 "USB0_RAMINFO,USB0 RAM Information Register"
|
|
bitfld.byte 0x01 4.--7. " DMACHANS ,DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " RAMBITS ,RAM address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x7A++0x01
|
|
line.byte 0x00 "USB0_LINKINFO,USB0 Link Information Register"
|
|
bitfld.byte 0x00 4.--7. " WTCON ,Wait for connect/disconnect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WTID ,Wait from ID Pull-up" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "USB0_VPLEN,USB0 VBUS Pulse Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "USB0_HS_EOF1,USB0 High-Speed EOF 1 Register"
|
|
endif
|
|
group.byte 0x7A++0x02
|
|
line.byte 0x00 "USB0_FS_EOF1,USB0 Full-Speed EOF 1 Register"
|
|
line.byte 0x01 "USB0_LS_EOF1,USB0 Low-Speed EOF 1 Register"
|
|
line.byte 0x02 "USB0_SOFT_RST,USB0 Software Reset Register"
|
|
bitfld.byte 0x02 1. " RSTX ,Reset USB XCLK domain" "No effect,Reset"
|
|
bitfld.byte 0x02 0. " RST ,Reset USB CLK domain" "No effect,Reset"
|
|
width 25.
|
|
tree "MP Registers"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "USB0_MP0_TXFUNCADDR,USB0 MP0 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x80+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP0_TXHUBADDR,USB0 MP0 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP0_TXHUBPORT,USB0 MP0 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x80++0x00
|
|
hide.byte 0x00 "USB0_MP0_TXFUNCADDR,USB0 MP0 Transmit Function Address Register"
|
|
hgroup.byte (0x80+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP0_TXHUBADDR,USB0 MP0 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP0_TXHUBPORT,USB0 MP0 Transmit Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "USB0_MP1_TXFUNCADDR,USB0 MP1 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x88+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP1_TXHUBADDR,USB0 MP1 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP1_TXHUBPORT,USB0 MP1 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x88+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP1_RXFUNCADDR,USB0 MP1 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x88+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP1_RXHUBADDR,USB0 MP1 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP1_RXHUBPORT,USB0 MP1 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x88++0x00
|
|
hide.byte 0x00 "USB0_MP1_TXFUNCADDR,USB0 MP1 Transmit Function Address Register"
|
|
hgroup.byte (0x88+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP1_TXHUBADDR,USB0 MP1 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP1_TXHUBPORT,USB0 MP1 Transmit Hub Port Register"
|
|
hgroup.byte (0x88+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP1_RXFUNCADDR,USB0 MP1 Receive Function Address Register"
|
|
hgroup.byte (0x88+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP1_RXHUBADDR,USB0 MP1 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP1_RXHUBPORT,USB0 MP1 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "USB0_MP2_TXFUNCADDR,USB0 MP2 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x90+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP2_TXHUBADDR,USB0 MP2 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP2_TXHUBPORT,USB0 MP2 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x90+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP2_RXFUNCADDR,USB0 MP2 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x90+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP2_RXHUBADDR,USB0 MP2 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP2_RXHUBPORT,USB0 MP2 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "USB0_MP2_TXFUNCADDR,USB0 MP2 Transmit Function Address Register"
|
|
hgroup.byte (0x90+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP2_TXHUBADDR,USB0 MP2 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP2_TXHUBPORT,USB0 MP2 Transmit Hub Port Register"
|
|
hgroup.byte (0x90+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP2_RXFUNCADDR,USB0 MP2 Receive Function Address Register"
|
|
hgroup.byte (0x90+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP2_RXHUBADDR,USB0 MP2 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP2_RXHUBPORT,USB0 MP2 Receive Hub Port Register"
|
|
endif
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "USB0_MP3_TXFUNCADDR,USB0 MP3 Transmit Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,TX function address value"
|
|
group.byte (0x98+0x02)++0x01
|
|
line.byte 0x00 "USB0_MP3_TXHUBADDR,USB0 MP3 Transmit Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP3_TXHUBPORT,USB0 MP3 Transmit Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
group.byte (0x98+0x04)++0x00
|
|
line.byte 0x00 "USB0_MP3_RXFUNCADDR,USB0 MP3 Receive Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,RX function address value"
|
|
group.byte (0x98+0x06)++0x01
|
|
line.byte 0x00 "USB0_MP3_RXHUBADDR,USB0 MP3 Receive Hub Address Register"
|
|
bitfld.byte 0x00 7. " MULTTRANS ,Multiple transaction translators" "Single,Multiple"
|
|
hexmask.byte 0x00 0.--6. 1. " ADDR ,Hub address value"
|
|
line.byte 0x01 "USB0_MP3_RXHUBPORT,USB0 MP3 Receive Hub Port Register"
|
|
hexmask.byte 0x01 0.--6. 1. " VALUE ,Hub port value"
|
|
else
|
|
hgroup.byte 0x98++0x00
|
|
hide.byte 0x00 "USB0_MP3_TXFUNCADDR,USB0 MP3 Transmit Function Address Register"
|
|
hgroup.byte (0x98+0x02)++0x01
|
|
hide.byte 0x00 "USB0_MP3_TXHUBADDR,USB0 MP3 Transmit Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP3_TXHUBPORT,USB0 MP3 Transmit Hub Port Register"
|
|
hgroup.byte (0x98+0x04)++0x00
|
|
hide.byte 0x00 "USB0_MP3_RXFUNCADDR,USB0 MP3 Receive Function Address Register"
|
|
hgroup.byte (0x98+0x06)++0x01
|
|
hide.byte 0x00 "USB0_MP3_RXHUBADDR,USB0 MP3 Receive Hub Address Register"
|
|
hide.byte 0x01 "USB0_MP3_RXHUBPORT,USB0 MP3 Receive Hub Port Register"
|
|
endif
|
|
tree.end
|
|
width 25.
|
|
tree "Endpoints Registers"
|
|
group.word 0x100++0x01 "Endpoint 0"
|
|
line.word 0x00 "USB0_EP0_TXMAXP,USB0 EP0 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0_CSR0_H,USB0 EP0 Configuration And Status (host) Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11. " DISPING ,Disable ping" "No,Yes"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " NAKTO ,NAK timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status packet" "No request,Request"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "No request,Request"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TOERR ,Timeout error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,Setup packet" "No request,Request"
|
|
bitfld.word 0x00 2. " RXSTALL ,RX stall" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x100+0x02)++0x01
|
|
line.word 0x00 "USB0_EP0_CSR0_P,USB0 EP0 Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 7. " SSETUPEND ,Service setup end" "No effect,Clear SETUPEND"
|
|
bitfld.word 0x00 6. " SPKTRDY ,Service RX packet ready" "No effect,Clear RXPKTRDY"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send stall" "No effect,Send"
|
|
rbitfld.word 0x00 4. " SETUPEND ,Setup end" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,Sent stall" "0,1"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x100+0x04)++0x01
|
|
line.word 0x00 "USB0_EP0_RXMAXP,USB0 EP0 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x100+0x06)++0x01
|
|
line.word 0x00 "USB0_EP0_RXCSR_H,USB0 EP0 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x100+0x06)++0x01
|
|
line.word 0x00 "USB0_EP0_RXCSR_P,USB0 EP0 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x100+0x08)++0x01
|
|
line.word 0x00 "USB0_EP0_CNT0,USB0 EP0 Number Of Received Bytes Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RXCNT ,RX byte count value"
|
|
group.byte (0x100+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP0_TYPE0,USB0 EP0 Connection Type Register"
|
|
bitfld.byte 0x00 0.--1. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
group.byte (0x100+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP0_NAKLIMIT0,USB0 EP0 NAK Limit Register"
|
|
bitfld.byte 0x00 0.--4. " VALUE ,Endpoint 0 timeout value (in frames)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x100+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x100+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP0_RXTYPE,USB0 EP0 Receive Type Register"
|
|
endif
|
|
group.byte (0x100+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP0_RXINTERVAL,USB0 EP0 Receive Polling Interval Register"
|
|
group.byte (0x100+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP0_CFGDATA0,USB0 EP0 Configuration Information Register"
|
|
rbitfld.byte 0x00 7. " MPRX ,Multi-Packet aggregate for RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " MPTX ,Multi-Packet split for TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " BIGEND ,Big endian data" "Little endian,Big endian"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " HBRX ,High bandwidth RX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " HBTX ,High bandwidth TX enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " DYNFIFO ,Dynamic FIFO size enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SOFTCON ,Soft connect enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " UTMIWID ,UTMI data width" "8 bit,16 bit"
|
|
group.word 0x110++0x01 "Endpoint 1"
|
|
line.word 0x00 "USB0_EP1_TXMAXP,USB0 EP1 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "USB0_EP1_TXCSR_H,USB0 EP1 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x110+0x02)++0x01
|
|
line.word 0x00 "USB0_EP1_TXCSR_P,USB0 EP1 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x110+0x04)++0x01
|
|
line.word 0x00 "USB0_EP1_RXMAXP,USB0 EP1 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x110+0x06)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCSR_H,USB0 EP1 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x110+0x06)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCSR_P,USB0 EP1 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x110+0x08)++0x01
|
|
line.word 0x00 "USB0_EP1_RXCNT,USB0 EP1 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x110+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x110+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP1_TXTYPE,USB0 EP1 Transmit Type Register"
|
|
endif
|
|
group.byte (0x110+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP1_TXINTERVAL,USB0 EP1 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x110+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x110+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP1_RXTYPE,USB0 EP1 Receive Type Register"
|
|
endif
|
|
group.byte (0x110+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP1_RXINTERVAL,USB0 EP1 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x110+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP1_FIFOSZ,USB0 EP1 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x120++0x01 "Endpoint 2"
|
|
line.word 0x00 "USB0_EP2_TXMAXP,USB0 EP2 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "USB0_EP2_TXCSR_H,USB0 EP2 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x120+0x02)++0x01
|
|
line.word 0x00 "USB0_EP2_TXCSR_P,USB0 EP2 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x120+0x04)++0x01
|
|
line.word 0x00 "USB0_EP2_RXMAXP,USB0 EP2 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x120+0x06)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCSR_H,USB0 EP2 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x120+0x06)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCSR_P,USB0 EP2 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x120+0x08)++0x01
|
|
line.word 0x00 "USB0_EP2_RXCNT,USB0 EP2 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x120+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x120+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP2_TXTYPE,USB0 EP2 Transmit Type Register"
|
|
endif
|
|
group.byte (0x120+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP2_TXINTERVAL,USB0 EP2 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x120+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x120+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP2_RXTYPE,USB0 EP2 Receive Type Register"
|
|
endif
|
|
group.byte (0x120+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP2_RXINTERVAL,USB0 EP2 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x120+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP2_FIFOSZ,USB0 EP2 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x130++0x01 "Endpoint 3"
|
|
line.word 0x00 "USB0_EP3_TXMAXP,USB0 EP3 Transmit Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "USB0_EP3_TXCSR_H,USB0 EP3 Transmit Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 9. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAKTOINCMP ,NAK timeout incomplete" "No timeout,Timeout"
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " RXSTALL ,RX STALL" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup packet" "OUT packet,SETUP packet"
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " TXTOERR ,TX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x130+0x02)++0x01
|
|
line.word 0x00 "USB0_EP3_TXCSR_P,USB0 EP3 Transmit Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOSET ,Txpkrdy autoset enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAREQEN ,DMA request enable TX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATGL ,Force data toggle" "No effect,Toggle"
|
|
bitfld.word 0x00 10. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 7. " INCOMPTX ,Incomplete TX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 6. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 5. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 2. " URUNERR ,Underrun error" "No error,Error"
|
|
rbitfld.word 0x00 1. " NEFIFO ,Not empty FIFO" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TXPKTRDY ,TX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x130+0x04)++0x01
|
|
line.word 0x00 "USB0_EP3_RXMAXP,USB0 EP3 Receive Maximum Packet Length Register"
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 11.--12. " MULTM1 ,Multi-Packets per Micro-frame" "1,2,3,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAY ,Maximum payload"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.word (0x130+0x06)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCSR_H,USB0 EP3 Receive Configuration And Status (host) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Auto request clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PIDERR ,Packet ID error" "No error,Error"
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 10. " DATGLEN ,Data toggle write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATGL ,Data toggle" "DATA0,DATA1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "No effect,Clear"
|
|
bitfld.word 0x00 6. " RXSTALL ,RX STALL" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,Request packet" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
bitfld.word 0x00 3. " NAKTODERR ,NAK timeout data error" "No error,Error"
|
|
bitfld.word 0x00 2. " RXTOERR ,RX timeout error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
else
|
|
group.word (0x130+0x06)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCSR_P,USB0 EP3 Receive Configuration And Status (peripheral) Register"
|
|
bitfld.word 0x00 15. " AUTOCLR ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfers" "Bulk or interrupt,Isochronous"
|
|
bitfld.word 0x00 13. " DMAREQEN ,DMA request enable RX EP" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 12. " DNYETPERR ,Disable NYET handshake" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " DMAREQMODE ,DMA mode select" "DMA mode 0,DMA mode 1"
|
|
textline " "
|
|
sif !cpuis("ADSPCM40*")
|
|
bitfld.word 0x00 8. " INCOMPRX ,Incomplete RX" "Complete,Incomplete"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " CLRDATATGL ,Clear endpoint data toggle" "0,1"
|
|
bitfld.word 0x00 6. " SENTSTALL ,Sent STALL" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Send STALL" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Flush endpoint FIFO" "No flush,Flush"
|
|
rbitfld.word 0x00 3. " DATAERR ,Data error" "No error,Error"
|
|
bitfld.word 0x00 2. " ORUNERR ,OUT run error" "No error,Error"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
bitfld.word 0x00 0. " RXPKTRDY ,RX packet ready" "Not ready,Ready"
|
|
endif
|
|
group.word (0x130+0x08)++0x01
|
|
line.word 0x00 "USB0_EP3_RXCNT,USB0 EP3 Number Of Bytes Received Register"
|
|
hexmask.word 0x00 0.--13. 1. " EPRXCNT ,EP RX count"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x130+0x0A)++0x00
|
|
line.byte 0x00 "USB0_EP3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x130+0x0A)++0x00
|
|
hide.byte 0x00 "USB0_EP3_TXTYPE,USB0 EP3 Transmit Type Register"
|
|
endif
|
|
group.byte (0x130+0x0B)++0x00
|
|
line.byte 0x00 "USB0_EP3_TXINTERVAL,USB0 EP3 Transmit Polling Interval Register"
|
|
if (((per.b(ad:0x40030000+0x60))&0x04)==0x04)
|
|
group.byte (0x130+0x0C)++0x00
|
|
line.byte 0x00 "USB0_EP3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Speed of operation value" "Processor core speed,High speed,Full speed,Low speed"
|
|
bitfld.byte 0x00 4.--5. " PROTOCOL ,Protocol for transfer" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.byte 0x00 0.--3. " TGTEP ,Target endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.byte (0x130+0x0C)++0x00
|
|
hide.byte 0x00 "USB0_EP3_RXTYPE,USB0 EP3 Receive Type Register"
|
|
endif
|
|
group.byte (0x130+0x0D)++0x00
|
|
line.byte 0x00 "USB0_EP3_RXINTERVAL,USB0 EP3 Receive Polling Interval Register"
|
|
sif cpuis("ADSPCM40*")
|
|
rgroup.byte (0x130+0x0F)++0x00
|
|
line.byte 0x00 "USB0_EP3_FIFOSZ,USB0 EP3 FIFO Size"
|
|
bitfld.byte 0x00 4.--7. " RXFIFOSZ ,Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " TXFIFOSZ ,Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "DMA Registers"
|
|
hgroup.byte 0x200++0x00
|
|
hide.byte 0x00 "USB0_DMA_IRQ,USB0 DMA Interrupt Register"
|
|
in
|
|
group.word 0x204++0x01 "Channel 0"
|
|
line.word 0x00 "USB0_DMA0_CTL,USB0 DMA Channel 0 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x204+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA0_ADDR,USB0 DMA Channel 0 Address Register"
|
|
line.long 0x04 "USB0_DMA0_CNT,USB0 DMA Channel 0 Count Register"
|
|
group.word 0x214++0x01 "Channel 1"
|
|
line.word 0x00 "USB0_DMA1_CTL,USB0 DMA Channel 1 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x214+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA1_ADDR,USB0 DMA Channel 1 Address Register"
|
|
line.long 0x04 "USB0_DMA1_CNT,USB0 DMA Channel 1 Count Register"
|
|
group.word 0x224++0x01 "Channel 2"
|
|
line.word 0x00 "USB0_DMA2_CTL,USB0 DMA Channel 2 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x224+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA2_ADDR,USB0 DMA Channel 2 Address Register"
|
|
line.long 0x04 "USB0_DMA2_CNT,USB0 DMA Channel 2 Count Register"
|
|
group.word 0x234++0x01 "Channel 3"
|
|
line.word 0x00 "USB0_DMA3_CTL,USB0 DMA Channel 3 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x234+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA3_ADDR,USB0 DMA Channel 3 Address Register"
|
|
line.long 0x04 "USB0_DMA3_CNT,USB0 DMA Channel 3 Count Register"
|
|
group.word 0x244++0x01 "Channel 4"
|
|
line.word 0x00 "USB0_DMA4_CTL,USB0 DMA Channel 4 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x244+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA4_ADDR,USB0 DMA Channel 4 Address Register"
|
|
line.long 0x04 "USB0_DMA4_CNT,USB0 DMA Channel 4 Count Register"
|
|
group.word 0x254++0x01 "Channel 5"
|
|
line.word 0x00 "USB0_DMA5_CTL,USB0 DMA Channel 5 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x254+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA5_ADDR,USB0 DMA Channel 5 Address Register"
|
|
line.long 0x04 "USB0_DMA5_CNT,USB0 DMA Channel 5 Count Register"
|
|
group.word 0x264++0x01 "Channel 6"
|
|
line.word 0x00 "USB0_DMA6_CTL,USB0 DMA Channel 6 Control Register"
|
|
bitfld.word 0x00 9.--10. " BRSTM ,Burst mode" "Unspecified length,Incr4|unspecified length,Incr8|incr4|unspecified length,Incr16|incr8|incr4|unspecified length"
|
|
bitfld.word 0x00 8. " ERR ,Bus error" "No error,Error"
|
|
bitfld.word 0x00 4.--7. " EP ,DMA channel endpoint assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IE ,DMA interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MODE ,DMA mode" "DMA mode 0,DMA mode 1"
|
|
bitfld.word 0x00 1. " DIR ,DMA transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EN ,DMA enable" "Disabled,Enabled"
|
|
group.long (0x264+0x04)++0x07
|
|
line.long 0x00 "USB0_DMA6_ADDR,USB0 DMA Channel 6 Address Register"
|
|
line.long 0x04 "USB0_DMA6_CNT,USB0 DMA Channel 6 Count Register"
|
|
tree.end
|
|
width 20.
|
|
tree "Endpoint Request Packet Count Registers"
|
|
group.word 0x300++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT0,USB0 EP0 Request Packet Count Register"
|
|
group.word 0x304++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT1,USB0 EP1 Request Packet Count Register"
|
|
group.word 0x308++0x01
|
|
line.word 0x00 "USB0_RQPKTCNT2,USB0 EP2 Request Packet Count Register"
|
|
tree.end
|
|
width 22.
|
|
sif cpuis("ADSPCM40*")
|
|
group.word 0x340++0x03
|
|
line.word 0x00 "USB0_RXDPKTBUFDIS,USB0 RX Double Packet Buffer Disable for Endpoints"
|
|
bitfld.word 0x00 3. " EP3 ,Disable RX Double Buffer of Endpoint 3" "Enabled,Disabled"
|
|
bitfld.word 0x00 2. " EP2 ,Disable RX Double Buffer of Endpoint 2" "Enabled,Disabled"
|
|
bitfld.word 0x00 1. " EP1 ,Disable RX Double Buffer of Endpoint 1" "Enabled,Disabled"
|
|
line.word 0x02 "USB0_TXDPKTBUFDIS,USB0 TX Double Packet Buffer Disable for Endpoints"
|
|
bitfld.word 0x02 3. " EP3 ,Disable TX Double Buffer of Endpoint 3" "Enabled,Disabled"
|
|
bitfld.word 0x02 2. " EP2 ,Disable TX Double Buffer of Endpoint 2" "Enabled,Disabled"
|
|
bitfld.word 0x02 1. " EP1 ,Disable TX Double Buffer of Endpoint 1" "Enabled,Disabled"
|
|
else
|
|
group.word 0x344++0x05
|
|
line.word 0x00 "USB0_CT_UCH,USB0 Chirp Timeout Register"
|
|
hexmask.word 0x00 0.--14. 1. " VALUE ,Chirp timeout value"
|
|
line.word 0x02 "USB0_CT_HHSRTN,USB0 Host High Speed Return To Normal Register"
|
|
hexmask.word 0x02 0.--14. 1. " VALUE ,Host high speed return to normal value"
|
|
line.word 0x04 "USB0_CT_HSBT,USB0 High Speed Timeout Register"
|
|
bitfld.word 0x04 0.--3. " VALUE ,HS timeout adder" "736 bit time,800 bit time,864 bit time,?..."
|
|
endif
|
|
group.word 0x360++0x01
|
|
line.word 0x00 "USB0_LPM_ATTR,USB0 LPM Attribute Register"
|
|
bitfld.word 0x00 12.--15. " EP ,Endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.word 0x00 8. " RMTWAK ,Remote wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4.--7. " HIRD ,Host initiated resume duration" "50 us,125 us,200 us,275 us,350 us,425 us,500 us,575 us,650 us,725 us,800 us,875 us,950 us,1025 us,1100 us,1175 us"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " LINKSTATE ,Link state" ",Sleep state,?..."
|
|
group.byte 0x362++0x01
|
|
line.byte 0x00 "USB0_LPM_CTL,USB0 LPM Control Register"
|
|
bitfld.byte 0x00 4. " NAK ,LPM NAK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " EN ,LPM enable" "Disabled,Disabled,Enabled extended transactions,Enabled LPM and extended transactions"
|
|
bitfld.byte 0x00 1. " RESUME ,LPM resume (remote wakeup)" "No effect,Resume"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TX ,LPM transmit" "Disabled,Enabled"
|
|
line.byte 0x01 "USB0_LPM_IEN,USB0 LPM Interrupt Enable Register"
|
|
bitfld.byte 0x01 5. " LPMERR ,LPM error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " LPMRES ,LPM resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " LPMNC ,LPM NYET control interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " LPMACK ,LPM ACK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " LPMNY ,LPM NYET interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " LPMST ,LPM STALL interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x364++0x00
|
|
hide.byte 0x00 "USB0_LPM_IRQ,USB0 LPM Interrupt Status Register"
|
|
in
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "USB0_LPM_FADDR,USB0 LPM Function Address Register"
|
|
hexmask.byte 0x00 0.--6. 1. " VALUE ,Function address value"
|
|
group.byte 0x380++0x00
|
|
line.byte 0x00 "USB0_VBUS_CTL,USB0 VBUS Control Register"
|
|
rbitfld.byte 0x00 4. " DRV ,VBUS drive" "Low,High"
|
|
eventfld.byte 0x00 3. " DRVINT ,VBUS drive interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " DRVIEN ,VBUS drive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DRVOD ,VBUS drive open drain" "No open drain,Open drain"
|
|
bitfld.byte 0x00 0. " INVDRV ,VBUS invert drive" "Not inverted,Inverted"
|
|
sif !cpuis("ADSPCM40*")
|
|
if ((((per.b(ad:0x40030000+0x60))&0x80)==0x80)&&(((per.b(ad:0x40030000+0x381))&0x01)==0x01))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
bitfld.byte 0x00 4. " DEDCHG ,Dedicated charging port" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CONDET ,Connected detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
elif ((((per.b(ad:0x40030000+0x60))&0x80)==0x80)&&(((per.b(ad:0x40030000+0x381))&0x01)==0x00))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
bitfld.byte 0x00 4. " DEDCHG ,Dedicated charging port" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
elif ((((per.b(ad:0x40030000+0x60))&0x80)==0x00)&&(((per.b(ad:0x40030000+0x381))&0x01)==0x01))
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 1. " CONDET ,Connected detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "USB0_BAT_CHG,USB0 Battery Charging Control Register"
|
|
rbitfld.byte 0x00 3. " CHGDET ,Charging port detected" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " SNSCHGDET ,Sense charger detection" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SNSCONDET ,Sense connection detection" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif !cpuis("ADSP-SC57?")
|
|
group.byte 0x382++0x00
|
|
line.byte 0x00 "USB0_IDCTL,USB0 ID Control"
|
|
bitfld.byte 0x00 1. " IDVAL ,ID value" "0,1"
|
|
bitfld.byte 0x00 0. " IDSEL ,ID select" "0,1"
|
|
endif
|
|
sif cpuis("ADSPCM40*")
|
|
group.byte 0x39C++0x00
|
|
line.byte 0x00 "USB0_PHY_CTL,USB0 PHY Control Register"
|
|
bitfld.byte 0x00 1. " SUSPEND ,Suspend power" "Normal operation,Enabled"
|
|
bitfld.byte 0x00 0. " PHYMAN ,PHY management" "From controller,From PHY_CTL"
|
|
rgroup.word 0x3A0++0x01
|
|
line.word 0x00 "USB0_PHY_STAT,USB0 PHY Status Register"
|
|
bitfld.word 0x00 7. " VBUSVALID ,Vbus Voltage Valid" "Vbus < 4.4V,Vbus >4.75V"
|
|
bitfld.word 0x00 5. " AVALID ,Vbus Voltage A Device Valid" "Vbus < 0.8V,Vbus > 2V"
|
|
bitfld.word 0x00 4. " VBUSLO ,Vbus Voltage Session End" "Vbus > 0.8V,Vbus < 0.2V"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CID ,ID Input State" "0,1"
|
|
else
|
|
group.byte 0x394++0x00
|
|
line.byte 0x00 "USB0_PHY_CTL,USB0 PHY Control Register"
|
|
bitfld.byte 0x00 7. " EN ,PHY enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ADSP-SC57?")
|
|
bitfld.byte 0x00 4. " DIS ,Disable PHY" "Yes,No"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 1. " RESTORE ,Restore from hibernate" "Not restore,Restore"
|
|
bitfld.byte 0x00 0. " HIBER ,Hibernate" "Disabled,Enabled"
|
|
group.word 0x398++0x01
|
|
line.word 0x00 "USB0_PLL_OSC,USB0 PLL And Oscillator Control Register"
|
|
rbitfld.word 0x00 14. " PLLSTABLE ,PLL stable" "Unstable,Stable"
|
|
bitfld.word 0x00 7. " PLLMSEL ,PLL multiplier select" "Not used,Used"
|
|
bitfld.word 0x00 1.--6. " PLLM ,PLL multiplier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DIVCLKIN ,Divide CLKIN" "Not divided,Divided by 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("ADSPCM407F")||cpuis("ADSPCM408F")||cpuis("ADSPCM409F"))
|
|
tree "EMAC (Ethernet Media Access Controller)"
|
|
base ad:0x40020000
|
|
width 29.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EMAC0_MACCFG,EMAC0 MAC Configuration Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 28.--30. " SARC ,Source address insertion or replacement control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27. " TWOKPE ,Support for 2K packets" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " CST ,CRC stripping" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 24. " TC ,Transmit configuration in RGMII" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " WD ,Watch dog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JB ,Jabber disable" "No,Yes"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " BE ,Frame burst enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " JE ,Jumbo frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " IFG ,Inter-Frame gap" "96-bit,88-bit,80-bit,72-bit,64-bit,56-bit,48-bit,40-bit"
|
|
bitfld.long 0x00 16. " DCRS ,Disable carrier sense" "No,Yes"
|
|
textline " "
|
|
sif cpuis("ADSP-SC57?")
|
|
textline " "
|
|
rbitfld.long 0x00 15. " PS ,Port Select" "1000 Mbps,10/100 Mbps"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " FES ,Speed of operation" "10 Mbps,100 Mbps"
|
|
bitfld.long 0x00 13. " DO ,Disable receive own" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "No loopback,Loopback"
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex"
|
|
bitfld.long 0x00 10. " IPC ,IP checksum" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DR ,Disable retry" "No,Yes"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 8. " LUD ,Link up or down" "Down,Up"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACS ,Automatic pad/crc stripping" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " BL ,Back off limit-min(attempts, BL)" "10,8,4,1"
|
|
bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PRELEN ,Preamble length for transmit frames" "0,1,2,3"
|
|
endif
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "EMAC0_MACFRMFILT,EMAC0 MAC Rx Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all frames" "Disabled,Enabled"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " DNTU ,Drop non-TCP/UDP over IP frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IPFE ,Layer 3 and layer 4 filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VTFE ,VAN tag filter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Hash,Hash or perfect"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 9. " SAF ,Source address filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "None,All but PAUSE,All,Address filtered"
|
|
bitfld.long 0x00 5. " DBF ,Disable broadcast frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PM ,Pass all multicast frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HMC ,Hash multicast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HUC ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PR ,Promiscuous mode" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_HASHTBL_HI,EMAC0 Hash Table High Register"
|
|
line.long 0x08 "EMAC0_HASHTBL_LO,EMAC0 Hash Table Low Register"
|
|
line.long 0x0C "EMAC0_SMI_ADDR,EMAC0 SMI Address Register"
|
|
bitfld.long 0x0C 11.--15. " PA ,Physical layer address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--10. " SMIR ,SMI register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 2.--5. " CR ,Clock range" "SCLK/42,SCLK/62,SCLK/16,SCLK/26,,,,,SCLK/4,SCLK/6,SCLK/8,SCLK/10,SCLK/12,SCLK/14,SCLK/16,SCLK/18"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SMIW ,SMI write" "Read,Write"
|
|
bitfld.long 0x0C 0. " SMIB ,SMI busy" "Not busy,Busy"
|
|
line.long 0x10 "EMAC0_SMI_DATA,EMAC0 SMI Data Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " SMID ,SMI data"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "EMAC0_FLOWCTL,EMAC0 Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " DZPQ ,Disable Zero-Quanta pause" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UP ,Unicast pause frame detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE ,Transmit flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCBBPA ,Initiate pause control frame" "No action,Initiated"
|
|
line.long 0x04 "EMAC0_VLANTAG,EMAC0 VLAN Tag Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x04 19. " VTHM ,VLAN tag hash table match enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ESVL ,Enable S-VLAN" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " VTIM ,VLAN tag inverse match enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 16. " ETV ,Enable tag VLAN comparison" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " VL ,VLAN tag id receive frames"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "EMAC0_DBG,EMAC0 Debug Register"
|
|
bitfld.long 0x00 25. " TXFIFOFULL ,Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " TXFIFONE ,Tx FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 22. " TXFIFOACT ,Tx FIFO active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TXFIFOCTLST ,Tx FIFO controller state" "Idle,Read,Waiting for TxStatus,Writing TxStatus"
|
|
bitfld.long 0x00 19. " TXPAUSE ,Tx paused" "Not paused,Paused"
|
|
bitfld.long 0x00 17.--18. " TXFRCTL ,Tx frame controller state" "Idle,Wait,Pause,Transmit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMTEA ,MM tx engine active" "Not active,Active"
|
|
bitfld.long 0x00 8.--9. " RXFIFOST ,Rx FIFO state" "Empty,Below FCT,Above FCT,Full"
|
|
bitfld.long 0x00 5.--6. " RXFIFOCTLST ,Rx FIFO controller state" "Idle,Read data,Read status,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFIFOACT ,Rx FIFO active" "Not active,Active"
|
|
bitfld.long 0x00 2. " SFIFOST[1] ,Small FIFO write state" "Not active,Active"
|
|
bitfld.long 0x00 1. " [0] ,Small FIFO read state" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MMREA ,MM Rx engine active" "Not active,Active"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "EMAC0_LPI_CTLSTAT,EMAC0 Low Power Idle Control And Status Register"
|
|
in
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMAC0_LPI_TMRSCTL,EMAC0 Low Power Idle Timeout Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " LST ,Link status timer"
|
|
hexmask.long.word 0x00 0.--15. 1. " TWT ,Timer wait time"
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMAC0_ISTAT,EMAC0 Interrupt Status Register"
|
|
bitfld.long 0x00 10. " LPIIS ,LPI interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " TS ,Time stamp interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " MMCRC ,MMC receive checksum offload interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MMCTX ,MMC transmit interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " MMCRX ,MMC receive interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " MMC ,MMC interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RGMIIIS ,RGMII or SMII interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMAC0_IMSK,EMAC0 Interrupt Mask Register"
|
|
bitfld.long 0x00 10. " LPIIM ,LPI interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 9. " TS ,Time stamp interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " RGMIIIM ,RGMII or SMII interrupt mask" "Unmasked,Masked"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "EMAC0_ADDR0_HI,EMAC0 MAC Address 0 High Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x04 "EMAC0_ADDR0_LO,EMAC0 MAC Address 0 Low Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "EMAC0_ADDR1_HI,EMAC0 MAC Address 1 High Register"
|
|
bitfld.long 0x00 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SA ,Source address compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MBC[5] ,Mask byte 5 control" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [4] ,Mask byte 4 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 27. " [3] ,Mask byte 3 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 26. " [2] ,Mask byte 2 control" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [1] ,Mask byte 1 control" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " [0] ,Mask byte 0 control" "Unmasked,Masked"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADDRHI ,Mac address"
|
|
line.long 0x04 "EMAC0_ADDR1_LO,EMAC0 MAC Address 1 Low Register"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "EMAC0_GIGE_CTLSTAT,EMAC0 RGMII Control And Status Register"
|
|
bitfld.long 0x00 3. " LNKSTS ,Link status" "Down,Up"
|
|
bitfld.long 0x00 1.--2. " LNKSPEED ,Link speed" "10Mbps,100Mbps,1000Mbps,"
|
|
bitfld.long 0x00 0. " LNKMOD ,Link mode" "Half duplex,Full duplex"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "EMAC0_WDOG_TIMOUT,EMAC0 Watchdog Timeout Register"
|
|
bitfld.long 0x00 16. " PWE ,Programmable watchdog enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--13. 1. " WTO ,Watchdog timeout"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EMAC0_MMC_CTL,EMAC0 MMC Control Register"
|
|
bitfld.long 0x00 5. " FULLPSET ,Full preset" "Half,Full"
|
|
bitfld.long 0x00 4. " CNTRPSET ,Counter reset/preset" "No action,Reset"
|
|
bitfld.long 0x00 3. " CNTRFRZ ,Counter freeze" "No freeze,Freeze"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RDRST ,Read reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " NOROLL ,Disable rollover" "No,Yes"
|
|
bitfld.long 0x00 0. " RST ,Reset" "No action,Reset"
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "EMAC0_MMC_RXINT,EMAC0 MMC Rx Interrupt Register"
|
|
in
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "EMAC0_MMC_TXINT,EMAC0 MMC Tx Interrupt Register"
|
|
in
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "EMAC0_MMC_RXIMSK,EMAC0 MMC Rx Interrupt Mask Register"
|
|
sif (cpuis("ADSPCM40*")||cpuis("ADSP-SC57?"))
|
|
bitfld.long 0x00 25. " CTLFIM ,Rx control frame counter interrupt mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " RCVERRFIM ,Rx error frame counter interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " WATCHERR ,Rx watch dog error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 21. " FIFOOV ,Rx FIFO overflow count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 20. " PAUSEFRM ,Rx pause frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUTRANGE ,Rx out of range type count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 18. " LENERR ,Rx length error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 17. " UCASTG ,Rx unicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 11. " R64 ,Rx 64 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSIZEG ,Rx oversize (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 9. " USIZEG ,Rx undersize (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 8. " JABERR ,Rx jabber error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RUNTERR ,Rx runt error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 6. " ALIGNERR ,Rx alignment error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 5. " CRCERR ,Rx CRC error count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MCASTG ,Rx multicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 3. " BCASTG ,Rx broadcast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 2. " OCTCNTG ,Rx octet count (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCTCNTGB ,Rx octet count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 0. " FRCNTGB ,Rx frame count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
line.long 0x04 "EMAC0_MMC_TXIMSK,EMAC0 MMC TX Interrupt Mask Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x04 25. " OSZGFIM ,Tx oversize good frame count interrupt mask" "Unmasked,Masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " VLANFRG ,Tx VLAN frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 23. " PAUSEFRM ,Tx pause frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXCESSDEF ,Tx excess deferred count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 21. " FRCNTG ,Tx frame count (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 20. " OCTCNTG ,Tx octet count (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CARRERR ,Tx carrier error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 18. " EXCESSCOL ,Tx exess collision count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 17. " LATECOL ,Tx late collision count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DEFERRED ,Tx deferred count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 15. " MULTCOLG ,Tx multiple collisions (good) count mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 14. " SNGCOLG ,Tx single collision (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " UNDERR ,Tx underflow error count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 12. " BCASTGB ,Tx broadcast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 11. " MCASTGB ,Tx multicast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " UCASTGB ,Tx unicast frames (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 9. " T1024TOMAX ,Tx 1024-to-max octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 8. " T512TO1023 ,Tx 512-to-1023 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " T256TO511 ,Tx 256-to-511 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 6. " T128TO255 ,Tx 128-to-255 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 5. " T65TO127 ,Tx 65-to-127 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " T64 ,Tx 64 octets (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 3. " MCASTG ,Tx multicast frames (good) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 2. " BCASTG ,Tx broadcast frames (good) count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FRCNTGB ,Tx frame count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x04 0. " OCTCNTGB ,Tx octet count (good/bad) count half/full mask" "Unmasked,Masked"
|
|
rgroup.long 0x114++0x67
|
|
line.long 0x00 "EMAC0_TXOCTCNT_GB,EMAC0 Tx OCT Count (good/bad) Register"
|
|
line.long 0x04 "EMAC0_TXFRMCNT_GB,EMAC0 Tx Frame Count (good/bad) Register"
|
|
line.long 0x08 "EMAC0_TXBCASTFRM_G,EMAC0 Tx Broadcast Frames (good) Register"
|
|
line.long 0x0C "EMAC0_TXMCASTFRM_G,EMAC0 Tx Multicast Frames (good) Register"
|
|
line.long 0x10 "EMAC0_TX64_GB,EMAC0 Tx 64-Byte Frames (good/bad) Register"
|
|
line.long 0x14 "EMAC0_TX65TO127_GB,EMAC0 Tx 65- To 127-Byte Frames (good/bad) Register"
|
|
line.long 0x18 "EMAC0_TX128TO255_GB,EMAC0 Tx 128- To 255-Byte Frames (good/bad) Register"
|
|
line.long 0x1C "EMAC0_TX256TO511_GB,EMAC0 Tx 256- To 511-Byte Frames (good/bad) Register"
|
|
line.long 0x20 "EMAC0_TX512TO1023_GB,EMAC0 Tx 512- To 1023-Byte Frames (good/bad) Register"
|
|
line.long 0x24 "EMAC0_TX1024TOMAX_GB,EMAC0 Tx 1024- To Max-Byte Frames (good/bad) Register"
|
|
line.long 0x28 "EMAC0_TXUCASTFRM_GB,EMAC0 Tx Unicast Frames (good/bad) Register"
|
|
line.long 0x2C "EMAC0_TXMCASTFRM_GB,EMAC0 Tx Multicast Frames (good/bad) Register"
|
|
line.long 0x30 "EMAC0_TXBCASTFRM_GB,EMAC0 Tx Broadcast Frames (good/bad) Register"
|
|
line.long 0x34 "EMAC0_TXUNDR_ERR,EMAC0 Tx Underflow Error Register"
|
|
line.long 0x38 "EMAC0_TXSNGCOL_G,EMAC0 Tx Single Collision (good) Register"
|
|
line.long 0x3C "EMAC0_TXMULTCOL_G,EMAC0 Tx Multiple Collision (good) Register"
|
|
line.long 0x40 "EMAC0_TXDEFERRED,EMAC0 Tx Deferred Register"
|
|
line.long 0x44 "EMAC0_TXLATECOL,EMAC0 Tx Late Collision Register"
|
|
line.long 0x48 "EMAC0_TXEXCESSCOL,EMAC0 Tx Excess Collision Register"
|
|
line.long 0x4C "EMAC0_TXCARR_ERR,EMAC0 Tx Carrier Error Register"
|
|
line.long 0x50 "EMAC0_TXOCTCNT_G,EMAC0 Tx Octet Count (good) Register"
|
|
line.long 0x54 "EMAC0_TXFRMCNT_G,EMAC0 Tx Frame Count (good) Register"
|
|
line.long 0x58 "EMAC0_TXEXCESSDEF,EMAC0 Tx Excess Deferral Register"
|
|
line.long 0x5C "EMAC0_TXPAUSEFRM,EMAC0 Tx Pause Frame Register"
|
|
line.long 0x60 "EMAC0_TXVLANFRM_G,EMAC0 Tx VLAN Frames (good) Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "EMAC0_TXOVRSIZE_G,EMAC0 Number Of Tx Frames (good) Greater Than Maxsize"
|
|
endif
|
|
rgroup.long 0x180++0x67
|
|
line.long 0x00 "EMAC0_RXFRMCNT_GB,EMAC0 Rx Frame Count (good/bad) Register"
|
|
line.long 0x04 "EMAC0_RXOCTCNT_GB,EMAC0 Rx Octet Count (good/bad) Register"
|
|
line.long 0x08 "EMAC0_RXOCTCNT_G,EMAC0 Rx Octet Count (good) Register"
|
|
line.long 0x0C "EMAC0_RXBCASTFRM_G,EMAC0 Rx Broadcast Frames (good) Register"
|
|
line.long 0x10 "EMAC0_RXMCASTFRM_G,EMAC0 Rx Multicast Frames (good) Register"
|
|
line.long 0x14 "EMAC0_RXCRC_ERR,EMAC0 Rx CRC Error Register"
|
|
line.long 0x18 "EMAC0_RXALIGN_ERR,EMAC0 Rx Alignment Error Register"
|
|
line.long 0x1C "EMAC0_RXRUNT_ERR,EMAC0 Rx Runt Error Register"
|
|
line.long 0x20 "EMAC0_RXJAB_ERR,EMAC0 Rx Jab Error Register"
|
|
line.long 0x24 "EMAC0_RXUSIZE_G,EMAC0 Rx Undersize (good) Register"
|
|
line.long 0x28 "EMAC0_RXOSIZE_G,EMAC0 Rx Oversize (good) Register"
|
|
line.long 0x2C "EMAC0_RX64_GB,EMAC0 Rx 64-Byte Frames (good/bad) Register"
|
|
line.long 0x30 "EMAC0_RX65TO127_GB,EMAC0 Rx 65- To 127-Byte Frames (good/bad) Register"
|
|
line.long 0x34 "EMAC0_RX128TO255_GB,EMAC0 Rx 128- To 255-Byte Frames (good/bad) Register"
|
|
line.long 0x38 "EMAC0_RX256TO511_GB,EMAC0 Rx 256- To 511-Byte Frames (good/bad) Register"
|
|
line.long 0x3C "EMAC0_RX512TO1023_GB,EMAC0 Rx 512- To 1023-Byte Frames (good/bad) Register"
|
|
line.long 0x40 "EMAC0_RX1024TOMAX_GB,EMAC0 Rx 1024- To Max-Byte Frames (good/bad) Register"
|
|
line.long 0x44 "EMAC0_RXUCASTFRM_G,EMAC0 Rx Unicast Frames (good) Register"
|
|
line.long 0x48 "EMAC0_RXLEN_ERR,EMAC0 Rx Length Error Register"
|
|
line.long 0x4C "EMAC0_RXOORTYPE,EMAC0 Rx Out Of Range Type Register"
|
|
line.long 0x50 "EMAC0_RXPAUSEFRM,EMAC0 Rx Pause Frames Register"
|
|
line.long 0x54 "EMAC0_RXFIFO_OVF,EMAC0 Rx FIFO Overflow Register"
|
|
line.long 0x58 "EMAC0_RXVLANFRM_GB,EMAC0 Rx VLAN Frames (good/bad) Register"
|
|
line.long 0x5C "EMAC0_RXWDOG_ERR,EMAC0 Rx Watch Dog Error Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
rgroup.long 0x1E0++0x07
|
|
line.long 0x00 "EMAC0_RXRCV_ERR,EMAC0 Rx Error Frames Received Register"
|
|
line.long 0x04 "EMAC0_RXCTLFRM_G,EMAC0 Rx Good Control Frames Register"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "EMAC0_IPC_RXIMSK,EMAC0 MMC IPC Rx Interrupt Mask Register"
|
|
bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 27. " TCPERROCT ,Rx TCP error octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 25. " UDPERROCT ,Rx UDP error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (good) octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " V6NOPAYOCT ,Rx ipv6 no payload octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 22. " V6HDERROCT ,Rx ipv6 header error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 21. " V6GOCT ,Rx ipv6 (good) octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V4UDSBLOCT ,Rx ipv4 UDS disable octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 19. " V4FRAGOCT ,Rx ipv4 fragmented octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 18. " V4NOPAYOCT ,Rx ipv4 no payload octets count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " V4HDERROCT ,Rx ipv4 header error octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 16. " V4GOCT ,Rx ipv4 (good) octets count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP error frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (good) frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UDPERRFRM ,Rx UDP error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 7. " V6NOPAYFRM ,Rx ipv6 no payload frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " V6HDERRFRM ,Rx ipv6 header error frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 5. " V6GFRM ,Rx ipv6 (good) frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 4. " V4UDSBLFRM ,Rx ipv4 UDS disable frames count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " V4FRAGFRM ,Rx ipv4 fragmented frames count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 2. " V4NOPAYFRM ,Rx ipv4 no payload frame count half/full mask" "Unmasked,Masked"
|
|
bitfld.long 0x00 1. " V4HDERRFRM ,Rx ipv4 header error frame count half/full mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " V4GFRM ,Rx ipv4 (good) frames count half/full mask" "Unmasked,Masked"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "EMAC0_IPC_RXINT,EMAC0 MMC IPC Rx Interrupt Register"
|
|
bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " TCPERROCT ,Rx TCP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " UDPERROCT ,Rx UDP error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " V6NOPAYOCT ,Rx ipv6 no payload octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " V6HDERROCT ,Rx ipv6 header error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " V6GOCT ,Rx ipv6 (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V4UDSBLOCT ,Rx ipv4 UDS disable octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " V4FRAGOCT ,Rx ipv4 fragmented octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " V4NOPAYOCT ,Rx ipv4 no payload octets count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " V4HDERROCT ,Rx ipv4 header error octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " V4GOCT ,Rx ipv4 (good) octets count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UDPERRFRM ,Rx IDP error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " V6NOPAYFRM ,Rx ipv6 no payload frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " V6HDERRFRM ,Rx ipv6 header error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " V6GFRM ,Rx ipv6 (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " V4UDSBLFRM ,Rx ipv4 UDS disable frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " V4FRAGFRM ,Rx ipv4 fragmented frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " V4NOPAYFRM ,Rx ipv4 no payload frames count half/full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " V4HDERRFRM ,Rx ipv4 header error frames count half/full interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " V4GFRM ,Rx ipv4 (good) frames count half/full interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0x210++0x37
|
|
line.long 0x00 "EMAC0_RXIPV4_GD_FRM,EMAC0 Rx Ipv4 Datagrams (good) Register"
|
|
line.long 0x04 "EMAC0_RXIPV4_HDR_ERR_FRM,EMAC0 Rx Ipv4 Datagrams Header Errors Register"
|
|
line.long 0x08 "EMAC0_RXIPV4_NOPAY_FRM,EMAC0 Rx Ipv4 Datagrams No Payload Frame Register"
|
|
line.long 0x0C "EMAC0_RXIPV4_FRAG_FRM,EMAC0 Rx Ipv4 Datagrams Fragmented Frames Register"
|
|
line.long 0x10 "EMAC0_RXIPV4_UDSBL_FRM,EMAC0 Rx Ipv4 UDP Disabled Frames Register"
|
|
line.long 0x14 "EMAC0_RXIPV6_GD_FRM,EMAC0 Rx Ipv6 Datagrams Good Frames Register"
|
|
line.long 0x18 "EMAC0_RXIPV6_HDR_ERR_FRM,EMAC0 Rx Ipv6 Datagrams Header Error Frames Register"
|
|
line.long 0x1C "EMAC0_RXIPV6_NOPAY_FRM,EMAC0 Rx Ipv6 Datagrams No Payload Frames Register"
|
|
line.long 0x20 "EMAC0_RXUDP_GD_FRM,EMAC0 Rx UDP Good Frames Register"
|
|
line.long 0x24 "EMAC0_RXUDP_ERR_FRM,EMAC0 Rx UDP Error Frames Register"
|
|
line.long 0x28 "EMAC0_RXTCP_GD_FRM,EMAC0 Rx TCP Good Frames Register"
|
|
line.long 0x2C "EMAC0_RXTCP_ERR_FRM,EMAC0 Rx TCP Error Frames Register"
|
|
line.long 0x30 "EMAC0_RXICMP_GD_FRM,EMAC0 Rx ICMP Good Frames Register"
|
|
line.long 0x34 "EMAC0_RXICMP_ERR_FRM,EMAC0 Rx ICMP Error Frames Register"
|
|
rgroup.long 0x250++0x37
|
|
line.long 0x00 "EMAC0_RXIPV4_GD_OCT,EMAC0 Rx Ipv4 Datagrams Good Octets Register"
|
|
line.long 0x04 "EMAC0_RXIPV4_HDR_ERR_OCT,EMAC0 Rx Ipv4 Datagrams Header Errors Register"
|
|
line.long 0x08 "EMAC0_RXIPV4_NOPAY_OCT,EMAC0 Rx Ipv4 Datagrams No Payload Octets Register"
|
|
line.long 0x0C "EMAC0_RXIPV4_FRAG_OCT,EMAC0 Rx Ipv4 Datagrams Fragmented Octets Register"
|
|
line.long 0x10 "EMAC0_RXIPV4_UDSBL_OCT,EMAC0 Rx Ipv4 UDP Disabled Octets Register"
|
|
line.long 0x14 "EMAC0_RXIPV6_GD_OCT,EMAC0 Rx Ipv6 Good Octets Register"
|
|
line.long 0x18 "EMAC0_RXIPV6_HDR_ERR_OCT,EMAC0 Rx Ipv6 Header Errors Register"
|
|
line.long 0x1C "EMAC0_RXIPV6_NOPAY_OCT,EMAC0 Rx Ipv6 No Payload Octets Register"
|
|
line.long 0x20 "EMAC0_RXUDP_GD_OCT,EMAC0 Rx UDP Good Octets Register"
|
|
line.long 0x24 "EMAC0_RXUDP_ERR_OCT,EMAC0 Rx UDP Error Octets Register"
|
|
line.long 0x28 "EMAC0_RXTCP_GD_OCT,EMAC0 Rx TCP Good Octets Register"
|
|
line.long 0x2C "EMAC0_RXTCP_ERR_OCT,EMAC0 Rx TCP Error Octets Register"
|
|
line.long 0x30 "EMAC0_RXICMP_GD_OCT,EMAC0 Rx ICMP Good Octets Register"
|
|
line.long 0x34 "EMAC0_RXICMP_ERR_OCT,EMAC0 Rx ICMP Error Octets Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "EMAC0_L3L4_CTL,EMAC0 Layer3 And Layer4 Control Register"
|
|
bitfld.long 0x00 21. " L4DPIM ,Layer 4 destination port inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " L4DPM ,Layer 4 destination port matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " L4SPIM ,Layer 4 source port inverse matching" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " L4SPM ,Layer 4 source port matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L4PEN ,Layer 4 filtering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--15. " L3HDBM ,Layer 3 destination address bits mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " L3HSBM ,Layer 3 source address bits mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " L3DAIM ,Layer 3 destination address inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " L3DAM ,Layer 3 destination address matching" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " L3SAIM ,Layer 3 source address inverse matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " L3SAM ,Layer 3 source address matching" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " L3PEN ,Layer 3 enabled" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_L4_ADDR,EMAC0 Layer 4 Address Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " L4DP ,Layer 4 destination port"
|
|
hexmask.long.word 0x04 0.--15. 1. " L4SP ,Layer 4 source port"
|
|
group.long 0x410++0x0F
|
|
line.long 0x00 "EMAC0_L3_ADDR0,EMAC0 Layer 3 Address0 Register"
|
|
line.long 0x04 "EMAC0_L3_ADDR1,EMAC0 Layer 3 Address1 Register"
|
|
line.long 0x08 "EMAC0_L3_ADDR2,EMAC0 Layer 3 Address2 Register"
|
|
line.long 0x0C "EMAC0_L3_ADDR3,EMAC0 Layer 3 Address3 Register"
|
|
group.long 0x584++0x07
|
|
line.long 0x00 "EMAC0_VLAN_INCL,EMAC0 VLAN Tag Inclusion Or Replacement Register"
|
|
bitfld.long 0x00 19. " CSVL ,C-VLAN or S-VLAN" "C-VLAN,S-VLAN"
|
|
bitfld.long 0x00 18. " VLP ,VLAN priority control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " VLC ,VLAN tag control in transmit frames" "No operation,Deletion,Insertion,Replacement"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " VLT ,VLAN tag for transmit frames"
|
|
line.long 0x04 "EMAC0_VLAN_HSHTBL,EMAC0 VLAN Hash Table Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VLHT ,VLAN hash table"
|
|
endif
|
|
group.long 0x700++0x07
|
|
line.long 0x00 "EMAC0_TM_CTL,EMAC0 Time Stamp Control Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 28. " ATSEN3 ,Auxiliary snapshot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATSEN2 ,Auxiliary snapshot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATSEN1 ,Auxiliary snapshot 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATSEN0 ,Auxiliary snapshot 0 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 24. " ATSFC ,Auxiliary time stamp FIFO clear" "No clear,Clear"
|
|
bitfld.long 0x00 18. " TSENMACADDR ,Time stamp enable MAC address" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SNAPTYPSEL ,Snapshot type select" "0,1,2,3"
|
|
bitfld.long 0x00 15. " TSMSTRENA ,Time stamp master (frames) enable" "Slave,Master"
|
|
bitfld.long 0x00 14. " TSEVNTENA ,Time stamp event (PTP frames) enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TSIPV4ENA ,Time stamp IPV4 (PTP frames) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSIPV6ENA ,Time stamp IPV6 (PTP frames) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSIPENA ,Time stamp IP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TSVER2ENA ,Time stamp VER2 (snooping) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TSCTRLSSR ,Time stamp control nanosecond rollover" "0x7FFFFFFF,0x3B9AC9FF"
|
|
bitfld.long 0x00 8. " TSENALL ,Time stamp enable all (frames)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TSADDREG ,Time stamp addend register update" "No effect,Update"
|
|
bitfld.long 0x00 4. " TSTRIG ,Time stamp (target time) trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSUPDT ,Time stamp (system time) update" "No effect,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TSINIT ,Time stamp (system time) initialize" "No effect,Initialize"
|
|
bitfld.long 0x00 1. " TSCFUPDT ,Time stamp (system time) fine/coarse update" "Coarse,Fine"
|
|
bitfld.long 0x00 0. " TSENA ,Time stamp (PTP) enable" "Disabled,Enabled"
|
|
line.long 0x04 "EMAC0_TM_SUBSEC,EMAC0 Time Stamp Sub Second Increment Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SSINC ,Sub-Second increment value"
|
|
rgroup.long 0x708++0x07
|
|
line.long 0x00 "EMAC0_TM_SEC,EMAC0 Time Stamp Low Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_NSEC,EMAC0 Time Stamp Nanoseconds Register"
|
|
hexmask.long 0x04 0.--30. 1. " TSSS ,Time stamp nanoseconds"
|
|
group.long 0x710++0x17
|
|
line.long 0x00 "EMAC0_TM_SECUPDT,EMAC0 Time Stamp Seconds Update Register"
|
|
line.long 0x04 "EMAC0_TM_NSECUPDT,EMAC0 Time Stamp Nanoseconds Update Register"
|
|
bitfld.long 0x04 31. " ADDSUB ,Add or subtract the time" "Add,Subtract"
|
|
hexmask.long 0x04 0.--30. 1. " TSSS ,Time stamp sub second initialize/increment"
|
|
line.long 0x08 "EMAC0_TM_ADDEND,EMAC0 Time Stamp Addend Register"
|
|
line.long 0x0C "EMAC0_TM_PPS0TGTM,EMAC0 Time Stamp Target Time Seconds Register"
|
|
line.long 0x10 "EMAC0_TM_PPS0NTGTM,EMAC0 Time Stamp Target Time Nanoseconds Register"
|
|
bitfld.long 0x10 31. " TSTRBUSY ,Target time register busy" "Not busy,Busy"
|
|
hexmask.long 0x10 0.--30. 1. " TSTR ,Target time nano seconds"
|
|
line.long 0x14 "EMAC0_TM_HISEC,EMAC0 Time Stamp High Second Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " TSHWR ,Time stamp higher word seconds register"
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "EMAC0_TM_STMPSTAT,EMAC0 Time Stamp Status Register"
|
|
in
|
|
group.long 0x72C++0x0B
|
|
line.long 0x00 "EMAC0_TM_PPSCTL,EMAC0 PPS Control Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 29.--30. " TRGTMODSEL3 ,Target time register mode for PPS3" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 24.--26. " PPSCMD3 ,Flexible PPS3 output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--22. " TRGTMODSEL2 ,Target time register mode for PPS2" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PPSCMD2 ,Flexible PPS2 output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--14. " TRGTMODSEL1 ,Target time register mode for PPS1" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 8.--10. " PPSCMD1 ,Flexible PPS1 output control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TRGTMODSEL0 ,Target time register mode" "Interrupt only,,Interrupt and PPS Start/Stop,PPS Start/Stop Only"
|
|
bitfld.long 0x00 4. " PPSEN ,Enable the flexible PPS output mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PPSCTL0 ,PPS frequency control (command,BR,DR)" "No command,START Single/2kHz/1kHz,START Pulse/4kHz/2kHz,Cancel START/8kHz/4kHz,STOP Pulse Time/16kHz/8kHz,STOP Pulse Now,Cancel STOP Pulse,?..."
|
|
line.long 0x04 "EMAC0_TM_AUXSTMP_NSEC,EMAC0 Time Stamp Auxiliary TS Nano Seconds Register"
|
|
line.long 0x08 "EMAC0_TM_AUXSTMP_SEC,EMAC0 Time Stamp Auxiliary TM Seconds Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "EMAC0_MAC_AVCTL,EMAC0 AV MAC Control Register"
|
|
bitfld.long 0x00 24.--25. " PTPCH ,Channel for queuing the PTP packets" "0,1,2,?..."
|
|
bitfld.long 0x00 21.--22. " AVCH ,Channel for queuing AV control packets" "0,1,2,?..."
|
|
bitfld.long 0x00 20. " AVCD ,AV channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VQE ,VLAN tagged non-AV packets queuing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " AVP ,AV priority for queuing" "Lowest,1,2,3,4,5,6,Highest"
|
|
hexmask.long.word 0x00 0.--15. 1. " AVT ,AV ether type value"
|
|
endif
|
|
group.long 0x760++0x07
|
|
line.long 0x00 "EMAC0_TM_PPS0INTVL,EMAC0 Time Stamp PPS Interval Register"
|
|
line.long 0x04 "EMAC0_TM_PPS0WIDTH,EMAC0 PPS Width Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x780++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS1TGTM,EMAC0 PPS 1 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS1NTGTM,EMAC0 PPS 1 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS1INTVL,EMAC0 PPS 1 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS1WIDTH,EMAC0 PPS 1 Width Register"
|
|
group.long 0x7A0++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS2TGTM,EMAC0 PPS 2 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS2NTGTM,EMAC0 PPS 2 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS2INTVL,EMAC0 PPS 2 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS2WIDTH,EMAC0 PPS 2 Width Register"
|
|
group.long 0x7C0++0x0F
|
|
line.long 0x00 "EMAC0_TM_PPS3TGTM,EMAC0 PPS 3 Target Time Seconds Register"
|
|
line.long 0x04 "EMAC0_TM_PPS3NTGTM,EMAC0 PPS 3 Target Time Nanoseconds Register"
|
|
bitfld.long 0x04 31. " TSTRBUSY ,Target time register" "Not busy,Busy"
|
|
hexmask.long 0x04 0.--30. 1. " TSTR ,Target time low register"
|
|
line.long 0x08 "EMAC0_TM_PPS3INTVL,EMAC0 PPS 3 Interval Register"
|
|
line.long 0x0C "EMAC0_TM_PPS3WIDTH,EMAC0 PPS 3 Width Register"
|
|
endif
|
|
group.long 0x1000++0x0B
|
|
line.long 0x00 "EMAC0_DMA0_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "EMAC0_DMA0_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA0_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x40020000+0x1018))&0x2)==0x0)
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x1018))&0x2000)==0x0)
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1014++0x03
|
|
line.long 0x00 "EMAC0_DMA0_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GLPII ,GMAC LPI interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
group.long 0x1018++0x07
|
|
line.long 0x00 "EMAC0_DMA0_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x04 "EMAC0_DMA0_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x04 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1020++0x03
|
|
hide.long 0x00 "EMAC0_DMA0_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "EMAC0_DMA0_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "EMAC0_DMA0_BMMODE,EMAC0 DMA SCB Bus Mode Register"
|
|
bitfld.long 0x00 31. " ENLPI ,Enable low power interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " WROSRLMT ,SCB maximum write outstanding request" "1,2,3,4,?..."
|
|
bitfld.long 0x00 16.--18. " RDOSRLMT ,SCB maximum read outstanding request" "1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " ONEKBBE ,1K boundary crossing enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " AAL ,Address aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BLEN16 ,SCB burst length 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BLEN8 ,SCB burst length 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BLEN4 ,SCB burst length 4" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " UNDEF ,SCB undefined burst length" "Fixed,Any"
|
|
rgroup.long 0x102C++0x03
|
|
line.long 0x00 "EMAC0_DMA0_BMSTAT,EMAC0 DMA SCB Status Register"
|
|
bitfld.long 0x00 1. " BUSRD ,Bus (SCB master) read active" "Not active,Active"
|
|
bitfld.long 0x00 0. " BUSWR ,Bus (SCB master) write active" "Not active,Active"
|
|
rgroup.long 0x1048++0x0F
|
|
line.long 0x00 "EMAC0_DMA0_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA0_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA0_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA0_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
group.long 0x1100++0x0B
|
|
line.long 0x00 "EMAC0_DMA1_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EMAC0_DMA1_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA1_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x40020000+0x1118))&0x2)==0x00)
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x1118))&0x2000)==0x00)
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1114++0x0B
|
|
line.long 0x00 "EMAC0_DMA1_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GTMSI ,MAC TMS interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "EMAC0_DMA1_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x04 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x04 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x04 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x04 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x04 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x08 "EMAC0_DMA1_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x08 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1120++0x03
|
|
hide.long 0x00 "EMAC0_DMA1_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "EMAC0_DMA1_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "EMAC0_DMA1_CHSFCS,EMAC0 Channel 1 Control Bits For Slot Function Register"
|
|
rbitfld.long 0x00 16.--19. " RSN ,Reference slot number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " ASC ,Advance slot check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ESC ,Enable slot comparison" "Disabled,Enabled"
|
|
rgroup.long 0x1148++0x0F
|
|
line.long 0x00 "EMAC0_DMA1_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA1_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA1_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA1_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "EMAC0_DMA1_CHCBSCTL,EMAC0 Channel 1 Credit Shaping Control Register"
|
|
bitfld.long 0x00 17. " ABPSSIE ,Average bits per slot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SLC ,Slot count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " CC ,Credit control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CBSD ,Credit based shaper disable" "No,Yes"
|
|
hgroup.long 0x1164++0x03
|
|
hide.long 0x00 "EMAC0_DMA1_CHCBSSTAT,EMAC0 Channel 1 Average Traffic Transmitted Register"
|
|
in
|
|
group.long 0x1168++0x0F
|
|
line.long 0x00 "EMAC0_DMA1_CHISC,EMAC0 Channel 1 Idle Slope Credit Value Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle slope credit"
|
|
line.long 0x04 "EMAC0_DMA1_CHSSC,EMAC0 Channel 1 Send Slope Credit Value Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " SSC ,Send slope credit"
|
|
line.long 0x08 "EMAC0_DMA1_CHHIC,EMAC0 Channel 1 High Credit Value Register"
|
|
hexmask.long 0x08 0.--28. 1. " HC ,High credit"
|
|
line.long 0x0C "EMAC0_DMA1_CHLOC,EMAC0 Channel 1 Low Credit Value Register"
|
|
hexmask.long 0x0C 0.--28. 1. " LC ,Low credit"
|
|
group.long 0x1200++0x0B
|
|
line.long 0x00 "EMAC0_DMA2_BUSMODE,EMAC0 DMA Bus Mode Register"
|
|
bitfld.long 0x00 25. " AAL ,Address aligned bursts" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PBL8 ,PBL * 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RPBL ,Receive programmable burst length" ",1,2,,4,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATDS ,Alternate descriptor size" "16 bytes,32 bytes"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x04 "EMAC0_DMA2_TXPOLL,EMAC0 DMA Tx Poll Demand Register"
|
|
line.long 0x08 "EMAC0_DMA2_RXPOLL,EMAC0 DMA Rx Poll Demand Register"
|
|
if (((per.l(ad:0x40020000+0x1218))&0x2)==0x00)
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x1218))&0x2000)==0x00)
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
else
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register"
|
|
endif
|
|
group.long 0x1214++0x0B
|
|
line.long 0x00 "EMAC0_DMA2_STAT,EMAC0 DMA Status Register"
|
|
rbitfld.long 0x00 30. " GTMSI ,MAC TMS interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " TTI ,Time stamp trigger interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 27. " MCI ,MAC MMC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " GLI ,Line interface interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 23.--25. " EB ,Error bits" "Data buffer/write/RxDMA,Data buffer/write/TxDMA,Data buffer/read/RxDMA,Data buffer/read/TxDMA,Descriptor/write/RxDMA,Descriptor/write/TxDMA,Descriptor/read/RxDMA,Descriptor/read/TxDMA"
|
|
rbitfld.long 0x00 20.--22. " TS ,Tx process state" "Stopped,Fetching,Waiting,Reading data,TIME_STAMP write,,Suspended,Closing descriptor"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " RS ,Rx process state" "Stopped,Fetching,,Waiting,Suspended,Closing descriptor,TIME_STAMP write,Packed data transfer"
|
|
eventfld.long 0x00 16. " NIS ,Normal interrupt summary" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " AIS ,Abnormal interrupt summary" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ERI ,Early receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " FBI ,Fatal bus error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ETI ,Early transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RWT ,Receive watchdog timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 8. " RPS ,Receive process stopped" "Not stopped,Stopped"
|
|
eventfld.long 0x00 7. " RU ,Receive buffer unavailable" "Available,Unavailable"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RI ,Receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " UNF ,Transmit buffer underflow" "No underflow,Underflow"
|
|
eventfld.long 0x00 4. " OVF ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TJT ,Transmit jabber timeout" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " TU ,Transmit buffer unavailable" "Available,Unavailable"
|
|
eventfld.long 0x00 1. " TPS ,Transmit process stopped" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TI ,Transmit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "EMAC0_DMA2_OPMODE,EMAC0 DMA Operation Mode Register"
|
|
bitfld.long 0x04 26. " DT ,Disable dropping TCP/IP errors" "No,Yes"
|
|
bitfld.long 0x04 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DFF ,Disable flushing of received frames" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 21. " TSF ,Transmit store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " FTF ,Flush transmit FIFO" "No flush,Flush"
|
|
bitfld.long 0x04 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x04 7. " FEF ,Forward error frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FUF ,Forward undersized good frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DGF ,Drop gaint frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x04 2. " OSF ,Operate on second frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
line.long 0x08 "EMAC0_DMA2_IEN,EMAC0 DMA Interrupt Enable Register"
|
|
bitfld.long 0x08 16. " NIE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " AIE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ERE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " FBE ,Fatal bus error enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ETE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " RWE ,Receive watchdog timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " RSE ,Receive stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RUE ,Receive buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UNE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OVE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TJE ,Transmit jabber timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TUE ,Transmit buffer unavailable enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TSE ,Transmit stopped enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1220++0x03
|
|
hide.long 0x00 "EMAC0_DMA2_MISS_FRM,EMAC0 DMA Missed Frame Register"
|
|
in
|
|
group.long 0x1224++0x03
|
|
line.long 0x00 "EMAC0_DMA2_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI watchdog timer count"
|
|
group.long 0x1230++0x03
|
|
line.long 0x00 "EMAC0_DMA2_CHSFCS,EMAC0 Channel 2 Control Bits For Slot Function Register"
|
|
rbitfld.long 0x00 16.--19. " RSN ,Reference slot number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " ASC ,Advance slot check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ESC ,Enable slot comparison" "Disabled,Enabled"
|
|
rgroup.long 0x1248++0x0F
|
|
line.long 0x00 "EMAC0_DMA2_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register"
|
|
line.long 0x04 "EMAC0_DMA2_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register"
|
|
line.long 0x08 "EMAC0_DMA2_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register"
|
|
line.long 0x0C "EMAC0_DMA2_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "EMAC0_DMA2_CHCBSCTL,EMAC0 Channel 2 Credit Shaping Control Register"
|
|
bitfld.long 0x00 17. " ABPSSIE ,Average bits per slot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SLC ,Slot count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " CC ,Credit control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CBSD ,Credit based shaper disable" "No,Yes"
|
|
hgroup.long 0x1264++0x03
|
|
hide.long 0x00 "EMAC0_DMA2_CHCBSSTAT,EMAC0 Channel 2 Avg Traffic Transmitted Status Register"
|
|
in
|
|
group.long 0x1268++0x0F
|
|
line.long 0x00 "EMAC0_DMA2_CHISC,EMAC0 Channel 2 Idle Slope Credit Value Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle slope credit"
|
|
line.long 0x04 "EMAC0_DMA2_CHSSC,EMAC0 Channel 2 Send Slope Credit Value Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " SSC ,Send slope credit"
|
|
line.long 0x08 "EMAC0_DMA2_CHHIC,EMAC0 Channel 2 High Credit Value Register"
|
|
hexmask.long 0x08 0.--28. 1. " HC ,High credit"
|
|
line.long 0x0C "EMAC0_DMA2_CHLOC,EMAC0 Channel 2 Low Credit Value Register"
|
|
hexmask.long 0x0C 0.--28. 1. " LC ,Low credit"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x4002A000
|
|
if (((per.l(ad:0x4002A000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002A000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x4002A000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI0_CTL,SPI0 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x4002A000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI0_RXCTL,SPI0 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI0_TXCTL,SPI0 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI0_RXCTL,SPI0 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI0_TXCTL,SPI0 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI0_CLK,SPI0 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI0_DLY,SPI0 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI0_SLVSEL,SPI0 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI0_RWC,SPI0 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI0_RWCR,SPI0 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI0_TWC,SPI0 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI0_TWCR,SPI0 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI0_IMSK,SPI0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI0_STAT,SPI0 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI0_ILAT,SPI0 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI0_ILAT_CLR,SPI0 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI0_ILAT_CLR,SPI0 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI0_RFIFO,SPI0 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI0_TFIFO,SPI0 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI0_MMRDH,SPI0 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI0_MMTOP,SPI0 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x4002B000
|
|
if (((per.l(ad:0x4002B000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002B000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x4002B000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI1_CTL,SPI1 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x4002B000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI1_RXCTL,SPI1 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI1_TXCTL,SPI1 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI1_RXCTL,SPI1 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI1_TXCTL,SPI1 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI1_CLK,SPI1 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI1_DLY,SPI1 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI1_SLVSEL,SPI1 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI1_RWC,SPI1 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI1_RWCR,SPI1 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI1_TWC,SPI1 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI1_TWCR,SPI1 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI1_IMSK,SPI1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI1_STAT,SPI1 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI1_ILAT,SPI1 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI1_ILAT_CLR,SPI1 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI1_ILAT_CLR,SPI1 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI1_RFIFO,SPI1 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI1_TFIFO,SPI1 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI1_MMRDH,SPI1 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI1_MMTOP,SPI1 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x4002C000
|
|
if (((per.l(ad:0x4002C000+0x04))&0x2003)==0x00)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x00)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2000)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2000)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x02)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x02)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2002)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2002)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
bitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x01)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x01)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FCWM ,Flow control watermark" "TFIFO empty or RFIFO full,75% or more,50% or more,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FCCH ,Flow control channel selection" "RX buffer,TX buffer"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2001)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2001)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMISO ,Enable MISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x03)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x03)
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x4002C000+0x04))&0x2003)==0x2003)&&(((per.l(ad:0x4002C000+0x04))&0x300000)==(0x100000||0x200000))
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOSI ,Start on MOSI" "MISO/SPIQ,MOSI"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI2_CTL,SPI2 Control Register"
|
|
bitfld.long 0x00 31. " MMSE ,Memory-mapped SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MMWEM ,Memory mapped write error mask" "Unmasked,Masked"
|
|
textline " "
|
|
sif (cpuis("ADSPCM40*"))
|
|
rbitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O mode" "Disabled,DIOM,QIOM,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FMODE ,Fast-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 15. " FCPL ,Flow control polarity" "Active-low,Active-high"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13. " FCEN ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " LSBF ,Least significant bit first" "MSB first,LSB first"
|
|
rbitfld.long 0x00 9.--10. " SIZE ,Word transfer size" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " SELST ,Slave select polarity between transfers" "Deasserted,Asserted"
|
|
bitfld.long 0x00 6. " ASSEL ,Slave select pin control" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
rbitfld.long 0x00 4. " CPHA ,Clock phase" "Toggle CLK from middle,Toggle CLK from start"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ODM ,Open drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSSE ,Protected slave select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTR ,Master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,Enable SPI operation" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 15.
|
|
if (((per.l(ad:0x4002C000+0x04))&0x02)==0x02)
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI2_RXCTL,SPI2 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " RWCEN ,Receive word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTI ,Receive transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI2_TXCTL,SPI2 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. " TWCEN ,Transmit word counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TTI ,Transmit transfer initiate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPI2_RXCTL,SPI2 Receive Control Register"
|
|
bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO urgent watermark" "Disabled,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO regular watermark" "Empty RFIFO,RFIFO less than 25% full,RFIFO less than 50% full,RFIFO less than 75% full"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDO ,Receive data overrun" "Discard,Overwrite"
|
|
bitfld.long 0x00 4.--6. " RDR ,Receive data request" "Disabled,Not empty RFIFO,25% full RFIFO,50% full RFIFO,75% full RFIFO,Full RFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI2_TXCTL,SPI2 Transmit Control Register"
|
|
bitfld.long 0x04 16.--18. " TUWM ,FIFO urgent watermark" "Disabled,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,empty TFIFO,?..."
|
|
bitfld.long 0x04 12.--13. " TRWM ,FIFO regular watermark" "Full TFIFO,TFIFO less than 25% empty,TFIFO less than 50% empty,TFIFO less than 75% empty"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TDU ,Transmit data under-run (handling transmit requests when the TFIFO buffer is empty)" "Send last word,Send zeros"
|
|
bitfld.long 0x04 4.--6. " TDR ,Transmit data request" "Disabled,Not full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEN ,Transmit enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPI2_CLK,SPI2 Clock Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate"
|
|
line.long 0x04 "SPI2_DLY,SPI2 Delay Register"
|
|
bitfld.long 0x04 9. " LAGX ,Extended SPI clock lag control" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LEADX ,Extended SPI clock lead control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STOP ,Transfer delay time in multiples of SPI clock period"
|
|
line.long 0x08 "SPI2_SLVSEL,SPI2 Slave Select Register"
|
|
bitfld.long 0x08 15. " SSEL7 ,Slave select 7 input" "Low,High"
|
|
bitfld.long 0x08 14. " SSEL6 ,Slave select 6 input" "Low,High"
|
|
bitfld.long 0x08 13. " SSEL5 ,Slave select 5 input" "Low,High"
|
|
bitfld.long 0x08 12. " SSEL4 ,Slave select 4 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SSEL3 ,Slave select 3 input" "Low,High"
|
|
bitfld.long 0x08 10. " SSEL2 ,Slave select 2 input" "Low,High"
|
|
bitfld.long 0x08 9. " SSEL1 ,Slave select 1 input" "Low,High"
|
|
bitfld.long 0x08 7. " SSE7 ,Slave select 7 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SSE6 ,Slave Select 6 Enable" "Low,High"
|
|
bitfld.long 0x08 5. " SSE5 ,Slave select 5 enable" "Low,High"
|
|
bitfld.long 0x08 4. " SSE4 ,Slave select 4 enable" "Low,High"
|
|
bitfld.long 0x08 3. " SSE3 ,Slave select 3 enable" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SSE2 ,Slave select 2 enable" "Low,High"
|
|
bitfld.long 0x08 1. " SSE1 ,Slave select 1 enable" "Low,High"
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "SPI2_RWC,SPI2 Received Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received word count"
|
|
line.long 0x04 "SPI2_RWCR,SPI2 Received Word Count Reload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Received word count reload"
|
|
line.long 0x08 "SPI2_TWC,SPI2 Transmitted Word Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Transmitted word count"
|
|
line.long 0x0C "SPI2_TWCR,SPI2 Transmitted Word Count Reload Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " VALUE ,Transmitted word count reload"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI2_IMSK,SPI2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " TF ,Transmit finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " RF ,Receive finish" "Unmasked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " TS ,Transmit start" "Unmasked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RS ,Receive start" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " MF ,Mode fault" "Unmasked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TC ,Transmit collision" "Unmasked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TUR ,Transmit under run" "Unmasked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ROR ,Receive overrun" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TUWM ,Transmit urgent watermark" "Unmasked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RUWM ,Receive urgent watermark" "Unmasked,Masked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI2_STAT,SPI2 Status Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
eventfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
eventfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 31. " MMAE ,Memory mapped access error" "No error,Error"
|
|
bitfld.long 0x00 29. " MMRE ,Memory mapped read error" "No error,Error"
|
|
bitfld.long 0x00 28. " MMWE ,Memory mapped write error" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " TFF ,SPI_TFIFO full" "Not full Tx FIFO,Full Tx FIFO"
|
|
bitfld.long 0x00 22. " RFE ,SPI_RFIFO empty" "RX FIFO Not empty,RX FIFO Empty"
|
|
bitfld.long 0x00 20. " FCS ,Flow control stall indication" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO status" "Full TFIFO,25% empty TFIFO,50% empty TFIFO,75% empty TFIFO,Empty TFIFO,?..."
|
|
bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO status" "Full TFIFO,25% empty RFIFO,50% empty RFIFO,75% empty RFIFO,Empty RFIFO,?..."
|
|
sif (cpuis("ADSP-SC57*"))
|
|
eventfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
eventfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
eventfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
eventfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
eventfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
eventfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
eventfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
eventfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
else
|
|
bitfld.long 0x00 11. " TF ,Transmit finish indication" "No status,TX finish detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RF ,Receive finish indication" "No status,RX finish detected"
|
|
bitfld.long 0x00 9. " TS ,Transmit start" "No status,TX start detected"
|
|
bitfld.long 0x00 8. " RS ,Receive start" "No status,RX start detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MF ,Mode fault indication" "No status,Mode fault"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision indication" "No status,Transmit collision"
|
|
bitfld.long 0x00 5. " TUR ,Transmit Under run indication" "No status,Transmit underrun"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun indication" "No status,Receive Overrun"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark breached" "TX Regular Watermark reached,TX Urgent Watermark breached"
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark breached" "RX Regular Watermark reached,RX Urgent Watermark breached"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIF ,SPI (single word transfer) finished" "No status,Transfer completed"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPI2_ILAT,SPI2 Masked Interrupt Condition Register"
|
|
bitfld.long 0x00 11. " TF ,Transmit finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 10. " RF ,Receive finish interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 9. " TS ,Transmit start interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Receive start interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 7. " MF ,Mode fault interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 6. " TC ,Transmit collision interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Transmit under-run interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 4. " ROR ,Receive overrun interrupt latch" "No interrupt,Latched interrupt"
|
|
bitfld.long 0x00 2. " TUWM ,Transmit urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Receive urgent watermark interrupt latch" "No interrupt,Latched interrupt"
|
|
sif (cpuis("ADSP-SC587*")||cpuis("ADSPCM40"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI2_ILAT_CLR,SPI2 Masked Interrupt Clear Register"
|
|
eventfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
eventfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI2_ILAT_CLR,SPI2 Masked Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " TF ,Clear transmit finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RF ,Clear receive finish interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 9. " TS ,Clear transmit start interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RS ,Clear receive start interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 7. " MF ,Clear mode fault interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TC ,Clear transmit collision interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TUR ,Clear transmit under-run interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ROR ,Clear receive overrun interrupt latch" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TUWM ,Clear transmit urgent watermark interrupt latch" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RUWM ,Clear receive urgent watermark interrupt latch" "No effect,Clear"
|
|
endif
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SPI2_RFIFO,SPI2 Receive FIFO Data Register"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI2_TFIFO,SPI2 Transmit FIFO Data Register"
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI2_MMRDH,SPI2 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI2_MMTOP,SPI2 SPI Memory Top Address"
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SPI2_MMRDH,SPI2 Memory Mapped Read Header"
|
|
bitfld.long 0x00 29. " CMDPINS ,Pins used for command" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 28. " CMDSKIP ,Command skip mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " WRAP ,SPI memory wrap indicator (SPI Memory auto increments address but wraps within 32 Byte lines)" "Not wrapped,Wrapped"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MERGE ,Merge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " TRIDMY ,Tristate dummy timing" "Immediately,After 4 bits,After 8 bits,Never"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode field"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of dummy/mode" "0 Bytes,1 Byte,2 Bytes,3 Bytes,4 Bytes,5 Bytes,6 Bytes,7 Bytes"
|
|
bitfld.long 0x00 11. " ADRPINS ,Pins used for address" "Use only one pin (MOSI),Use pins specified by MIOM"
|
|
bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of read address" "1 Byte,1 Byte,2 Bytes,3 Bytes,4 Bytes,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read opcode"
|
|
line.long 0x04 "SPI2_MMTOP,SPI2 SPI Memory Top Address"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPORT (Serial Port)"
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F"))
|
|
tree "SPORT0"
|
|
base ad:0x40001000
|
|
tree.end
|
|
tree "SPORT1"
|
|
base ad:0x40001100
|
|
width 20.
|
|
if ((((per.l(ad:0x40001100+0x0))&0x6800)==0x800)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x0))&0x4800)==0x00)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40001100+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT1_DIV_A,SPORT1 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT1_MCTL_A,SPORT1 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT1_CS0_A,SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT1_CS1_A,SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT1_CS2_A,SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT1_CS3_A,SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT1_ERR_A,SPORT1 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT1_MSTAT_A,SPORT1 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT1_CTL2_A,SPORT1 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT1_TXPRI_A,SPORT1 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT1_RXPRI_A,SPORT1 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT1_TXSEC_A,SPORT1 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT1_RXSEC_A,SPORT1 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SPORT0"
|
|
base ad:0x40001000
|
|
width 20.
|
|
if ((((per.l(ad:0x40001000+0x0))&0x6800)==0x800)&&(((per.l(ad:0x40001000+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001000+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x40001000+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001000+0x0))&0x4800)==0x00)&&(((per.l(ad:0x40001000+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40001000+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT0_DIV_A,SPORT0 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT0_MCTL_A,SPORT0 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT0_CS0_A,SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT0_CS1_A,SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT0_CS2_A,SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT0_CS3_A,SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT0_ERR_A,SPORT0 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT0_MSTAT_A,SPORT0 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT0_CTL2_A,SPORT0 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT0_TXPRI_A,SPORT0 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT0_RXPRI_A,SPORT0 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT0_TXSEC_A,SPORT0 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT0_RXSEC_A,SPORT0 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x40001000+0x80))&0x6800)==0x800)&&(((per.l(ad:0x40001000+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001000+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x40001000+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001000+0x80))&0x4800)==0x00)&&(((per.l(ad:0x40001000+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40001000+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT0_DIV_B,SPORT0 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT0_MCTL_B,SPORT0 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT0_CS0_B,SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT0_CS1_B,SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT0_CS2_B,SPORT0 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT0_CS3_B,SPORT0 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT0_ERR_B,SPORT0 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT0_MSTAT_B,SPORT0 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT0_CTL2_B,SPORT0 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT0_TXPRI_B,SPORT0 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT0_RXPRI_B,SPORT0 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT0_TXSEC_B,SPORT0 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT0_RXSEC_B,SPORT0 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPORT1"
|
|
base ad:0x40001100
|
|
width 20.
|
|
if ((((per.l(ad:0x40001100+0x0))&0x6800)==0x800)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x0))&0x6800)==0x2800)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x00))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x0))&0x4800)==0x00)&&(((per.l(ad:0x40001100+0x0+0x08))&0x01)==0x01))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40001100+0x0))&0x204800)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "SPORT1_DIV_A,SPORT1 Half SPORT 'A' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT1_MCTL_A,SPORT1 Half SPORT 'A' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "SPORT1_CS0_A,SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT1_CS1_A,SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT1_CS2_A,SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT1_CS3_A,SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x0+0x20)++0x03
|
|
line.long 0x00 "SPORT1_ERR_A,SPORT1 Half SPORT 'A' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x0+0x24)++0x03
|
|
line.long 0x00 "SPORT1_MSTAT_A,SPORT1 Half SPORT 'A' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x0+0x28)++0x03
|
|
line.long 0x00 "SPORT1_CTL2_A,SPORT1 Half SPORT 'A' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x0+0x40)++0x03
|
|
line.long 0x00 "SPORT1_TXPRI_A,SPORT1 Half SPORT 'A' Tx Buffer (primary) Register"
|
|
hgroup.long (0x0+0x44)++0x03
|
|
hide.long 0x00 "SPORT1_RXPRI_A,SPORT1 Half SPORT 'A' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x0+0x48)++0x03
|
|
line.long 0x00 "SPORT1_TXSEC_A,SPORT1 Half SPORT 'A' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x0+0x4C)++0x03
|
|
hide.long 0x00 "SPORT1_RXSEC_A,SPORT1 Half SPORT 'A' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
if ((((per.l(ad:0x40001100+0x80))&0x6800)==0x800)&&(((per.l(ad:0x40001100+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Right,Left"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x80))&0x6800)==0x2800)&&(((per.l(ad:0x40001100+0x80+0x08))&0x01)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " OPMODE2 ,OPMODE2" "I2S,Left-justified"
|
|
bitfld.long 0x00 16. " L_FIRST ,L_FIRST" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0x40001100+0x80))&0x4800)==0x00)&&(((per.l(ad:0x40001100+0x80+0x08))&0x01)==0x01))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,PLFS" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40001100+0x80))&0x204800)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Normal operation,,Compress Micro-law,Compress A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register"
|
|
rbitfld.long 0x00 30.--31. " DXSPRI ,Data transfer buffer status (primary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 29. " DERRPRI ,Data error status (primary)" "No error,Error"
|
|
rbitfld.long 0x00 27.--28. " DXSSEC ,Data transfer buffer status (secondary)" "Empty,,Partially full,Full"
|
|
rbitfld.long 0x00 26. " DERRSEC ,Data error status (secondary)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPTRAN ,Serial port transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 24. " SPENSEC ,Serial port enable (secondary)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " GCLKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TFIEN ,Transmit finish interrupt enable" "Last word interrupt,Last bit interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FSED ,Frame sync edge detect" "Level,Edge"
|
|
bitfld.long 0x00 18. " RJUST ,Right-Justified operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " LAFS ,Late frame sync" "Early,Late"
|
|
bitfld.long 0x00 16. " LFS ,Active-Low frame sync" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFS ,Data-Independent frame sync" "Data-dependent,Data-independent"
|
|
bitfld.long 0x00 14. " IFS ,Internal frame sync" "External,Internal"
|
|
bitfld.long 0x00 13. " FSR ,Frame sync required" "No frame,Frame"
|
|
bitfld.long 0x00 12. " CKRE ,Clock rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPMODE ,Operation mode" "DSP standard/multi-channel,I2s/packed/left-justified"
|
|
bitfld.long 0x00 10. " ICLK ,Internal clock" "External,Internal"
|
|
bitfld.long 0x00 9. " PACK ,Packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--8. " SLEN ,Serial word length" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LSBF ,Least-Significant bit first" "Low,High"
|
|
bitfld.long 0x00 1.--2. " DTYPE ,Data type" "Right-justify 0,Right-justify 1,Micro-law compand,A-law compand"
|
|
bitfld.long 0x00 0. " SPENPRI ,Serial port enable (primary)" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "SPORT1_DIV_B,SPORT1 Half SPORT 'B' Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame sync divisor"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divisor"
|
|
line.long 0x04 "SPORT1_MCTL_B,SPORT1 Half SPORT 'B' Multi-channel Control Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " WOFFSET ,Window offset"
|
|
hexmask.long.byte 0x04 8.--14. 1. " WSIZE ,Window size"
|
|
bitfld.long 0x04 4.--7. " MFD ,Multi-channel frame delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MCPDE ,Multi-Channel packing DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MCE ,Multichannel enable" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "SPORT1_CS0_B,SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register"
|
|
bitfld.long 0x00 31. " CH[31] ,Channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPORT1_CS1_B,SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register"
|
|
bitfld.long 0x04 31. " CH[63] ,Channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Channel 62 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " [59] ,Channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,Channel 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " [55] ,Channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Channel 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,Channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,Channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Channel 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,Channel 48 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " [47] ,Channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Channel 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [43] ,Channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Channel 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,Channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,Channel 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [35] ,Channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Channel 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [33] ,Channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPORT1_CS2_B,SPORT1 Half SPORT 'B' Multi-channel 64-95 Select Register"
|
|
bitfld.long 0x08 31. " CH[95] ,Channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Channel 94 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [91] ,Channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,Channel 90 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [87] ,Channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Channel 86 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,Channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,Channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Channel 82 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,Channel 80 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [79] ,Channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Channel 78 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [75] ,Channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Channel 74 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,Channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,Channel 70 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [67] ,Channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Channel 66 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,Channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x0C "SPORT1_CS3_B,SPORT1 Half SPORT 'B' Multi-channel 96-127 Select Register"
|
|
bitfld.long 0x0C 31. " CH[127] ,Channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Channel 126 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [123] ,Channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,Channel 122 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [119] ,Channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Channel 118 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,Channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,Channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Channel 114 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,Channel 112 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [111] ,Channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Channel 110 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [107] ,Channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Channel 106 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,Channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,Channel 102 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [99] ,Channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Channel 98 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,Channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Channel 96 enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long (0x80+0x20)++0x03
|
|
line.long 0x00 "SPORT1_ERR_B,SPORT1 Half SPORT 'B' Error Register"
|
|
sif cpuis("ADSP-SC57?")
|
|
eventfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
eventfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
eventfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 6. " FSERRSTAT ,Frame sync error status" "No error,Error"
|
|
bitfld.long 0x00 5. " DERRSSTAT ,Data error secondary status" "No error,Error"
|
|
bitfld.long 0x00 4. " DERRPSTAT ,Data error primary status" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSERRMSK ,Frame sync error (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " DERRSMSK ,Data error secondary (interrupt) mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " DERRPMSK ,Data error primary (interrupt) mask" "Masked,Unmasked"
|
|
rgroup.long (0x80+0x24)++0x03
|
|
line.long 0x00 "SPORT1_MSTAT_B,SPORT1 Half SPORT 'B' Multi-channel Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current channel"
|
|
group.long (0x80+0x28)++0x03
|
|
line.long 0x00 "SPORT1_CTL2_B,SPORT1 Half SPORT 'B' Control 2 Register"
|
|
bitfld.long 0x00 1. " CKMUXSEL ,Clock multiplexer select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSMUXSEL ,Frame sync multiplexer select" "Disabled,Enabled"
|
|
group.long (0x80+0x40)++0x03
|
|
line.long 0x00 "SPORT1_TXPRI_B,SPORT1 Half SPORT 'B' Tx Buffer (primary) Register"
|
|
hgroup.long (0x80+0x44)++0x03
|
|
hide.long 0x00 "SPORT1_RXPRI_B,SPORT1 Half SPORT 'B' Rx Buffer (primary) Register"
|
|
in
|
|
group.long (0x80+0x48)++0x03
|
|
line.long 0x00 "SPORT1_TXSEC_B,SPORT1 Half SPORT 'B' Tx Buffer (secondary) Register"
|
|
hgroup.long (0x80+0x4C)++0x03
|
|
hide.long 0x00 "SPORT1_RXSEC_B,SPORT1 Half SPORT 'B' Rx Buffer (secondary) Register"
|
|
in
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "ADCC (Analog-to-Digital Converter Controller)"
|
|
base ad:0x4000E000
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTL,ADCC Control Register"
|
|
bitfld.long 0x00 29. " TRGIE1 ,Trigger input enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TRGIE0 ,Trigger input enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ADCFG ,ADC interface configuration" "No action,Start ADC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LSBF1 ,LSB first 1" "MSB mode,LSB mode"
|
|
bitfld.long 0x00 24. " LSBF0 ,LSB first 0" "MSB mode,LSB mode"
|
|
bitfld.long 0x00 23. " DSWP1 ,Data swap 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DSWP0 ,Data swap 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TIDLE1 ,Transmit idle 1" "Low,High"
|
|
bitfld.long 0x00 20. " TIDLE0 ,Transmit idle 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSPOL1 ,Chip select polarity 1" "Low,High"
|
|
bitfld.long 0x00 18. " CSPOL0 ,Chip select polarity 0" "Low,High"
|
|
bitfld.long 0x00 17. " CKPOL1 ,Clock polarity 1" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CKPOL0 ,Clock polarity 0" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 15. " TRGPOL1 ,Trigger polarity 1" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12.--14. " TRGSEL1 ,Trigger select 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TRGPOL0 ,Trigger polarity 0" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 8.--10. " TRGSEL0 ,Trigger select 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " TRGOE1 ,Trigger output enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRGOE0 ,Trigger output enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSIZE ,Data size" "1bit,2bit"
|
|
bitfld.long 0x00 4. " CSIZE ,Control data size" "1bit,2bit"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TMR1EN ,Timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable ADCC operation" "Disabled,Enabled"
|
|
line.long 0x04 "ERRSTAT,Error Status Register"
|
|
rbitfld.long 0x04 7. " EMIS ,Event miss error status" "No error,Error"
|
|
rbitfld.long 0x04 6. " ECOL ,Event collision error status" "No error,Error"
|
|
eventfld.long 0x04 5. " MERR1 ,Memory response error 1 status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 4. " MERR0 ,Memory response error 0 status" "No error,Error"
|
|
eventfld.long 0x04 3. " BWERR1 ,Bandwidth monitor error 1 status" "No error,Error"
|
|
eventfld.long 0x04 2. " BWERR0 ,Bandwidth monitor error 0 status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " TRGOV1 ,Trigger overrun 1 status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " TRGOV0 ,Trigger overrun 0 status" "Not occurred,Occurred"
|
|
line.long 0x08 "ERRMSK,Error Mask Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " EMIS ,Event miss error" "Unmasked,Masked"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " ECOL ,Event collision error mask" "Unmasked,Masked"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " MERR1 ,Memory response error 1 mask" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " MERR0 ,Memory response error 0 mask" "Unmasked,Masked"
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " BWERR1 ,Bandwidth monitor error 1 mask" "Unmasked,Masked"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " BWERR0 ,Bandwidth monitor error 0 mask" "Unmasked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " TRGOV1 ,Trigger overrun 1 error mask" "Unmasked,Masked"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " TRGOV0 ,Trigger overrun 0 error mask" "Unmasked,Masked"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "EISTAT,Event Interrupt Status Register"
|
|
eventfld.long 0x00 23. " EVT[23] ,Event 23 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Event 22 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Event 21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " [20] ,Event 20 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " [19] ,Event 19 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Event 18 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " [17] ,Event 17 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [16] ,Event 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Event 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " [14] ,Event 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Event 13 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Event 12 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Event 11 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Event 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Event 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " [8] ,Event 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Event 7 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Event 6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " [5] ,Event 5 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Event 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,Event 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " [2] ,Event 2 Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Event 1 Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Event 0 Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "EIMSK,Event Interrupt Mask Register"
|
|
setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " EVT[23] ,Event 23 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Event 22 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Event 21 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Event 20 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,Event 19 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,Event 18 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,Event 17 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,Event 16 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,Event 15 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,Event 14 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,Event 13 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,Event 12 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,Event 11 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,Event 10 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 9. 0x08 9. 0x0C 9. " [9] ,Event 9 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 8. 0x08 8. 0x0C 8. " [8] ,Event 8 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " [7] ,Event 7 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " [6] ,Event 6 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " [5] ,Event 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " [4] ,Event 4 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " [3] ,Event 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " [2] ,Event 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " [1] ,Event 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " [0] ,Event 0 interrupt mask" "Not masked,Masked"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "FISTAT,Frame Interrupt Status Register"
|
|
eventfld.long 0x00 1. " FINT1 ,Frame interrupt 1" "No interrupted,Interrupted"
|
|
eventfld.long 0x00 0. " FINT0 ,Frame interrupt 0" "No interrupted,Interrupted"
|
|
line.long 0x04 "FIMSK,Frame Interrupt Mask Register"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " FINT1 ,Frame Interrupt 1 mask" "Not masked,Masked"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " FINT0 ,Frame interrupt 0 mask" "Not masked,Masked"
|
|
group.long 0x034++0x03
|
|
line.long 0x00 "EVTEN,Event Enable Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " EVT[23] ,Event 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Event 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Event 21 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Event 20 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Event 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Event 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Event 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Event 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Event 15 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Event 14 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Event 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Event 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Event 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Event 10 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Event 9 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Event 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Event 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Event 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Event 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Event 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Event 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Event 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Event 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Event 0 enable" "Disabled,Enabled"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "ECOL,Event Collision Status Register"
|
|
eventfld.long 0x00 23. " EVT[23] ,Event 23 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " [22] ,Event 22 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " [21] ,Event 21 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 20. " [20] ,Event 20 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " [19] ,Event 19 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " [18] ,Event 18 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " [17] ,Event 17 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " [16] ,Event 16 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 15. " [15] ,Event 15 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " [14] ,Event 14 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " [13] ,Event 13 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " [12] ,Event 12 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,Event 11 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " [10] ,Event 10 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " [9] ,Event 9 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " [8] ,Event 8 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " [7] ,Event 7 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " [6] ,Event 6 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " [5] ,Event 5 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " [4] ,Event 4 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " [3] ,Event 3 collision status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " [2] ,Event 2 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Event 1 collision status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " [0] ,Event 0 collision status" "Not occurred,Occurred"
|
|
line.long 0x04 "EMISS,Event Miss Status Register"
|
|
eventfld.long 0x04 23. " EVT[23] ,Event 23 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 22. " [22] ,Event 22 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 21. " [21] ,Event 21 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 20. " [20] ,Event 20 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 19. " [19] ,Event 19 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 18. " [18] ,Event 18 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 17. " [17] ,Event 17 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 16. " [16] ,Event 16 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 15. " [15] ,Event 15 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 14. " [14] ,Event 14 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 13. " [13] ,Event 13 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " [12] ,Event 12 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " [11] ,Event 11 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 10. " [10] ,Event 10 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 9. " [9] ,Event 9 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 8. " [8] ,Event 8 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 7. " [7] ,Event 7 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " [6] ,Event 6 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 5. " [5] ,Event 5 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " [4] ,Event 4 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " [3] ,Event 3 miss status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 2. " [2] ,Event 2 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " [1] ,Event 1 miss status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " [0] ,Event 0 miss status" "Not occurred,Occurred"
|
|
group.long 0x48++0xB
|
|
line.long 0x00 "BPTR0,Base Pointer 0 Register"
|
|
line.long 0x04 "FRINC0,Frame Increment 0 Register"
|
|
line.long 0x08 "CBSIZ0,Circular Buffer Size 0 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Circular buffer size 0 value"
|
|
if (((per.l(ad:0x4000E000))&0x20)==0x20)
|
|
group.long (0x48+0x0C)++0x03
|
|
line.long 0x00 "TCA0,Timing Control A (ADC0) Register"
|
|
bitfld.long 0x00 16.--19. " NCK ,Number of clocks" ",1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor buffer size 0 value"
|
|
else
|
|
group.long (0x48+0x0C)++0x03
|
|
line.long 0x00 "TCA0,Timing Control A (ADC0) Register"
|
|
bitfld.long 0x00 16.--19. " NCK ,Number of clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor buffer size 0 value"
|
|
endif
|
|
group.long (0x48+0x10)++0x07
|
|
line.long 0x00 "TCB0,Timing Control B (ADC0) Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCSCS ,Timing CS to CS delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TCKCS ,Time CK to CS hold"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCSCK ,Time CS to CK setup"
|
|
line.long 0x04 "BWMON0,Bandwidth Monitor 0 Register"
|
|
group.long (0x48+0x18)++0x03
|
|
line.long 0x00 "CFG,ADC Configuration Register"
|
|
bitfld.long 0x00 22. " REFSEL ,Reference selection" "Internal,External"
|
|
rbitfld.long 0x00 0. " PND ,Pending configuration status" "Not pending,Pending"
|
|
group.long 0x64++0xB
|
|
line.long 0x00 "BPTR1,Base Pointer 1 Register"
|
|
line.long 0x04 "FRINC1,Frame Increment 1 Register"
|
|
line.long 0x08 "CBSIZ1,Circular Buffer Size 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Circular buffer size 1 value"
|
|
if (((per.l(ad:0x4000E000))&0x20)==0x20)
|
|
group.long (0x64+0x0C)++0x03
|
|
line.long 0x00 "TCA1,Timing Control A (ADC1) Register"
|
|
bitfld.long 0x00 16.--19. " NCK ,Number of clocks" ",1,2,3,4,5,6,7,8,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor buffer size 0 value"
|
|
else
|
|
group.long (0x64+0x0C)++0x03
|
|
line.long 0x00 "TCA1,Timing Control A (ADC1) Register"
|
|
bitfld.long 0x00 16.--19. " NCK ,Number of clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor buffer size 0 value"
|
|
endif
|
|
group.long (0x64+0x10)++0x07
|
|
line.long 0x00 "TCB1,Timing Control B (ADC1) Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCSCS ,Timing CS to CS delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TCKCS ,Time CK to CS hold"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCSCK ,Time CS to CK setup"
|
|
line.long 0x04 "BWMON1,Bandwidth Monitor 1 Register"
|
|
group.long 0x7C++0x07
|
|
line.long 0x00 "EVT0,Event 0 Time Register"
|
|
line.long 0x04 "EVCTL0,Event 0 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x84++0x07
|
|
line.long 0x00 "EVT1,Event 1 Time Register"
|
|
line.long 0x04 "EVCTL1,Event 1 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x8C++0x07
|
|
line.long 0x00 "EVT2,Event 2 Time Register"
|
|
line.long 0x04 "EVCTL2,Event 2 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "EVT3,Event 3 Time Register"
|
|
line.long 0x04 "EVCTL3,Event 3 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "EVT4,Event 4 Time Register"
|
|
line.long 0x04 "EVCTL4,Event 4 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "EVT5,Event 5 Time Register"
|
|
line.long 0x04 "EVCTL5,Event 5 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xAC++0x07
|
|
line.long 0x00 "EVT6,Event 6 Time Register"
|
|
line.long 0x04 "EVCTL6,Event 6 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "EVT7,Event 7 Time Register"
|
|
line.long 0x04 "EVCTL7,Event 7 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xBC++0x07
|
|
line.long 0x00 "EVT8,Event 8 Time Register"
|
|
line.long 0x04 "EVCTL8,Event 8 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xC4++0x07
|
|
line.long 0x00 "EVT9,Event 9 Time Register"
|
|
line.long 0x04 "EVCTL9,Event 9 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xCC++0x07
|
|
line.long 0x00 "EVT10,Event 10 Time Register"
|
|
line.long 0x04 "EVCTL10,Event 10 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "EVT11,Event 11 Time Register"
|
|
line.long 0x04 "EVCTL11,Event 11 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xDC++0x07
|
|
line.long 0x00 "EVT12,Event 12 Time Register"
|
|
line.long 0x04 "EVCTL12,Event 12 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xE4++0x07
|
|
line.long 0x00 "EVT13,Event 13 Time Register"
|
|
line.long 0x04 "EVCTL13,Event 13 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "EVT14,Event 14 Time Register"
|
|
line.long 0x04 "EVCTL14,Event 14 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xF4++0x07
|
|
line.long 0x00 "EVT15,Event 15 Time Register"
|
|
line.long 0x04 "EVCTL15,Event 15 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0xFC++0x07
|
|
line.long 0x00 "EVT16,Event 16 Time Register"
|
|
line.long 0x04 "EVCTL16,Event 16 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "EVT17,Event 17 Time Register"
|
|
line.long 0x04 "EVCTL17,Event 17 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "EVT18,Event 18 Time Register"
|
|
line.long 0x04 "EVCTL18,Event 18 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x114++0x07
|
|
line.long 0x00 "EVT19,Event 19 Time Register"
|
|
line.long 0x04 "EVCTL19,Event 19 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x11C++0x07
|
|
line.long 0x00 "EVT20,Event 20 Time Register"
|
|
line.long 0x04 "EVCTL20,Event 20 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "EVT21,Event 21 Time Register"
|
|
line.long 0x04 "EVCTL21,Event 21 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x12C++0x07
|
|
line.long 0x00 "EVT22,Event 22 Time Register"
|
|
line.long 0x04 "EVCTL22,Event 22 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "EVT23,Event 23 Time Register"
|
|
line.long 0x04 "EVCTL23,Event 23 Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EVTOFS ,Event offset"
|
|
bitfld.long 0x04 20. " TMRSEL ,Timer select" "Timer 0,Timer 1"
|
|
bitfld.long 0x04 17. " SIMSAMP ,Simultaneous sampling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADCSEL ,ADC select" "ADC0,ADC1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CTLWD ,Control word for ADC"
|
|
rgroup.long 0x200++0x13
|
|
line.long 0x00 "EPND,Pending Events Status Register"
|
|
bitfld.long 0x00 23. " EVT[23] ,Event 23 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Event 22 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Event 21 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " [20] ,Event 20 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Event 19 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Event 18 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Event 17 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Event 16 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Event 15 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [14] ,Event 14 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Event 13 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Event 12 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Event 11 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Event 10 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Event 9 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,Event 8 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Event 7 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Event 6 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Event 5 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Event 4 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Event 3 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Event 2 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Event 1 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Event 0 pending status" "Not pending,Pending"
|
|
line.long 0x04 "T0STAT,Timer 0 Status Register"
|
|
bitfld.long 0x04 16. " DPND ,DMA pending status" "Not pending,Pending"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURFR ,Current frame count"
|
|
line.long 0x08 "TMR0,Timer 0 Current Count Register"
|
|
line.long 0x0C "T1STAT,Timer 1 Status Register"
|
|
bitfld.long 0x0C 16. " DPND ,DMA pending status" "Not pending,Pending"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CURFR ,Current frame count"
|
|
line.long 0x10 "TMR1,Timer 1 Current Count Register"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "EVDAT0,Event 0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "EVDAT1,Event 1 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "EVDAT2,Event 2 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "EVDAT3,Event 3 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x224++0x03
|
|
line.long 0x00 "EVDAT4,Event 4 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "EVDAT5,Event 5 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x22C++0x03
|
|
line.long 0x00 "EVDAT6,Event 6 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "EVDAT7,Event 7 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "EVDAT8,Event 8 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "EVDAT9,Event 9 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "EVDAT10,Event 10 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "EVDAT11,Event 11 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "EVDAT12,Event 12 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "EVDAT13,Event 13 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "EVDAT14,Event 14 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "EVDAT15,Event 15 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "EVDAT16,Event 16 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "EVDAT17,Event 17 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "EVDAT18,Event 18 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "EVDAT19,Event 19 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "EVDAT20,Event 20 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "EVDAT21,Event 21 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "EVDAT22,Event 22 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "EVDAT23,Event 23 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Event data sampled from ADC"
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "EVSTAT0,Event 0 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "EVSTAT1,Event 1 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "EVSTAT2,Event 2 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "EVSTAT3,Event 3 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "EVSTAT4,Event 4 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "EVSTAT5,Event 5 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "EVSTAT6,Event 6 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "EVSTAT7,Event 7 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "EVSTAT8,Event 8 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "EVSTAT9,Event 9 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "EVSTAT10,Event 10 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "EVSTAT11,Event 11 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "EVSTAT12,Event 12 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "EVSTAT13,Event 13 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "EVSTAT14,Event 14 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "EVSTAT15,Event 15 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "EVSTAT16,Event 16 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "EVSTAT17,Event 17 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "EVSTAT18,Event 18 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "EVSTAT19,Event 19 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "EVSTAT20,Event 20 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "EVSTAT21,Event 21 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "EVSTAT22,Event 22 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "EVSTAT23,Event 23 Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DLYCNT ,Delay count"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("ADSPCM402F")||cpuis("ADSPCM403F")||cpuis("ADSPCM409F"))
|
|
tree "DACC (Digital-to-Analog Converter Controller)"
|
|
base ad:0x4000F000
|
|
width 22.
|
|
if (((per.l(ad:0x4000F000))&0x4)==0x4)&&(((per.l(ad:0x4000F000))&0x40)==0x40)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DACC0_CTL0,DACC0 Control 0 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CINTEN ,Circular buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x4000F000))&0x4)==0x4)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DACC0_CTL0,DACC0 Control 0 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DACC0_CTL0,DACC0 Control 0 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DACC0_ERRSTAT,DACC0 Error Status Register"
|
|
eventfld.long 0x00 5. " MER1 ,Memory error 1" "No error,Error"
|
|
eventfld.long 0x00 4. " MER0 ,Memory error 0" "No error,Error"
|
|
eventfld.long 0x00 3. " AER1 ,Address alignment error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " AER0 ,Address alignment error 0" "No error,Error"
|
|
eventfld.long 0x00 1. " DUVF1 ,DAC underflow 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DUVF0 ,DAC underflow 0" "Not occurred,Occurred"
|
|
if (((per.l(ad:0x4000F000+0x04))&0x4)==0x4)&&(((per.l(ad:0x4000F000+0x04))&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC0_CTL1,DACC0 Control 1 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CINTEN ,Circular buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x4000F000+0x04))&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC0_CTL1,DACC0 Control 1 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC0_CTL1,DACC0 Control 1 Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "DACC0_ERRMSK_SET/CLR,DACC0 Error Mask Register"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " MER1 ,Memory error 1 mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " MER0 ,Memory error 0 mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AER1 ,Address alignment error 1 mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AER0 ,Address alignment error 0 mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " DUVF1 ,DAC underflow 1 mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " DUVF0 ,DAC underflow 0 mask" "Disabled,Enabled"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "DACC0_ISTAT,DACC0 Interrupt Status Register"
|
|
rbitfld.long 0x00 3. " CINT1 ,Core complete (Non-DMA) interrupt 1 mask" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " CINT0 ,Core complete (Non-DMA) interrupt 0 mask" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " DINT1 ,DMA complete interrupt 1 mask" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " DINT0 ,DMA complete interrupt 0 mask" "No interrupt,Interrupt"
|
|
line.long 0x04 "DACC0_IMSK_SET/CLR,DACC0 Interrupt Mask Register"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " CINT1 ,Core complete (Non-DMA) interrupt 1 mask set/clr" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " CINT0 ,Core complete (Non-DMA) interrupt 0 mask set/clr" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " DINT1 ,DMA complete interrupt 1 mask clear." "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " DINT0 ,DMA complete interrupt 0 mask clear" "Disabled,Enabled"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "DACC0_TC0,DACC0 Timing Control 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSIDLE ,Frame sync idle"
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor"
|
|
line.long 0x04 "DACC0_BPTR0,DACC0 Base Pointer 0 Register"
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "DACC0_MOD0,DACC0 Modify 0 Register"
|
|
line.long 0x04 "DACC0_CNT0,DACC0 Count 0 Register"
|
|
line.long 0x08 "DACC0_DAT0,DACC0 Data FIFO 0 Register"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "DACC0_TC1,DACC0 Timing Control 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FSIDLE ,Frame sync idle"
|
|
hexmask.long.word 0x00 0.--15. 1. " CKDIV ,Clock divisor"
|
|
line.long 0x04 "DACC0_BPTR1,DACC0 Base Pointer 1 Register"
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "DACC0_MOD1,DACC0 Modify 1 Register"
|
|
line.long 0x04 "DACC0_CNT1,DACC0 Count 1 Register"
|
|
line.long 0x08 "DACC0_DAT1,DACC0 Data FIFO 1 Register"
|
|
if (((per.l(ad:0x4000F000+0x50))&0x4)==0x4)&&(((per.l(ad:0x4000F000+0x50))&0x40)==0x40)
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "DACC0_BCST_CTL,DACC0 Broadcast (Write) Control Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CINTEN ,Circular buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x4000F000+0x50))&0x4)==0x4)
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "DACC0_BCST_CTL,DACC0 Broadcast (Write) Control Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CBUFEN ,Circular buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "DACC0_BCST_CTL,DACC0 Broadcast (Write) Control Register"
|
|
bitfld.long 0x00 18. " CKPOL ,Clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 16. " SYNCPOL ,SYNC polarity" "Low,High"
|
|
bitfld.long 0x00 8.--11. " DLEN ,Data length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GCKEN ,Gated clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LSBF ,LSB-First mode" "MSB-First,LSB-First"
|
|
bitfld.long 0x00 3. " DMAW ,DMA data width" "16-Bit,32-Bit"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "DACC0_CNTCUR0,DACC0 Current Count 0 Register"
|
|
line.long 0x04 "DACC0_CNTCUR1,DACC0 Current Count 1 Register"
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "DACC0_STAT,DACC0 Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "HAE (Harmonic Analysis Engine)"
|
|
base ad:0x400180A0
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HAE_RUN,HAE Run Register"
|
|
bitfld.long 0x00 0. " RUN ,Run/Stop" "Stop,Run"
|
|
group.long 0xA60++0x0F
|
|
line.long 0x00 "HAE_CFG0,HAE Configuration 0 Register"
|
|
bitfld.long 0x00 7. " RXIRQEN ,Receive IRQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXIRQEN ,Transmit IRQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LFREQ ,Line frequency select" "50 Hz,60 Hz"
|
|
line.long 0x04 "HAE_CFG1,HAE Configuration 1 Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " STARTDIV ,Start (clock) divider"
|
|
line.long 0x08 "HAE_CFG2,HAE Configuration 2 Register"
|
|
bitfld.long 0x08 6. " EN ,Enable clock" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--5. " UPDATE ,Update rate select" "125 uSec,250 uSec,1 mSec,16 mSec,128 mSec,512 mSec,1024 mSec,Disabled"
|
|
bitfld.long 0x08 1.--2. " SETTLE ,Settle period select" "512 mSec,768 mSec,1024 mSec,1280 mSec"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MODE ,(Results) mode select" "Results after settle,Results first"
|
|
line.long 0x0C "HAE_CFG3,HAE Configuration 3 Register"
|
|
bitfld.long 0x0C 12. " CHANEN[12] ,Channel 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [11] ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [10] ,Channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " [9] ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [8] ,Channel 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [7] ,Channel 7 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " [6] ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [5] ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [4] ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [2] ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [1] ,Channel 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " [0] ,Channel 0 enable" "Disabled,Enabled"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "HAE_STAT,HAE Status Register"
|
|
bitfld.long 0x00 2. " RDY ,Ready status" "No status,Ready"
|
|
eventfld.long 0x00 1. " RXIRQ ,Receive IRQ status" "No status,Interrupt detected"
|
|
eventfld.long 0x00 0. " TXIRQ ,Transmit IRQ status" "No status,Interrupt detected"
|
|
group.long 0xAA0++0x07
|
|
line.long 0x00 "HAE_ISAMPLE,HAE I (Current) Sample Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current input sample"
|
|
line.long 0x04 "HAE_VSAMPLE,HAE V (Voltage) Sample Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " VALUE ,Voltage input sample"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "HAE_IWAVEFORM,HAE I (Current) Waveform Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current waveform"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "HAE_VWAVEFORM,HAE V (Voltage) Waveform Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Voltage waveform"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "HAE_RESULTS_RAM,HAE Results RAM Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ENTRY ,Results memory address"
|
|
group.long 0x1D60++0x0B
|
|
line.long 0x00 "HAE_CFG4,HAE Configuration 4 Register"
|
|
bitfld.long 0x00 1. " DIDTEN ,Di/dt (Sensor) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HPFEN ,High-pass filter enable" "Disabled,Enabled"
|
|
line.long 0x04 "HAE_DIDT_GAIN,HAE DIDT Gain Register"
|
|
hexmask.long 0x04 0.--27. 1. " VALUE ,Di/dt Sensor gain"
|
|
line.long 0x08 "HAE_DIDT_COEF,HAE DIDT Coefficient Register"
|
|
hexmask.long 0x08 0.--27. 1. " VALUE ,Di/dt coefficient"
|
|
group.long 0x1D70++0x03
|
|
line.long 0x00 "HAE_VLEVEL,HAE Voltage Level Register"
|
|
hexmask.long 0x00 0.--27. 1. " VALUE ,Voltage input level"
|
|
group.long 0x1D8C++0x3
|
|
line.long 0x00 "HAE_H0_INDX,HAE Harmonic 0 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 0 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D90++0x3
|
|
line.long 0x00 "HAE_H1_INDX,HAE Harmonic 1 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 1 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D94++0x3
|
|
line.long 0x00 "HAE_H2_INDX,HAE Harmonic 2 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 2 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D98++0x3
|
|
line.long 0x00 "HAE_H3_INDX,HAE Harmonic 3 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 3 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D9C++0x3
|
|
line.long 0x00 "HAE_H4_INDX,HAE Harmonic 4 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 4 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DA0++0x3
|
|
line.long 0x00 "HAE_H5_INDX,HAE Harmonic 5 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 5 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DA4++0x3
|
|
line.long 0x00 "HAE_H6_INDX,HAE Harmonic 6 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 6 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DA8++0x3
|
|
line.long 0x00 "HAE_H7_INDX,HAE Harmonic 7 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 7 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DAC++0x3
|
|
line.long 0x00 "HAE_H8_INDX,HAE Harmonic 8 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 8 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DB0++0x3
|
|
line.long 0x00 "HAE_H9_INDX,HAE Harmonic 9 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 9 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DB4++0x3
|
|
line.long 0x00 "HAE_H10_INDX,HAE Harmonic 10 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 10 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1DB8++0x3
|
|
line.long 0x00 "HAE_H11_INDX,HAE Harmonic 11 Index Register"
|
|
bitfld.long 0x00 0.--5. " VALUE ,Harmonic 11 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SINC (Sinus Cardinalis Filter)"
|
|
base ad:0x4000D000
|
|
width 19.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SINC_CTL,SINC Control Register"
|
|
bitfld.long 0x00 31. " ELIM1 ,Enable Limit for Group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ESAT1 ,Enable saturation for group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " EPCNT1 ,Enable primary count for group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EFOVF1 ,Enable FIFO overflow for group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ELIM0 ,Enable limit for group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ESAT0 ,Enable saturation for group 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EPCNT0 ,Enable primary count for group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EFOVF0 ,Enable FIFO overflow for group 0" "Disabled,Enabled"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EN3 ,Enable filter pair 3" "Disabled,,Enabled/Group0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EN2 ,Enable filter pair 2" "Disabled,,Enabled/Group0,?..."
|
|
bitfld.long 0x00 2.--3. " EN1 ,Enable filter pair 1" "Disabled,,Enabled/Group0,?..."
|
|
bitfld.long 0x00 0.--1. " EN0 ,Enable filter pair 0" "Disabled,,Enabled/Group0,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EN3 ,Enable filter pair 3" "Disabled,,Enabled/Group0,Enabled/Group1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EN2 ,Enable filter pair 2" "Disabled,,Enabled/Group0,Enabled/Group1"
|
|
bitfld.long 0x00 2.--3. " EN1 ,Enable filter pair 1" "Disabled,,Enabled/Group0,Enabled/Group1"
|
|
bitfld.long 0x00 0.--1. " EN0 ,Enable filter pair 0" "Disabled,,Enabled/Group0,Enabled/Group1"
|
|
endif
|
|
line.long 0x04 "SINC_STAT,SINC Status Register"
|
|
rbitfld.long 0x04 31. " GLIM1 ,Group 1 limit status" "Not exceeded,Exceeded"
|
|
rbitfld.long 0x04 30. " GSAT1 ,Group 1 saturation status" "Not set,Set"
|
|
eventfld.long 0x04 29. " PCNT1 ,Primary (filter) count for group 1 status" "Not Reached,Reached"
|
|
textline " "
|
|
eventfld.long 0x04 28. " FOVF1 ,FIFO overflow for group 1 status" "No overflow,Overflow"
|
|
eventfld.long 0x04 27. " PFAB1 ,Primary (filter) fabric error for group 1 status" "Disabled,Enabled"
|
|
eventfld.long 0x04 23. " PSAT3 ,Primary (filter) 3 saturation status" "Not saturated,Saturated"
|
|
textline " "
|
|
eventfld.long 0x04 22. " PSAT2 ,Primary (filter) 2 saturation status" "Not saturated,Saturated"
|
|
eventfld.long 0x04 21. " PSAT1 ,Primary (filter) 1 saturation status" "Not saturated,Saturated"
|
|
eventfld.long 0x04 20. " PSAT0 ,Primary (filter) 0 saturation status" "Not saturated,Saturated"
|
|
textline " "
|
|
eventfld.long 0x04 19. " MAX3 ,Maximum for secondary filter 3 status" "Not exceeded,Exceeded"
|
|
eventfld.long 0x04 18. " MAX2 ,Maximum for secondary filter 2 status" "Not exceeded,Exceeded"
|
|
eventfld.long 0x04 17. " MAX1 ,Maximum for secondary filter 1 status" "Not exceeded,Exceeded"
|
|
textline " "
|
|
eventfld.long 0x04 16. " MAX0 ,Maximum for secondary filter 0 status" "Not exceeded,Exceeded"
|
|
rbitfld.long 0x04 15. " GLIM0 ,Group 0 limit status" "Not exceeded,Exceeded"
|
|
rbitfld.long 0x04 14. " GSAT0 ,Group 0 saturation status" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x04 13. " PCNT0 ,Primary (filter) count for group 0 status" "Not reached,Reached"
|
|
eventfld.long 0x04 12. " FOVF0 ,FIFO overflow for group 0 status" "No overflow,Overflow"
|
|
eventfld.long 0x04 11. " PFAB0 ,Primary (filter) fabric error for group 0 status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 3. " MIN3 ,Minimum for secondary filter 3 status" "Not exceeded,Exceeded"
|
|
eventfld.long 0x04 2. " MIN2 ,Minimum for secondary filter 2 status" "Not exceeded,Exceeded"
|
|
eventfld.long 0x04 1. " MIN1 ,Minimum for secondary filter 1 status" "Not exceeded,Exceeded"
|
|
textline " "
|
|
eventfld.long 0x04 0. " MIN0 ,Minimum for secondary filter 0 status" "Not exceeded,Exceeded"
|
|
line.long 0x08 "SINC_CLK,SINC Clock Control Register"
|
|
bitfld.long 0x08 26.--31. " MDIV1 ,Modulator (clock) divider for group 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 24. " MREQ1 ,Modulator (clock) request for group 1 status" "Inactive,Active"
|
|
bitfld.long 0x08 18.--23. " MADJ1 ,Modulator (clock) adjustment for group 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " MCEN1 ,Modulator (clock) enable for group 1" "Disable,,Enable and commence,Enable and commence on next rising edge"
|
|
bitfld.long 0x08 10.--15. " MDIV0 ,Modulator (clock) divider for group 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 8. " MREQ0 ,Modulator (clock) request for group 0 status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 2.--7. " MADJ0 ,Modulator (clock) adjustment for group 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--1. " MCEN0 ,Modulator (clock) enable for group 0" "Disable,,Enabled and commence,Enabled and commence on next rising edge"
|
|
if (((per.l(ad:0x4000D000+0x18))&0x4000)==0x4000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SINC_RATE0,SINC Rate Control for Group 0 Register"
|
|
bitfld.long 0x00 25.--30. " SADJ ,Secondary (filter) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--24. 1. " PADJ ,Primary (filter) adjustment"
|
|
bitfld.long 0x00 9.--14. " SDEC ,Secondary (filter) decimation rate" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " PDEC ,Primary (filter) decimation Rate"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SINC_RATE0,SINC Rate Control for Group 0 Register"
|
|
bitfld.long 0x00 25.--30. " SADJ ,Secondary (filter) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--24. 1. " PADJ ,Primary (filter) adjustment"
|
|
bitfld.long 0x00 9.--14. " SDEC ,Secondary (filter) decimation rate" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " PDEC ,Primary (filter) decimation rate"
|
|
endif
|
|
if (((per.l(ad:0x4000D000+0x1C))&0x4000)==0x4000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SINC_RATE1,SINC Rate Control for Group 1 Register"
|
|
bitfld.long 0x00 25.--30. " SADJ ,Secondary (filter) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--24. 1. " PADJ ,Primary (filter) adjustment"
|
|
bitfld.long 0x00 9.--14. " SDEC ,Secondary (filter) decimation rate" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " PDEC ,Primary (filter) decimation rate"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SINC_RATE1,SINC Rate Control for Group 1 Register"
|
|
bitfld.long 0x00 25.--30. " SADJ ,Secondary (filter) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--24. 1. " PADJ ,Primary (filter) adjustment"
|
|
bitfld.long 0x00 9.--14. " SDEC ,Secondary (filter) decimation rate" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " PDEC ,Primary (filter) decimation rate"
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SINC_LEVEL0,SINC Level Control for Group 0 Register"
|
|
bitfld.long 0x00 30. " PORD ,Primary (filter) order" "Third,Fourth"
|
|
bitfld.long 0x00 24.--29. " PSCALE ,Primary (filter) scaling" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " PCNT ,Primary (filter) count"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SORD ,Secondary (filter) order select" "Third,Fourth"
|
|
bitfld.long 0x00 11.--13. " LCNT ,(Excursion) limit count" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 8.--10. " LWIN ,(Excursion) limit window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SINC_LEVEL1,SINC Level Control for Group 1 Register"
|
|
bitfld.long 0x04 30. " PORD ,Primary (filter) order" "Third,Fourth"
|
|
bitfld.long 0x04 24.--29. " PSCALE ,Primary (filter) scaling" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
hexmask.long.byte 0x04 16.--23. 1. " PCNT ,Primary (filter) Count"
|
|
textline " "
|
|
bitfld.long 0x04 14. " SORD ,Secondary (filter) order" "Third,Fourth"
|
|
bitfld.long 0x04 11.--13. " LCNT ,(Excursion) limit count" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x04 8.--10. " LWIN ,(Excursion) limit window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "SINC_LIMIT0,SINC (Amplitude) Limits for Secondary Filter 0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " LMAX ,Limit maximum for secondary filter 0"
|
|
hexmask.long.word 0x08 0.--15. 1. " LMIN ,Limit minimum for secondary filter 0"
|
|
line.long 0x0C "SINC_LIMIT1,SINC (Amplitude) Limits for Secondary Filter 1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " LMAX ,Limit maximum for secondary filter 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LMIN ,Limit minimum for secondary filter 1"
|
|
line.long 0x10 "SINC_LIMIT2,SINC (Amplitude) Limits for Secondary Filter 2 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " LMAX ,Limit maximum for Secondary Filter 2"
|
|
hexmask.long.word 0x10 0.--15. 1. " LMIN ,Limit minimum for secondary filter 2"
|
|
line.long 0x14 "SINC_LIMIT3,SINC (Amplitude) Limits for Secondary Filter 3 Register"
|
|
hexmask.long.word 0x13 16.--31. 1. " LMAX ,Limit maximum for secondary filter 3"
|
|
hexmask.long.word 0x13 0.--15. 1. " LMIN ,Limit minimum for secondary filter 3"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SINC_BIAS0,SINC Bias for Group 0 Register"
|
|
line.long 0x04 "SINC_BIAS1,SINC Bias for Group 1 Register"
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "SINC_PPTR0,SINC Primary (Filters) Pointer for Group 0 Register"
|
|
line.long 0x04 "SINC_PPTR1,SINC Primary (Filters) Pointer for Group 1 Register"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "SINC_PHEAD0,SINC Primary (Filters) Head for Group 0 Register"
|
|
line.long 0x04 "SINC_PHEAD1,SINC Primary (Filters) Head for Group 1 Register"
|
|
line.long 0x08 "SINC_PTAIL0,SINC Primary (Filters) Tail for Group 0 Register"
|
|
line.long 0x0C "SINC_PTAIL1,SINC Primary (Filters) Tail for Group 1 Register"
|
|
sif (cpuis("ADSPCM40*"))
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "SINC_HIS_STAT,SINC History Status Register"
|
|
bitfld.long 0x00 12.--14. " P3HISPTR ,Pair 3 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
bitfld.long 0x00 8.--10. " P2HISPTR ,Pair 2 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
bitfld.long 0x00 4.--6. " P1HISPTR ,Pair 1 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P0HISPTR ,Pair 0 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SINC_HIS_STAT,SINC History Status Register"
|
|
bitfld.long 0x00 12.--14. " P3HISPTR ,Pair 3 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
bitfld.long 0x00 8.--10. " P2HISPTR ,Pair 2 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
bitfld.long 0x00 4.--6. " P1HISPTR ,Pair 1 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P0HISPTR ,Pair 0 history pointer" "3/MS,0/LS,0/MS,1/LS,1/MS,2/LS,2/MS,3/LS"
|
|
endif
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "SINC_P0SEC_HIST0,SINC Pair 0 Secondary (Filter) History 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x00 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x04 "SINC_P0SEC_HIST1,SINC Pair 0 Secondary (Filter) History 0 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x08 "SINC_P0SEC_HIST2,SINC Pair 0 Secondary (Filter) History 0 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x08 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x0C "SINC_P0SEC_HIST3,SINC Pair 0 Secondary (Filter) History 0 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LO ,Low data word"
|
|
rgroup.long 0x90++0x0F
|
|
line.long 0x00 "SINC_P1SEC_HIST0,SINC Pair 1 Secondary (Filter) History 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x00 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x04 "SINC_P1SEC_HIST1,SINC Pair 1 Secondary (Filter) History 1 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x08 "SINC_P1SEC_HIST2,SINC Pair 1 Secondary (Filter) History 1 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x08 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x0C "SINC_P1SEC_HIST3,SINC Pair 1 Secondary (Filter) History 1 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LO ,Low data word"
|
|
rgroup.long 0xA0++0x0F
|
|
line.long 0x00 "SINC_P2SEC_HIST0,SINC Pair 2 Secondary (Filter) History 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x00 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x04 "SINC_P2SEC_HIST1,SINC Pair 2 Secondary (Filter) History 2 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x08 "SINC_P2SEC_HIST2,SINC Pair 2 Secondary (Filter) History 2 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x08 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x0C "SINC_P2SEC_HIST3,SINC Pair 2 Secondary (Filter) History 2 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LO ,Low data word"
|
|
rgroup.long 0xB0++0x0F
|
|
line.long 0x00 "SINC_P3SEC_HIST0,SINC Pair 3 Secondary (Filter) History 3 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x00 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x04 "SINC_P3SEC_HIST1,SINC Pair 3 Secondary (Filter) History 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x04 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x08 "SINC_P3SEC_HIST2,SINC Pair 3 Secondary (Filter) History 3 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x08 0.--15. 1. " LO ,Low data word"
|
|
line.long 0x0C "SINC_P3SEC_HIST3,SINC Pair 3 Secondary (Filter) History 3 Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " HI ,High data word"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LO ,Low data word"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RCU (Reset Control Unit)"
|
|
base ad:0x40014000
|
|
width 17.
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 10. " CRSTMSKSEL ,Core reset system reset mask select" "No reset,Reset"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert RSTOUT"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Assert RSTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 10. " CRSTMSKSEL ,Core reset system reset mask select" "No reset,Reset"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert RSTOUT"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Assert RSTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,RCU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Deassert"
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCU_CTL,RCU Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 9. " CRSTREQEN ,Core reset request enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SRSTREQEN ,System reset request enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTOUTDSRT ,Reset out deassert" "No action,Deassert"
|
|
bitfld.long 0x00 1. " RSTOUTASRT ,Reset out assert" "No action,Deassert"
|
|
bitfld.long 0x00 0. " SYSRST ,System reset" "No action,Reset"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCU_STAT,RCU Status Register"
|
|
eventfld.long 0x00 18. " RSTOUTERR ,Reset out error" "No error,Error"
|
|
eventfld.long 0x00 17. " LWERR ,Lock write error" "No error,Error"
|
|
eventfld.long 0x00 16. " ADDRERR ,Address error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " BMODE ,Boot mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 5. " RSTOUT ,Reset out status" "No reset,Reset"
|
|
eventfld.long 0x00 3. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " SSRST ,System source reset" "No reset,Reset"
|
|
eventfld.long 0x00 0. " HWRST ,Hardware reset" "No reset,Reset"
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
bitfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR[0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
bitfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR[0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x08))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Low,High"
|
|
bitfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
bitfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RCU_CRCTL,RCU Core Reset Outputs Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Low,High"
|
|
bitfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
bitfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset Outputs Status Register"
|
|
eventfld.long 0x00 3. " CR[3] ,Core reset outputs 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,Core reset outputs 2" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " [1] ,Core reset outputs 1" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Core reset outputs 0" "Deasserted,Asserted"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset Outputs Status Register"
|
|
eventfld.long 0x00 0. " CR[0] , Core reset outputs 0" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RCU_CRSTAT,RCU Core Reset outputs Status Register"
|
|
eventfld.long 0x00 2. " CR2 ,Core reset outputs" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " CR1 ,Core reset outputs" "Deasserted,Asserted"
|
|
eventfld.long 0x00 0. " CR0 ,Core reset outputs" "Deasserted,Asserted"
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")||!cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40014000+0x10))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RCU_SIDIS,RCU System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable request" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System interface disable request" "Not asserted,Asserted"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RCU_SIDIS,RCU System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable request" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System Interface disable request" "Not asserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RCU_SISTAT,RCU System Interface Status Register"
|
|
bitfld.long 0x00 1. " SI1 ,System interface disable acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " SI0 ,System interface disable acknowledge" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCU_SRRQSTAT,System Reset Request Status"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
eventfld.long 0x00 7. " SRRQ[7] ,System reset triggered by system reset request 7" "Deasserted,Asserted"
|
|
eventfld.long 0x00 6. " [6] ,System reset triggered by system reset request 6" "Deasserted,Asserted"
|
|
eventfld.long 0x00 5. " [5] ,System reset triggered by system reset request 5" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 4. " [4] ,System reset triggered by system reset request 4" "Deasserted,Asserted"
|
|
eventfld.long 0x00 3. " [3] ,System reset triggered by system reset request 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,System reset triggered by system reset request 2" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,System reset triggered by system reset request 1" "Deasserted,Asserted"
|
|
eventfld.long 0x00 0. " [0] ,System reset triggered by system reset request 0" "Deasserted,Asserted"
|
|
else
|
|
eventfld.long 0x00 3. " SRRQ[3] ,System reset triggered by system reset request 3" "Deasserted,Asserted"
|
|
eventfld.long 0x00 2. " [2] ,System reset triggered by system reset request 2" "Deasserted,Asserted"
|
|
eventfld.long 0x00 1. " [1] ,System reset triggered by system reset request 1" "Deasserted,Asserted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,System reset triggered by system reset request 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x18))&0x80000000)==0x80000000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,RCU SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 2. " SVECT2 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SVECT1 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT0 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,RCU SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 2. " SVECT2 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
bitfld.long 0x00 1. " SVECT1 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT0 ,If the global lock bit is set (GLCK bit =1) and the SVECT[n] bit is set, the RCU_SVECTn register is read only (locked)." "Unlock,Lock"
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RCU_SIDIS,System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable request 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable request 0" "Deasserted,Asserted"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCU_SIDIS,System Interface Disable Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable request 1" "Deasserted,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable request 0" "Deasserted,Asserted"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x1C))&0x80000000)==0x80000000)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RCU_BCODE,RCU Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Do not enter,Enter"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Do not configure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "Hook,No hook"
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Preboot,No preboot"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Fault initialization,No fault initialization"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Enable and initialize,Do not initialize or enable"
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Memory initialization,No memory initialization"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Do not execute,Execute"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "Vector,Do not Vector"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "Execute,Do not execute"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCU_BCODE,RCU Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Do not enter,Enter"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Do not configure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "Hook,No hook"
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Preboot,No preboot"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Fault initialization,No fault initialization"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Enable and initialize,Do not initialize or enable"
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Memory initialization,No memory initialization"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Do not execute,Execute"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "Vector,Do not Vector"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "Execute,Do not execute"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
sif (cpuis("ADSP-SC57*"))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RCU_SISTAT,System Interface Status Register"
|
|
bitfld.long 0x00 1. " SI[1] ,System interface disable acknowledge 1" "No Acknowledge,Asserted"
|
|
bitfld.long 0x00 0. " SI[0] ,System interface disable acknowledge 0" "No Acknowledge,Asserted"
|
|
else
|
|
if (((per.l(ad:0x40014000+0x18))&0x01)==0x01)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RCU_SVECT0,RCU Software Vector Register 0"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCU_SVECT0,RCU Software Vector Register 0"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x24))&0x80000000)==0x80000000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " SVECT[2] ,Lock SVECT2 registers" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SVECT[1] ,Lock SVECT1 registers" "Unlocked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT[0] ,Lock SVECT0 registers" "Unlocked,Locked"
|
|
textline " "
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT_LCK,SVECT Lock Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 2. " SVECT[2] ,Lock SVECT2 registers" "Unlocked,Locked"
|
|
bitfld.long 0x00 1. " SVECT[1] ,Lock SVECT1 registers" "Unlocked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " SVECT[0] ,Lock SVECT0 registers" "Unlocked,Locked"
|
|
textline " "
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x18))&0x02)==0x02)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT1,RCU Software Vector Register 1"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RCU_SVECT1,RCU Software Vector Register 1"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x28))&0x80000000)==0x80000000)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RCU_BCODE,Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOCORE3 ,No core 3 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Not idle,Idle"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 configuration" "Configure,Not configure"
|
|
bitfld.long 0x00 10. " NOHOOK ,No hook" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Perform,Not perform"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No faults" "Perform,Not perform"
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Initialize,Not initialize"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Perform,Not perform"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute Wakeup" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Not execute,Execute"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "No,Yes"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "No,Yes"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCU_BCODE,Boot Code Register"
|
|
bitfld.long 0x00 31. " LOCK ,Lock" "Unlocked,Locked"
|
|
sif (cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOCORE3 ,No core 3 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " NOCORE2 ,No core 2 present" "Not exist,Exists"
|
|
bitfld.long 0x00 17. " NOCORE1 ,No core 1 present" "Not exist,Exists"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " NOCORE0 ,No core 0 present" "Not exist,Exists"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " IDLEONENTRY ,Idle on entry" "Not idle,Idle"
|
|
bitfld.long 0x00 12. " NOL2CONFIG ,No L2 Configuration" "Configure,Not configure"
|
|
bitfld.long 0x00 10. " NOHOOK ,No Hook" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NOPREBOOT ,No pre boot" "Perform,Not perform"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Perform,Not perform"
|
|
bitfld.long 0x00 5. " NOCACHE ,No cache" "Initialize,Not initialize"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No memory initialization" "Perform,Not perform"
|
|
bitfld.long 0x00 3. " HBTOVW ,Execute wakeup" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Not execute,Execute"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No vector initialize" "No,Yes"
|
|
bitfld.long 0x00 0. " NOKERNEL ,No boot kernel" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x18))&0x04)==0x04)&&(((per.l(ad:0x3108C000))&0x01)==0x01)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RCU_SVECT2,RCU Software Vector Register 2"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCU_SVECT2,RCU Software Vector Register 2"
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*")||cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x24))&0x01)==0x01)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RCU_SVECT0,Software Vector Register 0"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCU_SVECT0,Software Vector Register 0"
|
|
endif
|
|
sif (!cpuis("ADSPCM40*"))
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x24))&0x02)==0x02)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RCU_SVECT1,Software Vector Register 1"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCU_SVECT1,Software Vector Register 1"
|
|
endif
|
|
if (((per.l(ad:0x40027000))&0xFF)!=0xAD)&&(((per.l(ad:0x40014000+0x24))&0x04)==0x04)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "RCU_SVECT2,Software Vector Register 2"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RCU_SVECT2,Software Vector Register 2"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("ADSP-SC57*"))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RCU_MSG_SET/CLR,RCU Message Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CALLERR ,Call Error Flag" "Not set,Set"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " HALTONERR ,Halt on Error Call" "Not generate,Generate"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HALTONCALL ,Halt on callback call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " HALTONINIT ,Halt on initcode call" "Not generate,Generate"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " HALTONAPP ,Halt on application call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " L2INIT ,L2 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SECINIT ,SEC initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " C2ACTIVATE ,Core 2 activated" "Not activated,Activated"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " C1ACTIVATE ,Core 1 activated" "Not activated,Activated"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " C2L1INIT ,Core 2 L1 initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " C1L1INIT ,Core 1 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " C2IDLE ,Core 2 idle" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " C1IDLE ,Core 1 idle" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " C0IDLE ,Core 0 idle" "No,Yes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERRCODE ,ROM Error Code"
|
|
elif (cpuis("ADSPCM40*"))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RCU_MSG_SET/CLR,RCU Message Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CALLERR ,Call Error Flag" "Not set,Set"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " HALTONERR ,Halt on Error Call" "Not generate,Generate"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " HALTONCALL ,Halt on callback call" "Not generate,Generate"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " HALTONINIT ,Halt on initcode call" "Not generate,Generate"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " HALTONAPP ,Halt on application call" "Not generate,Generate"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " L3INIT ,L3 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " L2INIT ,L2 initialized" "Not initialized,Initialized"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RCU_MSG,RCU Message Register"
|
|
bitfld.long 0x00 31. " CALLERR ,Call error flag" "Not set,Set"
|
|
bitfld.long 0x00 30. " CALLBACK ,Callback call flag" "Not set,Set"
|
|
bitfld.long 0x00 29. " CALLINIT ,Call initcode flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CALLAPP ,Call application flag" "Not set,Set"
|
|
bitfld.long 0x00 27. " HALTONERR ,Halt on error call" "Do not generate,Generate"
|
|
bitfld.long 0x00 26. " HALTONCALL ,Halt on callback call" "Do not generate,Generate"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HALTONINIT ,Halt on initcode call" "Do not generate,Generate"
|
|
bitfld.long 0x00 24. " HALTONAPP ,Halt on application call" "Do not generate,Generate"
|
|
bitfld.long 0x00 23. " L3INIT ,L3 Initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 22. " L2INIT ,L2 Initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 20. " C2ACTIVATE ,Core 2 activated" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " C1ACTIVATE ,Core 1 activated" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " C2L1INIT ,Core 2 L1 initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 17. " C1L1INIT ,Core 1 L1 initialized" "Not initialized,Initialized"
|
|
bitfld.long 0x00 16. " C0L1INIT ,Core 0 L1 initialized" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C2IDLE ,Indicates that core 2 is in a safe idle state in ROM" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " C1IDLE ,Indicates that core 1 is in a safe idle state in ROM" "Not idle,Idle"
|
|
bitfld.long 0x00 8. " C0IDLE ,Indicates that core 0 is in a safe idle state in ROM" "Not idle,Idle"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERRCODE ,ERRCODE"
|
|
endif
|
|
sif (!cpuis("ADSP-SC57*")&&!cpuis("ADSPCM40*"))
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "RCU_MSG_SET,RCU Message Set Bits Register"
|
|
bitfld.long 0x00 31. " SET[31] , Set message bit 31" "No effect,Set"
|
|
bitfld.long 0x00 30. " [30] , Set message bit 30" "No effect,Set"
|
|
bitfld.long 0x00 29. " [29] , Set message bit 29" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " [28] , Set message bit 28" "No effect,Set"
|
|
bitfld.long 0x00 27. " [27] , Set message bit 27" "No effect,Set"
|
|
bitfld.long 0x00 26. " [26] , Set Message Bit 26" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] , Set message bit 25" "No effect,Set"
|
|
bitfld.long 0x00 24. " [24] , Set Message Bit 24" "No effect,Set"
|
|
bitfld.long 0x00 23. " [23] , Set Message Bit 23" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [22] , Set message bit 22" "No effect,Set"
|
|
bitfld.long 0x00 21. " [21] , Set message bit 21" "No effect,Set"
|
|
bitfld.long 0x00 20. " [20] , Set message bit 20" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] , Set message bit 19" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] , Set message bit 18" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] , Set message bit 17" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] , Set message bit 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " [15] , Set message bit 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] , Set message bit 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] , Set message bit 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] , Set message bit 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " [11] , Set message bit 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] , Set message bit 10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] , Set message bit 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] , Set message bit 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] , Set message bit 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] , Set message bit 6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] , Set message bit 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] , Set Message Bit 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " [3] , Set message bit 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] , Set message bit 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] , Set message bit 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] , Set message bit 0" "No effect,Set"
|
|
line.long 0x04 "RCU_MSG_CLR,RCU Message Clear Bits Register"
|
|
bitfld.long 0x04 31. " CLR[31] ,Clear MSG register bit 31" "No effect,Clear"
|
|
bitfld.long 0x04 30. " [30] ,Clear MSG register bit 30 " "No effect,Clear"
|
|
bitfld.long 0x04 29. " [29] ,Clear MSG register bit 29" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " [28] ,Clear MSG register bit 28" "No effect,Clear"
|
|
bitfld.long 0x04 27. " [27] ,Clear MSG register bit 27" "No effect,Clear"
|
|
bitfld.long 0x04 26. " [26] ,Clear MSG register bit 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " [25] ,Clear MSG register bit 25" "No effect,Clear"
|
|
bitfld.long 0x04 24. " [24] ,Clear MSG register bit 24" "No effect,Clear"
|
|
bitfld.long 0x04 23. " [23] ,Clear MSG register bit 23" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " [22] ,Clear MSG register bit 22" "No effect,Clear"
|
|
bitfld.long 0x04 21. " [21] ,Clear MSG register bit 21" "No effect,Clear"
|
|
bitfld.long 0x04 20. " [20] ,Clear MSG register bit 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [19] ,Clear MSG register bit 19" "No effect,Clear"
|
|
bitfld.long 0x04 18. " [18] ,Clear MSG register bit 18" "No effect,Clear"
|
|
bitfld.long 0x04 17. " [17] ,Clear MSG register bit 17" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " [16] ,Clear MSG register bit 16" "No effect,Clear"
|
|
bitfld.long 0x04 15. " [15] ,Clear MSG register bit 15" "No effect,Clear"
|
|
bitfld.long 0x04 14. " [14] ,Clear MSG register bit 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [13] ,Clear MSG register bit 13" "No effect,Clear"
|
|
bitfld.long 0x04 12. " [12] ,Clear MSG register bit 12" "No effect,Clear"
|
|
bitfld.long 0x04 11. " [11] ,Clear MSG register bit 11" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " [10] ,Clear MSG register bit 10" "No effect,Clear"
|
|
bitfld.long 0x04 9. " [9] ,Clear MSG register bit 9" "No effect,Clear"
|
|
bitfld.long 0x04 8. " [8] ,Clear MSG register bit 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Clear MSG register bit 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " [6] ,Clear MSG register bit 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " [5] ,Clear MSG register bit 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " [4] ,Clear MSG register bit 4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " [3] ,Clear MSG register bit 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " [2] ,Clear MSG register bit 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,Clear MSG register bit 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " [0] ,Clear MSG register bit 0" "No effect,Clear"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RCU_REVID,RCU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental version ID"
|
|
endif
|
|
sif (cpuis("ADSPCM40*"))
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "RCU_REVID,RCU Revision ID Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major Version ID"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REV ,Incremental version ID"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SWU (System Watchpoint Unit)"
|
|
tree "SWU0"
|
|
base ad:0x40022000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU0_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU0_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x40022000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU0_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU0_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU0_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU0_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU0_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU0_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40022000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU0_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU0_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU0_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU0_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU0_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU0_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40022000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU0_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU0_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU0_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU0_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU0_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU0_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40022000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU0_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU0_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU0_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU0_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU0_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU0_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU0_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU0_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU0_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU1"
|
|
base ad:0x40023000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU1_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU1_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x40023000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU1_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU1_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU1_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU1_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU1_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU1_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40023000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU1_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU1_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU1_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU1_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU1_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU1_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40023000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU1_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU1_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU1_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU1_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU1_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU1_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40023000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU1_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU1_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU1_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU1_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU1_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU1_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU1_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU1_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU1_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU2"
|
|
base ad:0x40024000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU2_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU2_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x40024000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU2_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU2_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU2_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU2_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU2_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU2_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40024000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU2_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU2_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU2_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU2_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU2_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU2_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40024000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU2_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU2_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU2_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU2_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU2_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU2_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40024000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU2_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU2_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU2_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU2_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU2_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU2_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU2_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU2_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU2_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU3"
|
|
base ad:0x40025000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU3_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU3_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x40025000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU3_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU3_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU3_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU3_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU3_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU3_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU3_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU3_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU3_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40025000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU3_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU3_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU3_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU3_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU3_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU3_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU3_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU3_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU3_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40025000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU3_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU3_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU3_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU3_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU3_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU3_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU3_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU3_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU3_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40025000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU3_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU3_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU3_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU3_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU3_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU3_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU3_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU3_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU3_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWU4"
|
|
base ad:0x40026000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SWU4_GCTL,SWU Global Control Register"
|
|
bitfld.long 0x00 1. " RST ,Global reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " EN ,Global enable" "Disabled,Enabled"
|
|
line.long 0x04 "SWU4_GSTAT,SWU Global Status Register"
|
|
eventfld.long 0x04 30. " ADDRERR ,Address error status" "Inactive,Active"
|
|
eventfld.long 0x04 15. " OVRBW3 ,Group 3 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 14. " UNDRBW3 ,Group 3 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 13. " OVRBW2 ,Group 2 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 12. " UNDRBW2 ,Group 2 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 11. " OVRBW1 ,Group 1 bandwidth above maximum target" "Not above,Above"
|
|
textline " "
|
|
eventfld.long 0x04 10. " UNDRBW1 ,Group 1 bandwidth below minimum target" "Not below,Below"
|
|
eventfld.long 0x04 9. " OVRBW0 ,Group 0 bandwidth above maximum target" "Not above,Above"
|
|
eventfld.long 0x04 8. " UNDRBW0 ,Group 0 bandwidth below minimum target" "Not below,Below"
|
|
textline " "
|
|
eventfld.long 0x04 7. " INT3 ,Group 3 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " INT2 ,Group 2 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " INT1 ,Group 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " INT0 ,Group 0 interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " MTCH3 ,Group 3 match" "No match,Match"
|
|
eventfld.long 0x04 2. " MTCH2 ,Group 2 match" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MTCH1 ,Group 1 match" "No match,Match"
|
|
eventfld.long 0x04 0. " MTCH0 ,Group 0 match" "No match,Match"
|
|
if (((per.l(ad:0x40026000+0x10+0x0))&0x10000)==0x10000)
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU4_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "SWU4_CTL0,SWU Control Register 0"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x0)++0x13
|
|
line.long 0x00 "SWU4_LA0,SWU Lower Address Register 0"
|
|
line.long 0x04 "SWU4_UA0,SWU Upper Address Register 0"
|
|
line.long 0x08 "SWU4_ID0,SWU ID Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU4_CNT0,Count Register 0"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU4_TARG0,SWU Target Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x0)++0x07
|
|
line.long 0x00 "SWU4_HIST0,SWU Bandwidth History Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU4_CUR0,SWU Current Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40026000+0x10+0x20))&0x10000)==0x10000)
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU4_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x20)++0x03
|
|
line.long 0x00 "SWU4_CTL1,SWU Control Register 1"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x20)++0x13
|
|
line.long 0x00 "SWU4_LA1,SWU Lower Address Register 1"
|
|
line.long 0x04 "SWU4_UA1,SWU Upper Address Register 1"
|
|
line.long 0x08 "SWU4_ID1,SWU ID Register 1"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU4_CNT1,Count Register 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU4_TARG1,SWU Target Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x20)++0x07
|
|
line.long 0x00 "SWU4_HIST1,SWU Bandwidth History Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU4_CUR1,SWU Current Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40026000+0x10+0x40))&0x10000)==0x10000)
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU4_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "SWU4_CTL2,SWU Control Register 2"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x40)++0x13
|
|
line.long 0x00 "SWU4_LA2,SWU Lower Address Register 2"
|
|
line.long 0x04 "SWU4_UA2,SWU Upper Address Register 2"
|
|
line.long 0x08 "SWU4_ID2,SWU ID Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU4_CNT2,Count Register 2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU4_TARG2,SWU Target Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x40)++0x07
|
|
line.long 0x00 "SWU4_HIST2,SWU Bandwidth History Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU4_CUR2,SWU Current Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
if (((per.l(ad:0x40026000+0x10+0x60))&0x10000)==0x10000)
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU4_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "No scaling,1:10,1:100,,1:1000,?..."
|
|
bitfld.long 0x00 20. " STALLCNTMODE ,Stall count mode" "Number of transactions,Number of stalls"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MAXACT ,Action for bandwidth above maximum" "No action,Action"
|
|
bitfld.long 0x00 18. " MINACT ,Action for bandwidth below minimum" "No action,Action"
|
|
bitfld.long 0x00 17. " BLENINC ,Increment bandwidth count by burst length" "Increment by 1,Burst Length Increment"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
else
|
|
group.long (0x10+0x60)++0x03
|
|
line.long 0x00 "SWU4_CTL3,SWU Control Register 3"
|
|
sif (!cpuis("ADSPCM40*"))
|
|
bitfld.long 0x00 24. " DATACNTMODE ,Data channel monitor" "Monitor address channel,Monitor data channel"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " BWEN ,Bandwidth mode enable" "Disabled,Enabled"
|
|
sif (!cpuis("ADSP-SC57*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMEN ,Trace message enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DBGEN ,Debug event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CNTRPTEN ,Count repeat enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CNTEN ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LCMPEN ,Locked comparison enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCMPEN ,Secure comparison enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDCMPEN ,ID comparison Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " ACMPM ,Address comparison mode" "No address comparison,Exact match on LAn,Match on address within range,Match on address outside range"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIR ,Transaction direction for match" "Reads only,Writes only"
|
|
bitfld.long 0x00 0. " EN ,Enable watchpoint" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x60)++0x13
|
|
line.long 0x00 "SWU4_LA3,SWU Lower Address Register 3"
|
|
line.long 0x04 "SWU4_UA3,SWU Upper Address Register 3"
|
|
line.long 0x08 "SWU4_ID3,SWU ID Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " IDMASK ,Identity mask (for Or with ID)"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID ,Identity"
|
|
line.long 0x0C "SWU4_CNT3,Count Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Count"
|
|
line.long 0x10 "SWU4_TARG3,SWU Target Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " BWMAX ,Maximum bandwidth target"
|
|
hexmask.long.word 0x10 0.--15. 1. " BWMIN ,Minimum bandwidth target"
|
|
rgroup.long (0x28+0x60)++0x07
|
|
line.long 0x00 "SWU4_HIST3,SWU Bandwidth History Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from window before last"
|
|
hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from last window"
|
|
line.long 0x04 "SWU4_CUR3,SWU Current Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " CURBW ,Current bandwidth"
|
|
hexmask.long.word 0x04 0.--15. 1. " CURCNT ,Current count"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TAPC (JTAG debug and Serial Wire Debug Port)"
|
|
base ad:0x40029000
|
|
width 14.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IDCODE,IDCODE Register"
|
|
hexmask.long.byte 0x00 28.--31. 1. " REVID ,Silicon revision"
|
|
hexmask.long.word 0x00 12.--27. 1. " JTAGID ,JTAG ID"
|
|
hexmask.long.word 0x00 1.--11. 1. " MNFID ,Manufacturer ID"
|
|
bitfld.long 0x00 0. " LSB ,IDCODE LSB" "0,1"
|
|
line.long 0x04 "USERCODE,USERCODE Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDBGKEY_CTL,Secure Debug Key Control Register"
|
|
bitfld.long 0x00 0. " VALID ,SDBGKEY valid" "Not valid,Valid"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SDBGKEY_STAT,Secure Debug Key Status Register"
|
|
sif cpuis("ADSPCM40*")
|
|
bitfld.long 0x00 2. " VALID ,SDBGKEY is Valid" "Not valid,Valid"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " FAIL ,SDBGKEY match fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " PASS ,SDBGKEY match pass" "Not passed,Passed"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SDBGKEY0,Secure Debug Key 0 Register"
|
|
line.long 0x04 "SDBGKEY1,Secure Debug Key 1 Register"
|
|
line.long 0x08 "SDBGKEY2,Secure Debug Key 2 Register"
|
|
line.long 0x0C "SDBGKEY3,Secure Debug Key 3 Register"
|
|
sif cpuis("ADSPCM40*")
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "USERKEYCMP0,User Key Compare 0 Register"
|
|
line.long 0x04 "USERKEYCMP1,User Key Compare 1 Register"
|
|
line.long 0x08 "USERKEYCMP2,User Key Compare 2 Register"
|
|
line.long 0x0C "USERKEYCMP3,User Key Compare 3 Register"
|
|
if (((per.l(ad:0x40029000+0xF0))&0xAD)==0xAD)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCMSG,Run Control Message Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ERASE_KEY ,Erase Key"
|
|
bitfld.long 0x00 15. " ERASE ,Erase on chip flash" "0,1"
|
|
bitfld.long 0x00 13. " HALTONENTRY ,Halt on Entry" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,Do Not Execute Hook Routine" "Performed,Not performed"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Performed,Not performed"
|
|
bitfld.long 0x00 5. " NOCACHE ,No Cache" "Initialized and enabled,Not initialized or Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No Memory Initialization" "Performed,Not performed"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Executed,Not executed"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No Vector Initialize" "Vector,Not vector"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NOKERNEL ,No Boot Kernel" "Executed,Not executed"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCMSG,Run Control Message Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ERASE_KEY ,Erase Key"
|
|
rbitfld.long 0x00 15. " ERASE ,Erase on chip flash" "0,1"
|
|
bitfld.long 0x00 13. " HALTONENTRY ,Halt on Entry" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " NOHOOK ,Do Not Execute Hook Routine" "Performed,Not performed"
|
|
bitfld.long 0x00 6. " NOFAULTS ,No Faults" "Performed,Not performed"
|
|
bitfld.long 0x00 5. " NOCACHE ,No Cache" "Initialized and enabled,Not initialized or Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NOMEMINIT ,No Memory Initialization" "Performed,Not performed"
|
|
bitfld.long 0x00 2. " HALT ,Halt" "Executed,Not executed"
|
|
bitfld.long 0x00 1. " NOVECTINIT ,No Vector Initialize" "Vector,Not vector"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NOKERNEL ,No Boot Kernel" "Executed,Not executed"
|
|
endif
|
|
group.long 0xF4++0x0B
|
|
line.long 0x00 "RCMSG_CLR,Run Control Message Clear Register"
|
|
line.long 0x04 "RCMSG_SET,Run Control Message Set Register"
|
|
line.long 0x08 "RCMSG_TOG,Run Control Message Toggle Register"
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DBGCTL,Debug Control Register"
|
|
bitfld.long 0x00 15. " SPIDENTRACE ,SPIDEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " NIDENTRACE ,NIDEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DBGENTRACE ,DBGEN for coresight trace modules" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " NIDENCTISYS ,NIDEN for system CTI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBGENCTISYS ,DBGEN for system CTI" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPIDENSTM ,SPIDEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SPNIDENSTM ,SPNIDEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " NIDENSTM ,NIDEN for STM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DBGENSTM ,DBGEN for STM" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DBGENC2 ,DBGEN for core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DBGENC1 ,DBGEN for core 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SPIDENC0 ,SPIDEN for core 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPNIDENC0 ,SPNIDEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NIDENC0 ,NIDEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DBGENC0 ,DBGEN for core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENDAP ,SPIDEN for DAP" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
width 0x0B
|