7357 lines
368 KiB
Plaintext
7357 lines
368 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: A31G2xx On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-06 JDU
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; 2023-11-02 NEJ
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; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
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; @Doc: Generated (TRACE32, build: 164232.), based on:
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; A31G21x_fixed.svd (Ver. 1.0), A31G22x_fixed.svd (Ver. 0.2)
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; @Core: Cortex-M0+
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; @Chip: A31G212CL, A31G212GR, A31G212KN, A31G212SQ, A31G213CL, A31G213GR,
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; A31G213KN, A31G213SQ, A31G224CL2N, A31G224ML2N, A31G224MM2N, A31G224RL2N,
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; A31G224RM2N, A31G224CLN, A31G224MLN, A31G224MMN, A31G224RLN, A31G224RMN,
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; A31G226CL2N, A31G226ML2N, A31G226MM2N, A31G226RL2N, A31G226RM2N,
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; A31G226CLN, A31G226MLN, A31G226MMN, A31G226RLN, A31G226RMN
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pera31g2xx.per 16938 2023-11-07 18:43:11Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
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group.long 0xD9C++0x03 "Region 3"
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
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|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif (cpuis("A31G21*"))
|
|
base ad:0x40003000
|
|
elif (cpuis("A31G22*"))
|
|
base ad:0x40003100
|
|
endif
|
|
tree "ADC (12-bit A/D Converter)"
|
|
sif (cpuis("A31G21*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,A/D Converter Control Register"
|
|
bitfld.long 0x0 15. "ADCEN,A/DC Module Enable bit (The A/DC is automatically disabled at power down mode)" "0: Disable A/DC module operation,1: Enable A/DC module operation"
|
|
bitfld.long 0x0 11.--13. "TRIG,A/DC Trigger Signal Selection bits" "0: ADST,1: Timer 10 A-match signal,2: Timer 11 A-match signal,3: Timer 12 A-match signal,4: A/DC trigger signal from timer 30,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "REFSEL,A/DC Reference Selection bit" "0: Select analog power (VDD),1: Select external reference (AVREF)"
|
|
bitfld.long 0x0 8. "ADST,A/DC Conversion Start bit. This bit is automatically cleared to '0b' after operation" "0: No effect,1: Trigger signal generation for conversion start"
|
|
newline
|
|
bitfld.long 0x0 5. "ADCIEN,A/DC Interrupt Enable bit" "0: Disable A/DC interrupt,1: Enable A/DC interrupt"
|
|
bitfld.long 0x0 4. "ADCIFLAG,A/DC Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADSEL,A/D Converter Channel Selection bits"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DR,A/D Converter Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "ADDATA,A/D Converter Result Data bits"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PREDR,A/D Converter Prescaler Data Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PRED,A/D Converter Prescaler Data bits."
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MR,ADC Mode Register"
|
|
bitfld.long 0x0 21. "TRGINFO,Trigger Information Option (In external trigger mode)" "0,1"
|
|
bitfld.long 0x0 20. "CHINFO,Channel Information Option" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DMAEN,DMA Enable Bit (only ADCEN=1)" "0: DMA Disable,1: DMA Enable"
|
|
hexmask.long.byte 0x0 12.--16. 1. "STSEL,Sampling Time Selection"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SEQCNT,Number of conversion in a sequence" "0: Single Mode,1: 2 Sequence ADC,2: 3 Sequence ADC,3: 4 Sequence ADC,4: 5 Sequence ADC,5: 6 Sequence ADC,6: 7 Sequence ADC,7: 8 Sequence ADC"
|
|
bitfld.long 0x0 7. "ADEN,ADC Enable Bit" "0: Disable ADC,1: Enable ADC"
|
|
newline
|
|
bitfld.long 0x0 6. "ARST,When sequence is over restart control bit" "0: after ending STOP,1: After ending restart"
|
|
bitfld.long 0x0 4.--5. "ADMOD,ADC Mode Selection Bit" "0: Single_Sequencial Conversion Mode,1: Burst Conversion Mode,2: Multiple Conversion Mode,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRGSEL,Trigger Selection Bit" "0: Software Trigger Only,1: TIMER1n event trigger,2: TIMER30 event trigger,?"
|
|
line.long 0x4 "CSCR,ADC Current Sequence_Channel Register"
|
|
bitfld.long 0x4 8.--10. "CSEQN,Current Sequence Number" "0: Current Sequence 0,1: Current Sequence 1,2: Current Sequence 2,3: Current Sequence 3,4: Current Sequence 4,5: Current Sequence 5,6: Current Sequence 6,7: Current Sequence 7"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CACH,Current Active Channel"
|
|
line.long 0x8 "CCR,ADC Clock Control Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC Clock Divider value bit ADC CLK = ADC Input Clock / CLKDIV (CLKDIV=1 ADC Stop CLKDIV=0 ADC Input Clock)"
|
|
bitfld.long 0x8 7. "ADCPD,ADC Deep Sleep" "0: ADC Normal Mode,1: ADC Deep Sleep Mode"
|
|
newline
|
|
bitfld.long 0x8 6. "EXTCLK,ADC External Clock Setting Bit" "0: ADC Internal Clock (CLKDIV Enable),1: ADC External Clock (SCU Clock)"
|
|
bitfld.long 0x8 5. "CLKINVT,Divide Clock Inversion (Option bit)" "0: duty ratio of divided clock is larger than 50p,1: duty ratio of divided clock is less than 50p"
|
|
line.long 0xC "TRG,ADC Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,Sequence Trigger Source 8th"
|
|
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,Sequence Trigger Source 7th"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,Sequence Trigger Source 6th"
|
|
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,Sequence Trigger Source 5th"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,Sequence Trigger Source 4th"
|
|
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,Sequence Trigger Source 3th"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,Sequence Trigger Source 2th"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0_BSTTRG,Sequence Trigger Source 1th Burst Conversion Trigger Source"
|
|
group.long 0x18++0x13
|
|
line.long 0x0 "SCSR1,ADC Channel Selection Register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SEQ3CH,Conversion Sequence Channel Selection 4th"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SEQ2CH,Conversion Sequence Channel Selection 3th"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "SEQ1CH,Conversion Sequence Channel Selection 2th"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEQ0CH,Conversion Sequence Channel Selection 1th"
|
|
line.long 0x4 "SCSR2,ADC Channel Selection Register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SEQ7CH,Conversion Sequence Channel Selection 8th"
|
|
hexmask.long.byte 0x4 16.--20. 1. "SEQ6CH,Conversion Sequence Channel Selection 7th"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "SEQ5CH,Conversion Sequence Channel Selection 6th"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEQ4CH,Conversion Sequence Channel Selection 5th"
|
|
line.long 0x8 "CR,ADC Control Register"
|
|
bitfld.long 0x8 7. "ASTOP,ADC STOP bit" "0,1"
|
|
bitfld.long 0x8 1. "TRGCLR,ADC all trigger flags cleared option (previous ADC operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ASTART,ADC START Bit" "0,1"
|
|
line.long 0xC "SR,ADC Status Register"
|
|
bitfld.long 0xC 8. "CMPIFLG,Compare Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0xC 5. "DOVRUN,DMA Overrun Flag (Not Interrupt)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "DMAIF,DMA Done Interrupt Flag (DMA transfer is completed)" "0,1"
|
|
bitfld.long 0xC 3. "TRGIF,ADC Trigger Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EOSIF,Sequence End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
bitfld.long 0xC 0. "EOCIF,Sequence Conversion End Interrupt Flag (Write '1' to clear flag)" "0,1"
|
|
line.long 0x10 "IER,ADC Interrupt Enable Register"
|
|
bitfld.long 0x10 4. "DMAIE,DMA Done Interrupt Enable" "0: DMA Interrupt Disable,1: DMA Interrupt Enable"
|
|
bitfld.long 0x10 3. "TRGIE,ADC Trigger Conversion Interrupt Enable" "0: ADC Trigger Conversion Interrupt Disable,1: ADC Trigger Conversion Interrupt Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "EOSIE,ADC Sequence Conversion Interrupt Enable" "0: ADC Sequence Conversion Interrupt Disable,1: ADC Sequence Conversion Interrupt Enable"
|
|
bitfld.long 0x10 0. "EOCIE,ADC Single Conversion Interrupt Enable" "0: ADC Single Conversion Interrupt Disable,1: ADC Single Conversion Interrupt Enable"
|
|
rgroup.long 0x2C++0x23
|
|
line.long 0x0 "DDR,ADC DMA Data Register"
|
|
bitfld.long 0x0 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x0 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "ADMACH,ADC Data Channel Indicator"
|
|
hexmask.long.word 0x0 4.--15. 1. "ADDMAR,ADC Conversion Result Data (12-bit)"
|
|
line.long 0x4 "DR0,ADC Sequence Data Register0"
|
|
bitfld.long 0x4 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x4 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x4 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x8 "DR1,ADC Sequence Data Register1"
|
|
bitfld.long 0x8 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x8 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x8 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0xC "DR2,ADC Sequence Data Register2"
|
|
bitfld.long 0xC 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0xC 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0xC 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x10 "DR3,ADC Sequence Data Register3"
|
|
bitfld.long 0x10 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x10 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x10 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x14 "DR4,ADC Sequence Data Register4"
|
|
bitfld.long 0x14 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x14 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x14 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x18 "DR5,ADC Sequence Data Register5"
|
|
bitfld.long 0x18 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x18 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x18 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x1C "DR6,ADC Sequence Data Register6"
|
|
bitfld.long 0x1C 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x1C 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x1C 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
line.long 0x20 "DR7,ADC Sequence Data Register7"
|
|
bitfld.long 0x20 31. "TRGINFO7,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 30. "TRGINFO6,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 29. "TRGINFO5,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 28. "TRGINFO4,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 27. "TRGINFO3,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 26. "TRGINFO2,ADC Trigger Information" "0,1"
|
|
newline
|
|
bitfld.long 0x20 25. "TRGINFO1,ADC Trigger Information" "0,1"
|
|
bitfld.long 0x20 24. "TRGINFO0,ADC Trigger Information" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--20. 1. "ACH,ADC Channel Information"
|
|
hexmask.long.word 0x20 4.--15. 1. "ADDATA,ADC Channel Data (12-bit)"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "CMPR,ADC Channel Compare Register"
|
|
bitfld.long 0x0 24. "CMPIEN,Compare Interrupt Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
bitfld.long 0x0 23. "CMPEN,Compare Operation Enable Bit" "0: Compare Disable,1: Compare Enable"
|
|
newline
|
|
bitfld.long 0x0 21. "LTE,AD Conversion Value Output Timing Setting" "0: If ADC value is higher than CVAL value output.,1: If the ADC value is lower than the CVAL value it.."
|
|
hexmask.long.byte 0x0 16.--20. 1. "CCH,Compare Channel"
|
|
newline
|
|
hexmask.long.word 0x0 4.--15. 1. "CVAL,Compare Value"
|
|
line.long 0x4 "BCR,ADC Buffer Control Register"
|
|
bitfld.long 0x4 4.--6. "TBUFSEL,Buffering Off Time Selection Bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1. "BUFEN,ADC Input Buffer Enable Bit" "0: Input Buffer Power Dcown Period,1: Input Buffer Operation Period"
|
|
newline
|
|
bitfld.long 0x4 0. "BYPSEL,ADC Input Buffer Bypass Selection Bit" "0: Input Buffer Operation mode,1: Input Buffer Bypass Mode"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("A31G22*"))
|
|
tree "CFMC (Code Flash Memory Controller)"
|
|
base ad:0x40000100
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Code Flash Memory Mode Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ACODE,Access Code."
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "INIT,Code Flash Memory INIT Register"
|
|
bitfld.long 0x0 29. "RSTBUSY,RSTBUSY status bit - sychronized with PCLK" "0,1"
|
|
bitfld.long 0x0 28. "RBSFLAG,1st RSTBUSY flag bit" "0,1"
|
|
bitfld.long 0x0 24. "FRBSFLG,2nd RSTBUSY flag bit" "0,1"
|
|
bitfld.long 0x0 0. "FUSERD,Fuse read bit. this bit must be set before DCT read in BootROM mode." "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "CR,Code Flash Memory Control Register"
|
|
bitfld.long 0x0 25. "BSAEN,Bank selection block access enable" "0,1"
|
|
bitfld.long 0x0 24. "RPAEN,Read protection block access enable" "0,1"
|
|
bitfld.long 0x0 23. "SELFPGM,When this bit is set(1) PGM/ERS/HVEN will be cleared automatically after WRBUSY falling edge. It also enable CPU wait control when HVEN bit is set(1)" "0,1"
|
|
bitfld.long 0x0 12. "IFAEN,Info(User Data0 User Data1 User Data2) block access enable" "0,1"
|
|
bitfld.long 0x0 7. "MAS,Mass(bulk) erase enable" "0,1"
|
|
bitfld.long 0x0 6. "SECT4K,Sector 4K erase enable" "0,1"
|
|
bitfld.long 0x0 5. "SECT1K,Sector 1K erase enable" "0,1"
|
|
bitfld.long 0x0 4. "PMODE,PMODE enable" "0,1"
|
|
bitfld.long 0x0 3. "WADCK,Program/Erase address data latch clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PGM,Program mode enable" "0,1"
|
|
bitfld.long 0x0 1. "ERS,Erase mode enable" "0,1"
|
|
bitfld.long 0x0 0. "HVEN,High Voltage cycle enable" "0,1"
|
|
line.long 0x4 "AR,Code Flash Memory Address Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "FADDR,Word(32-bit) base address : 64K-word address for 256KB Flash."
|
|
line.long 0x8 "DR,Code Flash Memory Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATA,Word size(32-bit) data"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "BUSY,Code Flash Memory Write Busy Status Register"
|
|
bitfld.long 0x0 0. "WRBUSY,Write Busy status bit" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CRCCCITT,Code Flash Memory CRC-CCITT Check Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CRC,CRC-CCITT check value read register"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "CFG,Code Flash Memory Config Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x7858 to these bits otherwise the write is ignored."
|
|
bitfld.long 0x0 8.--10. "WAIT,This bits only be written in AMBA mode and MSB 16-bit (bit [31:16]) must be 0x7858" "0: wait) /,1: wait) /,2: wait),3: wait),4: wait),5: wait),?,?"
|
|
bitfld.long 0x0 7. "CRCINIT,When this bit is set('1') CRC register will be initialized" "0,1"
|
|
bitfld.long 0x0 6. "CRCEN,CRC-CCITT enable" "0,1"
|
|
line.long 0x4 "WPROT,Flash Memory Write Protection Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "WPROT,Write protection"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "RPROT,Code Flash Memory Read Protection Register"
|
|
rbitfld.long 0x0 31. "DBGMOD,Debug Operating Status bit" "0,1"
|
|
rbitfld.long 0x0 30. "SRBOOT,SRAM Boot Mode Status bit" "0,1"
|
|
rbitfld.long 0x0 26. "PWMATCH,Password Match Flag bit" "0,1"
|
|
rbitfld.long 0x0 25. "RPBERSD,Chip Erase and Read Protection Block Erase Done Flag bit" "0,1"
|
|
rbitfld.long 0x0 24. "CERSD,Chip Erase Done Flag bit" "0,1"
|
|
rbitfld.long 0x0 17. "LVL2_STS,Protection Level 2 Status bit (raw data)" "0,1"
|
|
rbitfld.long 0x0 16. "LVL1_STS,Protection Level 1 Status bit (raw data)" "0,1"
|
|
rbitfld.long 0x0 9. "LVL2_EN,Protection Level 2 Enable Status bit" "0,1"
|
|
rbitfld.long 0x0 8. "LVL1_EN,Protection Level 1 Enable Status bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RPROT,Read protection"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "PWIN,Code Flash Memory Password Input Register"
|
|
hexmask.long 0x0 0.--31. 1. "PWIN,Password input data bit"
|
|
line.long 0x4 "PWPRST,Code Flash Memory Password Preset Register"
|
|
hexmask.long 0x4 0.--31. 1. "PWPRST,Password preset data bit"
|
|
group.long 0x48++0xF
|
|
line.long 0x0 "BCR,Code Flash Memory Bank Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key."
|
|
bitfld.long 0x0 4. "BSE,Memory Bank Selection Enable bit for swap operation" "0,1"
|
|
bitfld.long 0x0 0. "BSW,Bank Swap" "0,1"
|
|
line.long 0x4 "BSR,Code Flash Memory Bank Status Register"
|
|
bitfld.long 0x4 12. "BSERR,Error handling flag bit for Bank Selection" "0,1"
|
|
bitfld.long 0x4 8. "CBF,Current Boot bank flag bit" "0,1"
|
|
rbitfld.long 0x4 4. "BSST,Bank Selection Status bit" "0,1"
|
|
rbitfld.long 0x4 0. "BSWST,Bank Swap Status bit" "0,1"
|
|
line.long 0x8 "ABWPROT,Code Flash Memory Active Bootloader Area Write Protection Register"
|
|
hexmask.long.word 0x8 20.--31. 1. "AB_KEY,Write protection key value 0xAAB for the active bootloader area"
|
|
hexmask.long.word 0x8 0.--15. 1. "AB_WPROT,1KB write protection of user bootloader area in active bank"
|
|
line.long 0xC "NBWPROT,Code Flash Memory Non-active Bootloader Area Write Protection Register"
|
|
hexmask.long.word 0xC 20.--31. 1. "NB_KEY,Write protection key value 0x55B for the non-active bootloader area"
|
|
hexmask.long.word 0xC 0.--15. 1. "NB_WPROT,1KB write protection of user bootloader area in non-active bank"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "BOOT,Code Flash Memory Boot Register"
|
|
bitfld.long 0x0 8. "SRAMBOOT,SRAM Boot mode bit" "0,1"
|
|
bitfld.long 0x0 7. "INITFLG,Code Flash Initialize for debug" "0,1"
|
|
bitfld.long 0x0 6. "FERR,Code Flash Error bit for debug" "0,1"
|
|
bitfld.long 0x0 4. "SREMAP,SRAM Re-Map enable bit" "0,1"
|
|
rbitfld.long 0x0 0. "BOOTMD,Bootloader mode bit" "0,1"
|
|
line.long 0x4 "TMR,Code Flash Memory Timer Counter Register"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "TIMER,Code Flash Timer Counter"
|
|
line.long 0x8 "TICK,Code Flash Memory Tick Timer Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "TICK,Code Flash Tick Timer"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "TEST,Code Flash Memory TEST Register"
|
|
bitfld.long 0x0 31. "TESTFLG,Test Flash" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HIDDEN1,Hidden Test Enable 1"
|
|
bitfld.long 0x0 21.--22. "HIDDEN0,Hidden Test Enable 0" "0,1,2,3"
|
|
bitfld.long 0x0 20. "STOP,Flash Stop bit control" "0,1"
|
|
hexmask.long.word 0x0 8.--16. 1. "PROT,PROT[8:0] area access enable"
|
|
bitfld.long 0x0 7. "TSMODE,TSMODE set" "0,1"
|
|
bitfld.long 0x0 6. "TREGSEL,TREG selection (test register in flash IP)" "0,1"
|
|
bitfld.long 0x0 3. "DCT,DCT area access enable bit" "0,1"
|
|
bitfld.long 0x0 2. "LDTEN,LDT area access enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "REDEN,RED area access enable bit" "0,1"
|
|
bitfld.long 0x0 0. "MCS,MCS control bit" "0,1"
|
|
line.long 0x4 "HWID,Code Flash Memory Hardware ID Register"
|
|
line.long 0x8 "SIZE,Code Flash Memory Size Register"
|
|
rgroup.long 0x90++0x7
|
|
line.long 0x0 "DCT0,Code Flash Memory DCT0 Register"
|
|
line.long 0x4 "DCT1,Code Flash Memory DCT0 Register"
|
|
tree.end
|
|
tree "CMP (Comparator)"
|
|
base ad:0x40003420
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CMP0CR,Comparator 0 Control Register"
|
|
bitfld.long 0x0 20. "C0HYSEN,Comparator 0 Hysteresis Enable" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
bitfld.long 0x0 16. "C0HYSSEL,Comparator 0 Hysteresis Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "C0EN,Comparator 0 Enable bits" "0: Disable Comparator,1: Enable Comparator"
|
|
bitfld.long 0x0 4.--5. "C0INNSEL,Comparator 0 Reference (input -) Selection bit" "0: CREF0,1: BGR,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "C0INPSEL,Comparator 0 Source (input +) Selection bit" "0: CP0,1: GND,?,?"
|
|
line.long 0x4 "CMP1CR,Comparator 1 Control Register"
|
|
bitfld.long 0x4 20. "C1HYSEN,Comparator 1 Hysteresis Enable" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
bitfld.long 0x4 16. "C1HYSSEL,Comparator 1 Hysteresis Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "C1EN,Comparator 1 Enable bits" "0: Disable Comparator,1: Enable Comparator"
|
|
bitfld.long 0x4 4.--5. "C1INNSEL,Comparator Reference (input -) Selection bit" "0: CREF1,1: BGR,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "C1INPSEL,Comparator Source (input +) Selection bit" "0: CP1A,1: CP1B,?,?"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "DBNC,Comparator Debounce Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBNCTB,Debounce time base counter"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C1DBNC,Debounce shift Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "C0DBNC,Debounce shift Selection"
|
|
line.long 0x4 "ICON,Comparator Interrupt Control Register"
|
|
bitfld.long 0x4 13. "C1TPOL,Comparator 1 Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
|
|
bitfld.long 0x4 12. "C0TPOL,Comparator 0 Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
|
|
newline
|
|
bitfld.long 0x4 9. "C1IPOL,Comparator 1 interrupt polarity (level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
|
|
bitfld.long 0x4 8. "C0IPOL,Comparator 0 interrupt polarity (level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "C1IMODE,Comparator 1 Interrupt Mode" "0: level interrupt,1: rising edge interrupt,?,?"
|
|
bitfld.long 0x4 0.--1. "C0IMODE,Comparator 0 Interrupt Mode" "0: level interrupt,1: rising edge interrupt,?,?"
|
|
line.long 0x8 "IEN,Comparator Interrupt Enable Register"
|
|
bitfld.long 0x8 7. "COUTMON,Enable Comparator output monitoring" "0: Disable,1: Enable"
|
|
bitfld.long 0x8 1. "C1IEN,Comparator 1 Interrupt Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 0. "C0IEN,Comparator 0 Interrupt Enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IST,Comparator Interrupt Status Register"
|
|
bitfld.long 0x0 19. "C1EPF,The falling edge polarity status flag of comparator 1" "0: None,1: Comparator 1 edge polarity is falling"
|
|
bitfld.long 0x0 18. "C1EPR,The rising edge polarity status flag of comparator 1" "0: None,1: Comparator 1 edge polarity is rising"
|
|
newline
|
|
bitfld.long 0x0 17. "C0EPF,The falling edge polarity status flag of comparator 0" "0: None,1: Comparator 0 edge polarity is falling"
|
|
bitfld.long 0x0 16. "C0EPR,The rising edge polarity status flag of comparator 0" "0: None,1: Comparator 0 edge polarity is rising"
|
|
newline
|
|
bitfld.long 0x0 13. "C1COUT,Comparator 1 current output status" "0: Current output is low,1: current output is high"
|
|
bitfld.long 0x0 12. "C0COUT,Comparator 0 current output status" "0: Current output is low,1: current output is high"
|
|
newline
|
|
bitfld.long 0x0 9. "C1DO,Comparator 1 debounce output status" "0: None,1: Debounced output"
|
|
bitfld.long 0x0 8. "C0DO,Comparator 0 debounce output status" "0: None,1: Debounced output"
|
|
newline
|
|
bitfld.long 0x0 1. "C1IRQ,Comparator 1 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
|
|
bitfld.long 0x0 0. "C0IRQ,Comparator 0 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ICLR,Comparator Interrupt Clear Register"
|
|
bitfld.long 0x0 19. "C1EPFFC,Comparator 1 Edge Polarity Falling Flag Clear (write '1' to clear C1EPFFC)" "0,1"
|
|
bitfld.long 0x0 18. "C1EPRFC,Comparator 1 Edge Polarity Rising Flag Clear (write '1' to clear C1EPRFC)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "C0EPFFC,Comparator 0 Edge Polarity Falling Flag Clear (write '1' to clear C0EPFFC)" "0,1"
|
|
bitfld.long 0x0 16. "C0EPRFC,Comparator 0 Edge Polarity Rising Flag Clear (write '1' to clear C0EPRFC)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "C1ICLR,Comparator 1 Interrupt Clear (write '1' to clear C1IRQ)" "0,1"
|
|
bitfld.long 0x0 0. "C0ICLR,Comparator 0 Interrupt Clear (write '1' to clear C0IRQ)" "0,1"
|
|
tree.end
|
|
tree "DFMC (Data Flash Memory Controller)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "INIT,DATA Flash Memory INIT Register"
|
|
bitfld.long 0x0 29. "RSTBUSY,RSTBUSY status bit - sychronized with PCLK" "0,1"
|
|
bitfld.long 0x0 28. "RBSFLAG,1st RSTBUSY flag bit" "0,1"
|
|
bitfld.long 0x0 24. "FRBSFLG,2nd RSTBUSY flag bit" "0,1"
|
|
bitfld.long 0x0 0. "FUSERD,Fuse read bit. this bit must be set before DCT read in BootROM mode." "0,1"
|
|
line.long 0x4 "MR,Data Flash Memory Mode Register"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ACODE,Access Code."
|
|
line.long 0x8 "CR,Data Flash Memory Control Register"
|
|
bitfld.long 0x8 24. "RPAEN,Read protection block access enable" "0,1"
|
|
bitfld.long 0x8 16. "WPGMEN,When the 'PMODE' bit is set to '1' 32-bit unit flash writing is possible. otherwise 8-bit unit flash writing is possible." "0,1"
|
|
bitfld.long 0x8 7. "MAS,Mass(bulk) erase enable" "0,1"
|
|
bitfld.long 0x8 6. "SECT4K,Sector 4K erase enable" "0,1"
|
|
bitfld.long 0x8 5. "SECT1K,Sector 1K erase enable" "0,1"
|
|
bitfld.long 0x8 4. "PMODE,PMODE enable" "0,1"
|
|
bitfld.long 0x8 3. "WADCK,Program/Erase address data latch clock enable" "0,1"
|
|
bitfld.long 0x8 2. "PGM,Program mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ERS,Erase mode enable" "0,1"
|
|
bitfld.long 0x8 0. "HVEN,High Voltage cycle enable" "0,1"
|
|
line.long 0xC "AR,Data Flash Memory Address Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "FADDR,Word(32-bit) base address : 64K-word address for 256KB Flash."
|
|
line.long 0x10 "DR,Data Flash Memory Data Register"
|
|
hexmask.long 0x10 0.--31. 1. "FDATA,Byte size(8-bit) data when 8-bit write mode (WPGMEN=0) Word size (32-bit) data when 32-bit write mode (WPGMEN=1)"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "BUSY,Data Flash Memory Write Busy Status Register"
|
|
bitfld.long 0x0 0. "WRBUSY,Write Busy status bit" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CRCCCITT,Data Flash Memory CRC-CCITT Check Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CRC,CRC16 check value read register"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "CFG,Data Flash Memory Config Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x7858 to these bits otherwise the write is ignored."
|
|
bitfld.long 0x0 8.--10. "WAIT,This bits only be written in AMBA mode and MSB 16-bit (bit [31:16]) must be 0x7858" "0: wait) /,1: wait) /,2: wait),3: wait),4: wait),5: wait),?,?"
|
|
bitfld.long 0x0 7. "CRCINIT,When this bit is set('1') CRC register will be initialized" "0,1"
|
|
bitfld.long 0x0 6. "CRCEN,CRC-CCITT enable" "0,1"
|
|
line.long 0x4 "WPROT,Data Flash Memory Write Protection Register"
|
|
hexmask.long 0x4 0.--31. 1. "WPROT,Write protection"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "RPROT,Data Flash Memory Read Protection Register"
|
|
rbitfld.long 0x0 31. "DBGMOD,Debug Operating Status bit" "0,1"
|
|
rbitfld.long 0x0 30. "SRBOOT,SRAM Boot Mode Status bit" "0,1"
|
|
rbitfld.long 0x0 26. "PWMATCH,Password Match Flag bit" "0,1"
|
|
rbitfld.long 0x0 25. "RPBERSD,Chip Erase and Read Protection Block Erase Done Flag bit" "0,1"
|
|
rbitfld.long 0x0 24. "CERSD,Chip Erase Done Flag bit" "0,1"
|
|
rbitfld.long 0x0 16. "RPROT_STS,Read Protection Status bit (raw data)" "0,1"
|
|
rbitfld.long 0x0 8. "RPROT_EN,Read Protection Enable Status" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RPROT,Read protection"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "PWIN,Data Flash Memory Password Input Register"
|
|
hexmask.long 0x0 0.--31. 1. "PWIN,Password input data bit"
|
|
line.long 0x4 "PWPRST,Data Flash Memory Password Preset Register"
|
|
hexmask.long 0x4 0.--31. 1. "PWPRST,Password preset data bit"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "TEST,Code Flash Memory TEST Register"
|
|
bitfld.long 0x0 31. "TESTFLG,Test Flash" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HIDDEN1,Hidden Test Enable 1"
|
|
bitfld.long 0x0 21.--22. "HIDDEN0,Hidden Test Enable 0" "0,1,2,3"
|
|
bitfld.long 0x0 20. "STOP,Flash Stop bit control" "0,1"
|
|
hexmask.long.word 0x0 8.--16. 1. "PROT,PROT[8:0] area access enable"
|
|
bitfld.long 0x0 7. "TSMODE,TSMODE set" "0,1"
|
|
bitfld.long 0x0 6. "TREGSEL,TREG selection (test register in flash IP)" "0,1"
|
|
bitfld.long 0x0 3. "DCT,DCT area access enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LDTEN,LDT area access enable bit" "0,1"
|
|
bitfld.long 0x0 1. "REDEN,RED area access enable bit" "0,1"
|
|
bitfld.long 0x0 0. "MCS,MCS control bit" "0,1"
|
|
rgroup.long 0x90++0x7
|
|
line.long 0x0 "DCT0,Code Flash Memory DCT0 Register"
|
|
line.long 0x4 "DCT1,Code Flash Memory DCT0 Register"
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0x0
|
|
tree "DMAC0"
|
|
base ad:0x40000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC1"
|
|
base ad:0x40000410
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC2"
|
|
base ad:0x40000420
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC3"
|
|
base ad:0x40000430
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC4"
|
|
base ad:0x40000440
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC5"
|
|
base ad:0x40000450
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC6"
|
|
base ad:0x40000460
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree "DMAC7"
|
|
base ad:0x40000470
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 4. "DMARC,DMA Request Clear" "0: The data to be transmitted remains,1: All data has been transmitted"
|
|
newline
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
bitfld.long 0xC 29.--30. "OFFSET,Memory or Peripheral Base Offset" "?,1: Peripheral to Memory,?,?"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAR,The target address of data transfer."
|
|
tree.end
|
|
tree.end
|
|
tree "LCD (LCD Driver)"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,LCD Driver Control Register"
|
|
bitfld.long 0x0 6.--7. "IRSEL,Internal LCD Bias Driving Resistor bit" "0: RLCD3:105/105/80[kohm]@(1/2)/(1/3)/(1/4) bias.,1: RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias.,2: RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias.,3: RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias."
|
|
bitfld.long 0x0 3.--5. "DBS,LCD Duty and Bias Selection bits." "0: 1/8 duty 1/4 bias.,1: 1/6 duty 1/4 bias.,2: 1/5 duty 1/3 bias.,3: 1/4 duty 1/3 bias.,4: 1/3 duty 1/3 bias.,5: 1/3 duty 1/2 bias.,?,?"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "LCLK,LCD Clock Selection bits (When fLCD = 32.768kHz)." "0: 128Hz,1: 256Hz,2: 512Hz,3: 1024Hz"
|
|
bitfld.long 0x0 0. "DISP,LCD Display Control bit." "0: Display off.,1: Normal display on."
|
|
line.long 0x4 "BCCR,LCD Automatic Bias and Contrast Control Register"
|
|
bitfld.long 0x4 12. "LCDABC,LCD Automatic Bias Control bit." "0: LCD automatic bias is off.,1: LCD automatic bias is on."
|
|
bitfld.long 0x4 8.--10. "BMSEL,'Bias Mode A' Time Selection bits. Refer to the figure 'LCD automatic bias control'." "0: 'Bias Mode A' for 1-clock of fLCD.,1: 'Bias Mode A' for 2-clock of fLCD.,2: 'Bias Mode A' for 3-clock of fLCD.,3: 'Bias Mode A' for 4-clock of fLCD.,4: 'Bias Mode A' for 5-clock of fLCD.,5: 'Bias Mode A' for 6-clock of fLCD.,6: 'Bias Mode A' for 7-clock of fLCD.,7: 'Bias Mode A' for 8-clock of fLCD."
|
|
newline
|
|
bitfld.long 0x4 5. "LCTEN,LCD Driver Contrast Control bit." "0: Disable LCD driver contrast.,1: Enable LCD driver contrast."
|
|
hexmask.long.byte 0x4 0.--3. 1. "VLCD,VLC0 Voltage Control when the contrast is enabled."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "BSSR,LCD Bias Source Selection Register"
|
|
bitfld.long 0x0 9. "LCDDR,LCD Driving Resistor for Bias Select" "0: Internal LCD driving resistors for bias,1: External LCD driving resistors for bias"
|
|
bitfld.long 0x0 8. "LCDEPEN,LCD External Bias Path Enable bit" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 7. "VLC3EN,Extenal Bias VLC3 Enable bit" "0: Disable VLC3,1: Enable VLC3"
|
|
bitfld.long 0x0 6. "VLC2EN,Extenal Bias VLC2 Enable bit" "0: Disable VLC2,1: Enable VLC2"
|
|
newline
|
|
bitfld.long 0x0 5. "VLC1EN,Extenal Bias VLC1 Enable bit" "0: Disable VLC1,1: Enable VLC1"
|
|
bitfld.long 0x0 4. "VLC0EN,Extenal Bias VLC0 Enable bit" "0: Disable VLC0,1: Enable VLC0"
|
|
group.byte 0x10++0x2B
|
|
line.byte 0x0 "LCDDR0,LCD Display Data Register 0"
|
|
line.byte 0x1 "LCDDR1,LCD Display Data Register 1"
|
|
line.byte 0x2 "LCDDR2,LCD Display Data Register 2"
|
|
line.byte 0x3 "LCDDR3,LCD Display Data Register 3"
|
|
line.byte 0x4 "LCDDR4,LCD Display Data Register 4"
|
|
line.byte 0x5 "LCDDR5,LCD Display Data Register 5"
|
|
line.byte 0x6 "LCDDR6,LCD Display Data Register 6"
|
|
line.byte 0x7 "LCDDR7,LCD Display Data Register 7"
|
|
line.byte 0x8 "LCDDR8,LCD Display Data Register 8"
|
|
line.byte 0x9 "LCDDR9,LCD Display Data Register 9"
|
|
line.byte 0xA "LCDDR10,LCD Display Data Register 10"
|
|
line.byte 0xB "LCDDR11,LCD Display Data Register 11"
|
|
line.byte 0xC "LCDDR12,LCD Display Data Register 12"
|
|
line.byte 0xD "LCDDR13,LCD Display Data Register 13"
|
|
line.byte 0xE "LCDDR14,LCD Display Data Register 14"
|
|
line.byte 0xF "LCDDR15,LCD Display Data Register 15"
|
|
line.byte 0x10 "LCDDR16,LCD Display Data Register 16"
|
|
line.byte 0x11 "LCDDR17,LCD Display Data Register 17"
|
|
line.byte 0x12 "LCDDR18,LCD Display Data Register 18"
|
|
line.byte 0x13 "LCDDR19,LCD Display Data Register 19"
|
|
line.byte 0x14 "LCDDR20,LCD Display Data Register 20"
|
|
line.byte 0x15 "LCDDR21,LCD Display Data Register 21"
|
|
line.byte 0x16 "LCDDR22,LCD Display Data Register 22"
|
|
line.byte 0x17 "LCDDR23,LCD Display Data Register 23"
|
|
line.byte 0x18 "LCDDR24,LCD Display Data Register 24"
|
|
line.byte 0x19 "LCDDR25,LCD Display Data Register 25"
|
|
line.byte 0x1A "LCDDR26,LCD Display Data Register 26"
|
|
line.byte 0x1B "LCDDR27,LCD Display Data Register 27"
|
|
line.byte 0x1C "LCDDR28,LCD Display Data Register 28"
|
|
line.byte 0x1D "LCDDR29,LCD Display Data Register 29"
|
|
line.byte 0x1E "LCDDR30,LCD Display Data Register 30"
|
|
line.byte 0x1F "LCDDR31,LCD Display Data Register 31"
|
|
line.byte 0x20 "LCDDR32,LCD Display Data Register 32"
|
|
line.byte 0x21 "LCDDR33,LCD Display Data Register 33"
|
|
line.byte 0x22 "LCDDR34,LCD Display Data Register 34"
|
|
line.byte 0x23 "LCDDR35,LCD Display Data Register 35"
|
|
line.byte 0x24 "LCDDR36,LCD Display Data Register 36"
|
|
line.byte 0x25 "LCDDR37,LCD Display Data Register 37"
|
|
line.byte 0x26 "LCDDR38,LCD Display Data Register 38"
|
|
line.byte 0x27 "LCDDR39,LCD Display Data Register 39"
|
|
line.byte 0x28 "LCDDR40,LCD Display Data Register 40"
|
|
line.byte 0x29 "LCDDR41,LCD Display Data Register 41"
|
|
line.byte 0x2A "LCDDR42,LCD Display Data Register 42"
|
|
line.byte 0x2B "LCDDR43,LCD Display Data Register 43"
|
|
tree.end
|
|
tree "TS (Temperature Sensor)"
|
|
base ad:0x40006300
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,Temperature Sensor Control Register"
|
|
bitfld.long 0x0 8. "INTEN,TS Interrupt Enable bit" "0: Disable temp sensor interrupt,1: Enable temp sensor interrupt. When TS_SR flag is.."
|
|
bitfld.long 0x0 0. "START,start reference clock counting" "0: Stop reference clock counting,1: Start auto clear this bit to '0' after 1 set."
|
|
line.long 0x4 "RCCNT,Temperature Sensor Reference Clock Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "RCCV,Reference Clock Counter Initaial Value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCCNT,Temperature Sensor Sensing Clock Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "SCCV,Temp Sensor Clock Counter value"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SR,Temperature Sensor Status Register"
|
|
bitfld.long 0x0 8. "DONE,Reference Clock Counting Done Flag" "0: Reference clock counter is running.,1: Reference clock counting is done. When reference.."
|
|
rbitfld.long 0x0 0. "BUSY,The Status of the reference clock counter" "0: Reference clock counter is ready.,1: Reference clock counter is busy. BUSY flag is.."
|
|
tree.end
|
|
endif
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40000300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,CRC/Checksum Control Register. Notes: 1. The CRCRLT register and the CRC/Checksum block should be initialized by writing '1b' to the RLTCLR bit before a new CRC/Checksum calculation. 2. The CRCRUN bit should be set to '1b' last time after setting.."
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 21. "OUT_INV,CRC output data inversion" "0: Disable Output data inversion,1: Enable Output data inversion"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20. "OUT_REV,CRC output data reverse" "0: Disable reverse Output data,1: Enable reverse Output data"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16. "IN_REV,Selects the first data bit to be calculated" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 9. "CRCINTEN,CRC interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 8. "CRCINTF,CRC interrupt flag bit" "0,1"
|
|
bitfld.long 0x0 7. "MODS,User/Auto Mode Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RLTCLR,CRC/Checksum Result Data Register (CRCRLT) Initialization bit" "0,1"
|
|
bitfld.long 0x0 5. "MDSEL,CRC/Checksum Selection bit" "0,1"
|
|
bitfld.long 0x0 4. "POLYS,Polynomial Selection bit (CRC only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FIRSTBS,First Shifted-in Selection bit (CRC only)" "0,1"
|
|
bitfld.long 0x0 0. "CRCRUN,CRC/Checksum Start Control and Busy bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "DMADINT,The DMA done interrupt" "0: Disable DMA done interrupt,1: Enable DMA done interrupt"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1.--2. "POLY,Polynomial selection" "0: CRC32 polynomial (0x04C1_1DB7),1: CRC16 polynomial (0x8005),2: CRC8 polynomial (0x07),3: CRC7 Polynomial (0x09)"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "INIT_EN,CRC initial value" "0: No Effect,1: Applies the initial value register value"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "IN,CRC/Checksum Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "INDATA,CRC Input Data bit"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RLT,CRC/Checksum Result Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RLTDATA,CRC Result Data bit"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "INIT,CRC/Checksum Initial Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INIDATA,CRC Initial Data bit"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "INIT,CRC Initial Data Register"
|
|
wgroup.byte 0x8++0x0
|
|
line.byte 0x0 "IDR,CRC Input Data Register"
|
|
hexmask.byte 0x0 0.--7. 1. "INPUT,CRC input data"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ODR,CRC Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "OUTPUT,CRC output data"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SR,CRC Status Register"
|
|
bitfld.long 0x0 8. "DMADINT,DMA done interrupt flag" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "DAC (D/A Converter)"
|
|
base ad:0x40003450
|
|
sif (cpuis("A31G21*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,D/A Converter Control Register"
|
|
bitfld.long 0x0 0. "DACEN,D/A Converter Enable Bit" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DR,D/A Converter Buffer Register"
|
|
hexmask.long.byte 0x0 4.--11. 1. "DADTA,D/A Converter Data Data"
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "DACDR,D/A Converter Data (16-bit)"
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DACEN,D/A Converter Control TEST Register"
|
|
bitfld.long 0x0 0. "DACPORT,D/A output Enable Bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DR,D/A Converter Data Register"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "BR,D/A Converter Buffer Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DACBR,D/A Converter Buffer Data (16-bit)"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CR,D/A Converter Control Register"
|
|
bitfld.long 0x0 13. "DAC2_OUT_EN,Select DAC2_OUT channel for Internal output to DAC_Output of CMP" "0,1"
|
|
bitfld.long 0x0 11. "DAC0_OUT_EN,Select DAC0_OUT channel for DAO(PA6) pin output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DACOUTBUFEN,DAC Output Buffer Selection" "0,1"
|
|
bitfld.long 0x0 4. "DACBC,D/A Converter Buffer Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DACRLDS,D/A Converter Reload Selection. These bits select a reload signal to load data from D/AC data register to buffer." "0,1,2,3"
|
|
bitfld.long 0x0 0. "DACEN,D/A Converter Enable Bit" "0,1"
|
|
line.long 0x4 "PGSR,Programmable Gain Control Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PSG,Programmable Gain Selection"
|
|
line.long 0x8 "OFSCR,D/A Converter Offset Control Register"
|
|
bitfld.long 0x8 7. "OFSEN,D/A Converter Offset Control Enable Bit" "0,1"
|
|
bitfld.long 0x8 6. "OFSDIR,D/A Converter Offset Direction Selection Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "OFS,D/A Converter Offset Value"
|
|
line.long 0xC "ICR,D/A Converter Interrupt Control Register"
|
|
bitfld.long 0xC 5. "DUDRUNF,DMA under-run interrupt flag" "0,1"
|
|
bitfld.long 0xC 4. "DMAIF,DMA done received interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DUDRUNE,DMA under-run interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "DAMIE,DMA done received interrupt enable" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("A31G21*"))
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA0"
|
|
base ad:0x40000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x40000410
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x40000420
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
|
|
tree.end
|
|
tree "DMA3"
|
|
base ad:0x40000430
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR,DMA Channel n Control Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
|
|
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
|
|
line.long 0x4 "SR,DMA Channel n Status Register"
|
|
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
|
|
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
|
|
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
|
|
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
|
|
line.long 0xC "MAR,DMA Channel n Memory Address"
|
|
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
|
|
tree.end
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x40000100
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "MR,Flash Memory Mode Select register"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ACODE,Access Code."
|
|
line.long 0x4 "CR,Flash Memory Control register"
|
|
bitfld.long 0x4 24. "LOCKSEL,LOCK(read protection) access enable." "0,1"
|
|
bitfld.long 0x4 23. "SELFPGM,When this bit is set('1') PGM/ERS/HVEN will be cleared automatically after WRBUSY falling edge. It also enable CPU wait control when HVEN bit is set(1)" "0,1"
|
|
bitfld.long 0x4 12. "IFEN,Info(OTP1/2/3) block enable" "0,1"
|
|
bitfld.long 0x4 8. "BBLOCK,Boot Block(1st 4KB) protection enable/disable from Mass(bulk) erase" "0,1"
|
|
bitfld.long 0x4 7. "MAS,Mass(bulk) erase enable/disable" "0,1"
|
|
bitfld.long 0x4 6. "SECT4K,Sector 4K erase enable/disable" "0,1"
|
|
bitfld.long 0x4 5. "SECT1K,Sector 1K erase enable/disable" "0,1"
|
|
bitfld.long 0x4 4. "PMODE,PMODE enable/disable" "0,1"
|
|
bitfld.long 0x4 3. "WADCK,Program/Erase address data latch clock enable/disable" "0,1"
|
|
bitfld.long 0x4 2. "PGM,Program mode enable/disable" "0,1"
|
|
bitfld.long 0x4 1. "ERS,Erase mode enable/disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HVEN,High Voltage cycle enable/disable" "0,1"
|
|
line.long 0x8 "AR,Flash Memory Address register"
|
|
hexmask.long.word 0x8 0.--15. 1. "FADDR,Word(32-bit) base address : 64K-word address for 256KB Flash."
|
|
line.long 0xC "DR,Flash Memory Data register"
|
|
hexmask.long 0xC 0.--31. 1. "FDATA,Word size(32-bit) data"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "BUSY,Flash Write Busy Status Register"
|
|
bitfld.long 0x0 0. "WRBUSY,Write Busy status bit" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CRC,Flash CRC-CCITT check value"
|
|
hexmask.long.word 0x0 0.--15. 1. "CRC16,CRC16 check value read register"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "CFG,Flash Memory Config Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x7858 to these bits otherwise the write is ignored."
|
|
bitfld.long 0x0 8.--10. "WAIT,This bits only be written in AMBA mode and MSB 16-bit (bit [31:16]) must be 0x7858" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 7. "CRCINIT,When this bit is set('1') CRC register will be initialized" "0,1"
|
|
bitfld.long 0x0 6. "CRCEN,CRC16 enable" "0,1"
|
|
line.long 0x4 "WPROT,Write Protection Register"
|
|
hexmask.long 0x4 0.--31. 1. "WPROT,Write protection"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "LOCK,Flash LOCK register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RPROT,Read protection"
|
|
tree.end
|
|
tree "LED (LED Driver)"
|
|
base ad:0x40006000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "COMOE,COM Output Enable Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "COMOE2,Port Mode Select2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "COMOE1,Port Mode Select1"
|
|
line.long 0x4 "SEGOE,SEG Output Enable Register"
|
|
bitfld.long 0x4 8.--10. "SEGOE2,Port Mode Select2" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SEGOE1,Port Mode Select1"
|
|
line.long 0x8 "PRESD,LED Prescaler Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PRESD,Pre-scale value of LED clock"
|
|
line.long 0xC "COMER,COM EnableRegister"
|
|
bitfld.long 0xC 15. "COM15,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 14. "COM14,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 13. "COM13,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 12. "COM12,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 11. "COM11,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 10. "COM10,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 9. "COM9,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 8. "COM8,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 7. "COM7,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "COM6,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 5. "COM5,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 4. "COM4,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 3. "COM3,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 2. "COM2,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 1. "COM1,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
bitfld.long 0xC 0. "COM0,Only Selected COM of COM0 and COM26 is active." "0,1"
|
|
line.long 0x10 "COMPWID,COM Pulse Width Control Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "COMPWID,COM Pulse Width Control bits"
|
|
line.long 0x14 "DIMM1,COM Dimming Control Register1"
|
|
hexmask.long.byte 0x14 24.--31. 1. "COMDIMM3,COM3 Dimming Control bits"
|
|
hexmask.long.byte 0x14 16.--23. 1. "COMDIMM2,COM2 Dimming Control bits"
|
|
hexmask.long.byte 0x14 8.--15. 1. "COMDIMM1,COM1 Dimming Control bits"
|
|
hexmask.long.byte 0x14 0.--7. 1. "COMDIMM0,COM0 Dimming Control bits"
|
|
line.long 0x18 "DIMM2,COM Dimming Control Register2"
|
|
hexmask.long.byte 0x18 24.--31. 1. "COMDIMM7,COM7 Dimming Control bits"
|
|
hexmask.long.byte 0x18 16.--23. 1. "COMDIMM6,COM6 Dimming Control bits"
|
|
hexmask.long.byte 0x18 8.--15. 1. "COMDIMM5,COM5 Dimming Control bits"
|
|
hexmask.long.byte 0x18 0.--7. 1. "COMDIMM4,COM4 Dimming Control bits"
|
|
line.long 0x1C "DIMM3,COM Dimming Control Register3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "COMDIMM11,COM11 Dimming Control bits"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "COMDIMM10,COM10 Dimming Control bits"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "COMDIMM9,COM9 Dimming Control bits"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "COMDIMM8,COM8 Dimming Control bits"
|
|
line.long 0x20 "DIMM4,COM Dimming Control Register4"
|
|
hexmask.long.byte 0x20 24.--31. 1. "COMDIMM15,COM15 Dimming Control bits"
|
|
hexmask.long.byte 0x20 16.--23. 1. "COMDIMM14,COM14 Dimming Control bits"
|
|
hexmask.long.byte 0x20 8.--15. 1. "COMDIMM13,COM13 Dimming Control bits"
|
|
hexmask.long.byte 0x20 0.--7. 1. "COMDIMM12,COM12 Dimming Control bits"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "STPD,LED STOP Duration Register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "LEDSTPD,LED STOP Duration Register (since LED Start)"
|
|
line.long 0x4 "SR,LED STATUS Register"
|
|
bitfld.long 0x4 3. "MATCHF,Flag to occur when LEDSTPD reg match with counter" "0,1"
|
|
bitfld.long 0x4 2. "LED_INT,LED Interrupt Flag(in LED_INTE=1)" "0,1"
|
|
bitfld.long 0x4 1. "LED_INTE,LED Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "LED_ENDF,LED Operation End Flag" "0,1"
|
|
line.long 0x8 "CON2,LED Control Register2"
|
|
bitfld.long 0x8 3. "OVERLAP,OVERLAP TIME Select" "0,1"
|
|
bitfld.long 0x8 0.--2. "OVERTS,OVERLAP TIME Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CON1,LED Control Register1"
|
|
bitfld.long 0xC 2.--3. "MD,Mode Select" "0,1,2,3"
|
|
bitfld.long 0xC 1. "LEDEN,LED Enable" "0,1"
|
|
bitfld.long 0xC 0. "LEDST,LED START STOP Operation" "0,1"
|
|
tree.end
|
|
tree "TOUCH (Touch Sensor)"
|
|
base ad:0x40003600
|
|
rgroup.long 0x0++0x5F
|
|
line.long 0x0 "SUM_CH0,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x4 "SUM_CH1,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x8 "SUM_CH2,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0xC "SUM_CH3,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x10 "SUM_CH4,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x14 "SUM_CH5,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x18 "SUM_CH6,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x1C "SUM_CH7,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x20 "SUM_CH8,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x24 "SUM_CH9,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x28 "SUM_CH10,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x28 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x2C "SUM_CH11,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x2C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x30 "SUM_CH12,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x30 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x34 "SUM_CH13,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x34 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x38 "SUM_CH14,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x3C "SUM_CH15,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x3C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x40 "SUM_CH16,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x40 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x44 "SUM_CH17,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x44 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x48 "SUM_CH18,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x48 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x4C "SUM_CH19,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x4C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x50 "SUM_CH20,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x50 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x54 "SUM_CH21,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x54 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x58 "SUM_CH22,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x58 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
line.long 0x5C "SUM_CH23,Touch Sensor Channel 0~23 Sum Register"
|
|
hexmask.long.word 0x5C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
|
|
group.long 0x60++0x5F
|
|
line.long 0x0 "SCO0,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x0 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x4 "SCO1,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x4 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x8 "SCO2,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x8 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0xC "SCO3,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0xC 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x10 "SCO4,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x10 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x14 "SCO5,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x14 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x18 "SCO6,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x18 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x1C "SCO7,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x1C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x20 "SCO8,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x20 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x24 "SCO9,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x24 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x28 "SCO10,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x28 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x2C "SCO11,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x2C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x30 "SCO12,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x30 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x34 "SCO13,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x34 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x38 "SCO14,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x38 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x3C "SCO15,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x3C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x40 "SCO16,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x40 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x44 "SCO17,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x44 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x48 "SCO18,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x48 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x4C "SCO19,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x4C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x50 "SCO20,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x50 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x54 "SCO21,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x54 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x58 "SCO22,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x58 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
line.long 0x5C "SCO23,Touch Sensor Offset Capacitor Selection Register for CH0~23"
|
|
hexmask.long.word 0x5C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "CON,Touch Sensor Control Register"
|
|
bitfld.long 0x0 4. "OSC_EN,Oscillator Enable" "0,1"
|
|
bitfld.long 0x0 3. "BGR_EN,Band Gap Reference Enable" "0,1"
|
|
bitfld.long 0x0 2. "TS_IF,Touch Sensor Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TS_RUN,Touch Sensor Enable" "0,1"
|
|
line.long 0x4 "MODE,Touch Sensor Mode Register"
|
|
bitfld.long 0x4 7. "SREF,External Reference Offset Enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 6. "SC_GAIN,Gain Calibration Capacitor Enable" "0: Gain Calibration Capacitor Disable,1: Gain Calibration Capacitor Enable"
|
|
bitfld.long 0x4 4.--5. "SAP,Touch Sensor Selection" "?,1: Touch Sensor mode Select,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "PORT,Port Configuration During Inactive Status" "0: Input Floating,1: Output Low,?,?"
|
|
line.long 0x8 "SUM_CNT,Touch Sensor Sum Repeat Count Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TS_SUM_CNT,Touch Sensor Sum Repeat Count"
|
|
line.long 0xC "CH_SEL,Touch Sensor Channel Selection Register"
|
|
bitfld.long 0xC 23. "CH23_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 22. "CH22_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 21. "CH21_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 20. "CH20_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 19. "CH19_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 18. "CH18_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 17. "CH17_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 16. "CH16_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 15. "CH15_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 14. "CH14_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 13. "CH13_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 12. "CH12_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 11. "CH11_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 10. "CH10_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 9. "CH9_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 8. "CH8_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 7. "CH7_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 6. "CH6_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 5. "CH5_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 4. "CH4_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 3. "CH3_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
newline
|
|
bitfld.long 0xC 2. "CH2_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 1. "CH1_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
bitfld.long 0xC 0. "CH0_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
|
|
group.long 0x114++0x47
|
|
line.long 0x0 "SLP_CR,Touch Sensor Low Pass Filter Control Register"
|
|
bitfld.long 0x0 4.--6. "SLP_C,Capacitor Trimming for Input Low Pass Filter" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SLP_R,Resistor Trimming for Input Low Pass Filter"
|
|
line.long 0x4 "ADC_CH_SEL,ADC Channel Selection Register"
|
|
bitfld.long 0x4 23. "CH23_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 22. "CH22_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 21. "CH21_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 20. "CH20_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 19. "CH19_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 18. "CH18_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 17. "CH17_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 16. "CH16_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 15. "CH15_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 14. "CH14_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 13. "CH13_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 12. "CH12_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 11. "CH11_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 10. "CH10_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 9. "CH9_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 8. "CH8_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 7. "CH7_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 6. "CH6_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 5. "CH5_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 4. "CH4_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 3. "CH3_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 2. "CH2_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 1. "CH1_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "CH0_SEL,ADC Channel Selection" "0: Disable,1: Enable"
|
|
line.long 0x8 "INTEG_CNT,Touch Sensor Sensing Integration Count Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TS_INTEG_CNT,Touch Sensor Sensing Integration Count"
|
|
line.long 0xC "FREQ_NUM,Touch Sensor Frequency Number Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TS_FREQ_NUM,Touch Sensor Frequency Number"
|
|
line.long 0x10 "FREQ_DEL,Touch Sensor Frequency Delta Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "TS_FREQ_DEL,Touch Sensor Frequency Delta Register"
|
|
line.long 0x14 "CLK_CFG,Touch Sensor Clock Configuration Register"
|
|
bitfld.long 0x14 7. "ACLKSEL,ADC Clock Source Select" "0: Touch Sensor Clock,1: System MCU Clock"
|
|
bitfld.long 0x14 4.--6. "ACLKDIV,ADC Clock Divider" "0: OSCsys / 1,1: OSCsys / 2,?,?,?,?,?,?"
|
|
bitfld.long 0x14 3. "TSCLKOE,Divided Touch Sensor Clock Output Enable" "0: Clock Output Disable,1: Clock Output Enable"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "TSCLKDIV,Touch Sensor Clock Divider" "0: OSCts / 1,1: OSCts / 2,?,?,?,?,?,?"
|
|
line.long 0x18 "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection"
|
|
line.long 0x1C "TRIM_A_OSC,Touch Sensor RING Oscillator Trimming for ADC Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "TRIM_A_OSC,Touch Sensor RING Oscillator Trimming for ADC"
|
|
line.long 0x20 "SCI,Touch Sensor Input Capacitor Selection Register"
|
|
hexmask.long.byte 0x20 4.--7. 1. "IBIAS_TRIM,BGR Current Bias Control"
|
|
bitfld.long 0x20 0.--2. "SCI,Touch Sensor Input Capacitor Selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "SCC,Touch Sensor Conversion Capacitor Selection Register"
|
|
bitfld.long 0x24 0.--2. "SCC,Touch Sensor Conversion Capacitor Selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "SVREF,Touch Sensor VREF Resistor Selection Register"
|
|
hexmask.long.byte 0x28 0.--3. 1. "SVREF,Touch Sensor VREF Resistor Selection"
|
|
line.long 0x2C "TAR,Touch Sensor Integration AMP Reset Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "TAR,Touch Sensor Integration AMP Reset Register"
|
|
line.long 0x30 "TRST,Touch Sensor Reset time of Sensing Register"
|
|
hexmask.long.byte 0x30 0.--7. 1. "TRST,Touch Sensor Reset time of Sensing"
|
|
line.long 0x34 "TDRV,Touch Sensor Sample time of Sensing Register"
|
|
hexmask.long.byte 0x34 0.--7. 1. "TDRV,Touch Sensor Driving time of Sensing"
|
|
line.long 0x38 "TINT,Touch Sensor Integration time of Sensing Register"
|
|
hexmask.long.byte 0x38 0.--7. 1. "TINT,Touch Sensor Integration time of Sensing"
|
|
line.long 0x3C "TD,Touch Sensor Differential AMP Sampling Register"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "TD,Touch Sensor Differential AMP Sampling"
|
|
line.long 0x40 "TWR,Touch Sensor Wait time Register"
|
|
hexmask.long.byte 0x40 0.--7. 1. "TWR,Touch Sensor Wait Time"
|
|
line.long 0x44 "TLED,LED stable time Register"
|
|
hexmask.long.byte 0x44 0.--7. 1. "TLED,LED stable Time"
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x0
|
|
tree "PA"
|
|
base ad:0x40001000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "PB"
|
|
base ad:0x40001100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "PC"
|
|
base ad:0x40001200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "PD"
|
|
base ad:0x40001300
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "PE"
|
|
base ad:0x40001400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "PF"
|
|
base ad:0x40001500
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MOD,Port n Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
|
|
line.long 0x4 "TYP,Port n Output Type Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
|
|
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
|
|
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
|
|
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
|
|
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PUPD,Port n Pull-up/down Resistor Selection Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INDR,Port n Input Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
|
|
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
|
|
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
|
|
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
|
|
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
|
|
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
|
|
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OUTDR,Port n Output Data Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "BSR,Port n Output Bit Set Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
|
|
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
|
|
line.long 0x4 "BCR,Port n Output Bit Clear Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
|
|
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
|
|
group.long 0x24++0x17
|
|
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
|
|
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
|
|
line.long 0x4 "DBCR,Port n Debounce Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
|
|
line.long 0x8 "IER,Port n interrupt enable register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
|
|
line.long 0xC "ISR,Port n interrupt status register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
|
|
line.long 0x10 "ICR,Port n interrupt control register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
|
|
line.long 0x14 "PLSR,PORT F level select register"
|
|
bitfld.long 0x14 2. "PF7LSB,PORTF 7 Level Select bit" "0,1"
|
|
bitfld.long 0x14 1. "PF6LSB,PORTF 6 Level Select bit" "0,1"
|
|
bitfld.long 0x14 0. "PF5LSB,PORTF 5 Level Select bit" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "STR,Port n Strength Configuration Register\n This function is only valid for PB[2:0] and PC[4:2] ports."
|
|
bitfld.long 0x0 8.--9. "P4,P4 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "P3,P3 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "P2,P2 Strength Configuration" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "P1,P1 Strength Configuration" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "P0,P0 Strength Configuration" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
tree "I2C0"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR,I2Cn Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8.--9. "INTERVAL,I2C bus internal delay between address and data transfers (or between two data transfers)" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
|
|
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
|
|
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
|
|
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
|
|
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "EN,Activate I2Cn Block by supplying" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "TXDLYENB,I2Cn_SDHR Register Control bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 5. "IEN,I2Cn Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 4. "IFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "ACKEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 2. "IMASTER,Represent Operation Mode of I2Cn" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "STOPC,STOP Condition Generation When I2Cn is master." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "STARTC,START Condition Generation When I2Cn is master." "0,1"
|
|
endif
|
|
line.long 0x4 "ST,I2Cn Status Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 31. "SLT,This bit shows SCL low timeout status." "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
|
|
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
|
|
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 7. "GCALL,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 6. "TEND,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 5. "STOPD,This bit is set when a STOP condition is detected." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 4. "SSEL,This bit is set when I2C is addressed by other master." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 3. "MLOST,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 2. "BUSY,This bit reflects bus status." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x4 1. "TMODE,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 0. "RXACK,This bit shows the state of ACK signal." "0,1"
|
|
endif
|
|
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
|
|
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x8 1.--7. 1. "SLA,These bits configure the slave address 0 in slave mode."
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 0. "GCALLEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
|
|
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0xC 1.--7. 1. "SLA,These bits configure the slave address 1 in slave mode."
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 0. "GCALLEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
line.long 0x10 "DR,I2Cn Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
|
|
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
|
|
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
|
|
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "SLTCR,I2C n SCL Low Timeout Control Register"
|
|
bitfld.long 0x0 1. "SLTINT,Selection of SCL low timeout Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SLTEN,SCL low timeout enable bit." "0,1"
|
|
line.long 0x4 "SLTPDR,I2C n SCL Low Timeout Control Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PDATA,This register defines the period of SCL low timeout"
|
|
line.long 0x8 "MBCR,I2C n Manual Bus Control Register"
|
|
rbitfld.long 0x8 9. "SCLS,SCL status bit" "0,1"
|
|
rbitfld.long 0x8 8. "SDAS,SDA status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SCLO,SCL output data bit" "0,1"
|
|
bitfld.long 0x8 2. "SDAO,SDA output data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SCLMCE,SCL manual control enable bit" "0,1"
|
|
bitfld.long 0x8 0. "SDAMCE,SDA manual control enable bit" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x40004900
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CR,I2Cn Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8.--9. "INTERVAL,I2C bus internal delay between address and data transfers (or between two data transfers)" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
|
|
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
|
|
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
|
|
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
|
|
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "EN,Activate I2Cn Block by supplying" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "TXDLYENB,I2Cn_SDHR Register Control bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 5. "IEN,I2Cn Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 4. "IFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "ACKEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 2. "IMASTER,Represent Operation Mode of I2Cn" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "STOPC,STOP Condition Generation When I2Cn is master." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "STARTC,START Condition Generation When I2Cn is master." "0,1"
|
|
endif
|
|
line.long 0x4 "ST,I2Cn Status Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 31. "SLT,This bit shows SCL low timeout status." "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
|
|
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
|
|
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 7. "GCALL,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 6. "TEND,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 5. "STOPD,This bit is set when a STOP condition is detected." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 4. "SSEL,This bit is set when I2C is addressed by other master." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 3. "MLOST,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 2. "BUSY,This bit reflects bus status." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x4 1. "TMODE,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 0. "RXACK,This bit shows the state of ACK signal." "0,1"
|
|
endif
|
|
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
|
|
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x8 1.--7. 1. "SLA,These bits configure the slave address 0 in slave mode."
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 0. "GCALLEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
|
|
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0xC 1.--7. 1. "SLA,These bits configure the slave address 1 in slave mode."
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 0. "GCALLEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
|
|
endif
|
|
line.long 0x10 "DR,I2Cn Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
|
|
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
|
|
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
|
|
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "SLTCR,I2C n SCL Low Timeout Control Register"
|
|
bitfld.long 0x0 1. "SLTINT,Selection of SCL low timeout Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SLTEN,SCL low timeout enable bit." "0,1"
|
|
line.long 0x4 "SLTPDR,I2C n SCL Low Timeout Control Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PDATA,This register defines the period of SCL low timeout"
|
|
line.long 0x8 "MBCR,I2C n Manual Bus Control Register"
|
|
rbitfld.long 0x8 9. "SCLS,SCL status bit" "0,1"
|
|
rbitfld.long 0x8 8. "SDAS,SDA status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SCLO,SCL output data bit" "0,1"
|
|
bitfld.long 0x8 2. "SDAO,SDA output data bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SCLMCE,SCL manual control enable bit" "0,1"
|
|
bitfld.long 0x8 0. "SDAMCE,SDA manual control enable bit" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("A31G22*"))
|
|
tree "I2C2"
|
|
base ad:0x40004A00
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "CR,I2C n Control Register"
|
|
bitfld.long 0x0 8.--9. "INTERVAL,I2C bus internal delay between address and data transfers (or between two data transfers)" "0,1,2,3"
|
|
bitfld.long 0x0 7. "EN,Activate I2Cn Block by supplying" "0,1"
|
|
bitfld.long 0x0 6. "TXDLYENB,I2Cn_SDHR Register Control bit" "0,1"
|
|
bitfld.long 0x0 5. "IEN,I2Cn Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "IFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
|
|
bitfld.long 0x0 3. "ACKEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
|
|
rbitfld.long 0x0 2. "IMASTER,Represent Operation Mode of I2Cn" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOPC,STOP Condition Generation When I2Cn is master." "0,1"
|
|
bitfld.long 0x0 0. "STARTC,START Condition Generation When I2Cn is master." "0,1"
|
|
line.long 0x4 "ST,I2C n Status Register"
|
|
bitfld.long 0x4 31. "SLT,This bit shows SCL low timeout status." "0,1"
|
|
bitfld.long 0x4 7. "GCALL,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
|
|
bitfld.long 0x4 6. "TEND,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
|
|
bitfld.long 0x4 5. "STOPD,This bit is set when a STOP condition is detected." "0,1"
|
|
bitfld.long 0x4 4. "SSEL,This bit is set when I2C is addressed by other master." "0,1"
|
|
bitfld.long 0x4 3. "MLOST,This bit represents the result of bus arbitration in master mode." "0,1"
|
|
bitfld.long 0x4 2. "BUSY,This bit reflects bus status." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 1. "TMODE,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
|
|
bitfld.long 0x4 0. "RXACK,This bit shows the state of ACK signal." "0,1"
|
|
line.long 0x8 "SAR1,I2C n Slave Address Register 1"
|
|
hexmask.long.byte 0x8 1.--7. 1. "SLA,These bits configure the slave address 0 in slave mode."
|
|
bitfld.long 0x8 0. "GCALLEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
|
|
line.long 0xC "SAR2,I2C n Slave Address Register 2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "SLA,These bits configure the slave address 1 in slave mode."
|
|
bitfld.long 0xC 0. "GCALLEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
|
|
line.long 0x10 "DR,I2C n Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
|
|
line.long 0x14 "SDHR,I2C n SDA Hold Time Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
|
|
line.long 0x18 "SCLR,I2C n SCL Low Period Register"
|
|
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x1C "SCHR,I2C n SCL High Period Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
|
|
line.long 0x20 "SLTCR,I2C n SCL Low Timeout Control Register"
|
|
bitfld.long 0x20 1. "SLTINT,Selection of SCL low timeout Interrupt" "0,1"
|
|
bitfld.long 0x20 0. "SLTEN,SCL low timeout enable bit." "0,1"
|
|
line.long 0x24 "SLTPDR,I2C n SCL Low Timeout Control Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "PDATA,This register defines the period of SCL low timeout"
|
|
line.long 0x28 "MBCR,I2C n Manual Bus Control Register"
|
|
rbitfld.long 0x28 9. "SCLS,SCL status bit" "0,1"
|
|
rbitfld.long 0x28 8. "SDAS,SDA status bit" "0,1"
|
|
bitfld.long 0x28 3. "SCLO,SCL output data bit" "0,1"
|
|
bitfld.long 0x28 2. "SDAO,SDA output data bit" "0,1"
|
|
bitfld.long 0x28 1. "SCLMCE,SCL manual control enable bit" "0,1"
|
|
bitfld.long 0x28 0. "SDAMCE,SDA manual control enable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "PCU (Port Control Unit)"
|
|
base ad:0x0
|
|
sif (cpuis("A31G21*"))
|
|
tree "PCU"
|
|
base ad:0x40001F00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "KEYR,Port LED KEY Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SEGENKEY,Writing 0xA087 in Operation Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMENKEY,Writing 0x0702 in Operation Key register"
|
|
line.long 0x4 "SEGR,Port LED SEG Register"
|
|
bitfld.long 0x4 9. "SEG9,LED SEG9x Signal bit" "0,1"
|
|
bitfld.long 0x4 8. "SEG8,LED SEG8 Signal bit" "0,1"
|
|
bitfld.long 0x4 7. "SEG7,LED SEG7 Signal bit" "0,1"
|
|
bitfld.long 0x4 6. "SEG6,LED SEG6 Signal bit" "0,1"
|
|
bitfld.long 0x4 5. "SEG5,LED SEG5 Signal bit" "0,1"
|
|
bitfld.long 0x4 4. "SEG4,LED SEG4 Signal bit" "0,1"
|
|
bitfld.long 0x4 3. "SEG3,LED SEG3 Signal bit" "0,1"
|
|
bitfld.long 0x4 2. "SEG2,LED SEG2 Signal bit" "0,1"
|
|
bitfld.long 0x4 1. "SEG1,LED SEG1 Signal bit" "0,1"
|
|
bitfld.long 0x4 0. "SEG0,LED SEGx Signal bit" "0,1"
|
|
line.long 0x8 "COMR,Port LED COM Register"
|
|
bitfld.long 0x8 27. "LED_ENDF,Led end signal" "0,1"
|
|
bitfld.long 0x8 15. "COM15,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 14. "COM14,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 13. "COM13,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 12. "COM12,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 11. "COM11,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 10. "COM10,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 9. "COM9,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 8. "COM8,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 7. "COM7,LED COMx Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "COM6,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 5. "COM5,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 4. "COM4,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 3. "COM3,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 2. "COM2,LED COMx Signal" "0,1"
|
|
bitfld.long 0x8 1. "COM1,LED COM1 Signal" "0,1"
|
|
bitfld.long 0x8 0. "COM0,LED COMx Signal" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "PORTEN,Port Access Enable 0x15->0x51"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORTEN,Writing the sequence of 0x15 and 0x51 in this register enables"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "PCU1"
|
|
base ad:0x40001544
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SPI2PMR,Port SPI2n Pin Re-Map Register"
|
|
bitfld.long 0x0 1. "SPI21_PRM,Enable Pin Re-map of SPI21 channel" "0,1"
|
|
bitfld.long 0x0 0. "SPI20_PRM,Enable Pin Re-map of SPI20 channel" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "PCU2"
|
|
base ad:0x40001F00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ISEGPEN,Port LED ISEG Port Enable Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "ISEGENKEY,Write 0x0702 to the operation key register for operating each of the ISEG"
|
|
line.long 0x4 "ISEGR,Port LED ISEG Register"
|
|
bitfld.long 0x4 9. "ISEG9,LED ISEG9 singal control of PD2 port" "0,1"
|
|
bitfld.long 0x4 8. "ISEG8,LED ISEG8 singal control of PD3 port" "0,1"
|
|
bitfld.long 0x4 7. "ISEG7,LED ISEG7 singal control of PD4 port" "0,1"
|
|
bitfld.long 0x4 6. "ISEG6,LED ISEG6 singal control of PD5 port" "0,1"
|
|
bitfld.long 0x4 5. "ISEG5,LED ISEG5 singal control of PE7 port" "0,1"
|
|
bitfld.long 0x4 4. "ISEG4,LED ISEG4 singal control of PE6 port" "0,1"
|
|
bitfld.long 0x4 3. "ISEG3,LED ISEG3 singal control of PE5 port" "0,1"
|
|
bitfld.long 0x4 2. "ISEG2,LED ISEG2 singal control of PE4 port" "0,1"
|
|
bitfld.long 0x4 1. "ISEG1,LED ISEG1 singal control of PE3 port" "0,1"
|
|
bitfld.long 0x4 0. "ISEG0,LED ISEG0 singal control of PE2 port" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ISEGIR,Port LED ISEG Inversion Register"
|
|
bitfld.long 0x0 9. "ISEG9_INV,LED ISEG9 inverted singal control of PD2 port" "0,1"
|
|
bitfld.long 0x0 8. "ISEG8_INV,LED ISEG8 inverted singal control of PD3 port" "0,1"
|
|
bitfld.long 0x0 7. "ISEG7_INV,LED ISEG7 inverted singal control of PD4 port" "0,1"
|
|
bitfld.long 0x0 6. "ISEG6_INV,LED ISEG6 inverted singal control of PD5 port" "0,1"
|
|
bitfld.long 0x0 5. "ISEG5_INV,LED ISEG5 inverted singal control of PE7 port" "0,1"
|
|
bitfld.long 0x0 4. "ISEG4_INV,LED ISEG4 inverted singal control of PE6 port" "0,1"
|
|
bitfld.long 0x0 3. "ISEG3_INV,LED ISEG3 inverted singal control of PE5 port" "0,1"
|
|
bitfld.long 0x0 2. "ISEG2_INV,LED ISEG2 inverted singal control of PE4 port" "0,1"
|
|
bitfld.long 0x0 1. "ISEG1_INV,LED ISEG1 inverted singal control of PE3 port" "0,1"
|
|
bitfld.long 0x0 0. "ISEG0_INV,LED ISEG0 inverted singal control of PE2 port" "0,1"
|
|
wgroup.long 0xF0++0x3
|
|
line.long 0x0 "PORTEN,Port Access Enable Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORTEN,Writing the sequence of 0x15 and 0x51 in this register enables"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SCU (System Control Unit)"
|
|
base ad:0x0
|
|
tree "SCU (System Control Unit)"
|
|
base ad:0x40000000
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "SMR,System Mode Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 11. "LSEAON,LSE Always on select bit in power down mode" "0: LSE is automatically off entering power down mode,1: LSE isn't automatically off entering power down.."
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 10. "ROSCAON,ROSC Always on select bit in power down mode" "0: ROSC is automatically off entering power down mode,1: ROSC isn't automatically off entering power down.."
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 10. "LSIAON,LSI Always on select bit in power down mode" "0: LSI is automatically off entering power down mode,1: LSI isn't automatically off entering power down.."
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 9. "BGRAON,BGR Always on select bit in power down mode" "0: BGR is automatically off entering power down mode,1: BGR isn't automatically off entering power down.."
|
|
newline
|
|
bitfld.long 0x0 8. "VDCAON,VDC Always on select bit in power down mode" "0,1"
|
|
bitfld.long 0x0 4.--5. "PREVMODE,Previous operating mode before current reset event" "0,1,2,3"
|
|
line.long 0x4 "SCR,System Control Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes write 0x9EB3 to these bits otherwise the write is ignored."
|
|
bitfld.long 0x4 0. "SWRST,Internal soft reset activation bit (check RSER[4] for reset)" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WUER,Wake up source enable register"
|
|
bitfld.long 0x0 13. "GPIOFWUE,Enable wakeup source of GPIOF port pin change event" "0,1"
|
|
bitfld.long 0x0 12. "GPIOEWUE,Enable wakeup source of GPIOE port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIODWUE,Enable wakeup source of GPIOD port pin change event" "0,1"
|
|
bitfld.long 0x0 10. "GPIOCWUE,Enable wakeup source of GPIOC port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIOBWUE,Enable wakeup source of GPIOB port pin change event" "0,1"
|
|
bitfld.long 0x0 8. "GPIOAWUE,Enable wakeup source of GPIOA port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WTWUE,Enable wakeup source of watch timer event" "0,1"
|
|
bitfld.long 0x0 1. "WDTWUE,Enable wakeup source of watchdog timer event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVDWUE,Enable wakeup source of LVD event" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "WUSR,Wake up source status register"
|
|
bitfld.long 0x0 13. "GPIOFWU,Status of wakeup source of GPIOF port pin change event" "0,1"
|
|
bitfld.long 0x0 12. "GPIOEWU,Status of wakeup source of GPIOE port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIODWU,Status of wakeup source of GPIOD port pin change event" "0,1"
|
|
bitfld.long 0x0 10. "GPIOCWU,Status of wakeup source of GPIOC port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPIOBWU,Status of wakeup source of GPIOB port pin change event" "0,1"
|
|
bitfld.long 0x0 8. "GPIOAWU,Status of wakeup source of GPIOA port pin change event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WTWU,Status of wakeup source of watch timer event" "0,1"
|
|
bitfld.long 0x0 1. "WDTWU,Status of wakeup source of watchdog timer event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVDWU,Status of wakeup source of LVD event" "0,1"
|
|
group.long 0x18++0x23
|
|
line.long 0x0 "RSER,Reset source enable register"
|
|
bitfld.long 0x0 6. "PINRST,External pin reset enable bit" "0,1"
|
|
bitfld.long 0x0 5. "CPURST,CPU request reset enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWRST,Software reset enable bit" "0,1"
|
|
bitfld.long 0x0 3. "WDTRST,Watchdog Timer reset enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MCKFRST,MCLK Clock fail reset enable bit" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "HSEFRST,HSE Clock fail reset enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 1. "MOFRST,MOSC Clock fail reset enable bit" "0,1"
|
|
endif
|
|
bitfld.long 0x0 0. "LVDRST,LVD reset enable bit" "0,1"
|
|
line.long 0x4 "RSSR,Reset source status register"
|
|
bitfld.long 0x4 7. "PORST,Power on reset status bit" "0,1"
|
|
bitfld.long 0x4 6. "PINRST,External pin reset status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CPURST,CPU request reset status bit" "0,1"
|
|
bitfld.long 0x4 4. "SWRST,Software reset status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "WDTRST,Watchdog Timer reset status bit" "0,1"
|
|
bitfld.long 0x4 2. "MCKFRST,MCLK Clock fail reset status bit" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 1. "HSEFRST,HSE Clock fail reset status bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x4 1. "MOFRST,MOSC Clock fail reset status bit" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 0. "LVDRST,LVD reset status bit" "0,1"
|
|
line.long 0x8 "PRER1,Peripheral reset enable register 1"
|
|
bitfld.long 0x8 31. "WT,WT reset mask" "0,1"
|
|
bitfld.long 0x8 26. "TIMER21,TIMER21 reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TIMER20,TIMER20 reset mask" "0,1"
|
|
bitfld.long 0x8 24. "TIMER30,TIMER30 reset mask" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 22. "TIMER16,TIMER16 reset mask" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 21. "TIMER15,TIMER15 reset mask" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 20. "TIMER14,TIMER14 reset mask" "0,1"
|
|
endif
|
|
bitfld.long 0x8 19. "TIMER13,TIMER13 reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "TIMER12,TIMER12 reset mask" "0,1"
|
|
bitfld.long 0x8 17. "TIMER11,TIMER11 reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "TIMER10,TIMER10 reset mask" "0,1"
|
|
bitfld.long 0x8 13. "GPIOF,GPIOF reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "GPIOE,GPIOE reset mask" "0,1"
|
|
bitfld.long 0x8 11. "GPIOD,GPIOD reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "GPIOC,GPIOC reset mask" "0,1"
|
|
bitfld.long 0x8 9. "GPIOB,GPIOB reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "GPIOA,GPIOA reset mask" "0,1"
|
|
bitfld.long 0x8 4. "DMA,DMA reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PCU,PCU reset mask" "0,1"
|
|
bitfld.long 0x8 2. "WDT,WDT reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FMC,FMC reset mask" "0,1"
|
|
bitfld.long 0x8 0. "SCU,SCU reset mask" "0,1"
|
|
line.long 0xC "PRER2,Peripheral reset enable register 2"
|
|
bitfld.long 0xC 31. "CRC,CRC reset mask" "0,1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0xC 29. "LED,LED reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TOUCH,TOUCH reset mask" "0,1"
|
|
bitfld.long 0xC 11. "SPI21,SPI21 reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "SPI20,SPI20 reset mask" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 28. "LCD,LCD reset enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 27. "TS,Temperature Sensor reset mask" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 23. "CMP,CMP reset mask" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 22. "DAC,DAC reset mask" "0,1"
|
|
endif
|
|
bitfld.long 0xC 20. "ADC,ADC reset mask" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 15. "SPI21,SPI21 reset mask" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 14. "SPI20,SPI20 reset mask" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 13. "UART1,UART1 reset mask" "0,1"
|
|
bitfld.long 0xC 12. "UART0,UART0 reset mask" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 11. "USART13,USART13 reset mask" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 10. "USART12,USART12 reset mask" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 9. "USART11,USART11 reset mask" "0,1"
|
|
bitfld.long 0xC 8. "USART10,USART10 reset mask" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 6. "I2C2,I2C2 reset mask" "0,1"
|
|
endif
|
|
bitfld.long 0xC 5. "I2C1,I2C1 reset mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "I2C0,I2C0 reset mask" "0,1"
|
|
line.long 0x10 "PER1,Peripheral enable register 1"
|
|
bitfld.long 0x10 31. "WT,WT function enable" "0,1"
|
|
bitfld.long 0x10 26. "TIMER21,TIMER21 function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TIMER20,TIMER20 function enable" "0,1"
|
|
bitfld.long 0x10 24. "TIMER30,TIMER30 function enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 22. "TIMER16,TIMER16 function enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 21. "TIMER15,TIMER15 function enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 20. "TIMER14,TIMER14 function enable" "0,1"
|
|
endif
|
|
bitfld.long 0x10 19. "TIMER13,TIMER13 function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "TIMER12,TIMER12 function enable" "0,1"
|
|
bitfld.long 0x10 17. "TIMER11,TIMER11 function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "TIMER10,TIMER10 function enable" "0,1"
|
|
bitfld.long 0x10 13. "GPIOF,GPIOF function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "GPIOE,GPIOE function enable" "0,1"
|
|
bitfld.long 0x10 11. "GPIOD,GPIOD function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "GPIOC,GPIOC function enable" "0,1"
|
|
bitfld.long 0x10 9. "GPIOB,GPIOB function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "GPIOA,GPIOA function enable" "0,1"
|
|
bitfld.long 0x10 4. "DMA,DMA function enable" "0,1"
|
|
line.long 0x14 "PER2,Peripheral enable register 2"
|
|
bitfld.long 0x14 31. "CRC,CRC function enable" "0,1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x14 29. "LED,LED function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TOUCH,TOUCH function enable" "0,1"
|
|
bitfld.long 0x14 11. "SPI21,SPI21 function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "SPI20,SPI20 function enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 28. "LCD,LCD function enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 27. "TS,Temperature Sensor function enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 23. "CMP,CMP function enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 22. "DAC,DAC function enable" "0,1"
|
|
endif
|
|
bitfld.long 0x14 20. "ADC,ADC function enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 15. "SPI21,SPI21 function enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 14. "SPI20,SPI20 function enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 13. "UART1,UART1 function enable" "0,1"
|
|
bitfld.long 0x14 12. "UART0,UART0 function enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 11. "USART13,USART13 function enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 10. "USART12,USART12 function enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 9. "USART11,USART11 function enable" "0,1"
|
|
bitfld.long 0x14 8. "USART10,USART10 function enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x14 6. "I2C2,I2C2 function enable" "0,1"
|
|
endif
|
|
bitfld.long 0x14 5. "I2C1,I2C1 function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "I2C0,I2C0 function enable" "0,1"
|
|
line.long 0x18 "PCER1,Peripheral clock enable register 1"
|
|
bitfld.long 0x18 31. "WT,WT clock enable" "0,1"
|
|
bitfld.long 0x18 26. "TIMER21,TIMER21 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "TIMER20,TIMER20 clock enable" "0,1"
|
|
bitfld.long 0x18 24. "TIMER30,TIMER30 clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x18 22. "TIMER16,TIMER16 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x18 21. "TIMER15,TIMER15 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 20. "TIMER14,TIMER14 clock enable" "0,1"
|
|
bitfld.long 0x18 19. "TIMER13,TIMER13 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "TIMER12,TIMER12 clock enable" "0,1"
|
|
bitfld.long 0x18 17. "TIMER11,TIMER11 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "TIMER10,TIMER10 clock enable" "0,1"
|
|
bitfld.long 0x18 13. "GPIOF,GPIOF clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "GPIOE,GPIOE clock enable" "0,1"
|
|
bitfld.long 0x18 11. "GPIOD,GPIOD clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "GPIOC,GPIOC clock enable" "0,1"
|
|
bitfld.long 0x18 9. "GPIOB,GPIOB clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "GPIOA,GPIOA clock enable" "0,1"
|
|
bitfld.long 0x18 4. "DMA,DMA clock enable" "0,1"
|
|
line.long 0x1C "PCER2,Peripheral clock enable register 2"
|
|
bitfld.long 0x1C 31. "CRC,CRC clock enable" "0,1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x1C 29. "LED,LED clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "TOUCH,TOUCH clock enable" "0,1"
|
|
bitfld.long 0x1C 11. "SPI21,SPI21 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 10. "SPI20,SPI20 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 28. "LCD,LCD driver clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 27. "TS,Temperature sensor clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 23. "CMP,CMP clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 22. "DAC,DAC clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 20. "ADC,ADC clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 15. "SPI21,SPI21 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 14. "SPI20,SPI20 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x1C 13. "UART1,UART1 clock enable" "0,1"
|
|
bitfld.long 0x1C 12. "UART0,UART0 clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 11. "USART13,USART13 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 10. "USART12,USART12 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x1C 9. "USART11,USART11 clock enable" "0,1"
|
|
bitfld.long 0x1C 8. "USART10,USART10 clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x1C 6. "I2C2,I2C2 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 5. "I2C1,I2C1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "I2C0,I2C0 clock enable" "0,1"
|
|
line.long 0x20 "PPCLKSR,Peripheral clock selection register"
|
|
bitfld.long 0x20 22. "T1xCLK,Timer 1x Clock Selection bit" "0,1"
|
|
bitfld.long 0x20 20. "T20CLK,Timer 20 Clock Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17. "T30CLK,Timer 30 Clock Selection bit" "0,1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x20 10. "LEDCLK,LED Clock Selection bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x20 6.--7. "LCDCLK,LCD Clock Selection bit" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x20 3.--4. "WTCLK,Watch Timer Clock Selection bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 0. "WDTCLK,Watch-dog Timer Clock Selection bit" "0,1"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "CSCR,Clock Source Control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,On writes write 0xA507 to these bits otherwise the write is ignored."
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "LSECON,Low speed external oscillator control"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "SOSCCON,External crystal sub oscillator control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MOSCCON,External crystal main oscillator control"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 8.--11. 1. "LSICON,Low speed internal oscillator control"
|
|
hexmask.long.byte 0x0 4.--7. 1. "HSICON,High speed internal oscillator control"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "HSECON,Hight speed external oscillator control"
|
|
endif
|
|
line.long 0x4 "SCCR,System Clock Control register"
|
|
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes write 0x570A to these bits otherwise the write is ignored."
|
|
bitfld.long 0x4 2. "FINSEL,PLL input source FIN select register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "MCLKSEL,System clock select register" "0,1,2,3"
|
|
line.long 0x8 "CMR,Clock Monitoring register"
|
|
bitfld.long 0x8 15. "MCLKREC,MCLK fail auto recovery" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 11. "LSEMNT,Low speed External oscillator monitoring enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x8 11. "SOSCMNT,External sub oscillator monitoring enable" "0,1"
|
|
bitfld.long 0x8 10. "SOSCIE,External sub oscillator fail interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SOSCFAIL,External sub oscillator fail interrupt" "0,1"
|
|
bitfld.long 0x8 8. "SOSCSTS,External sub oscillator status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "MOSCMNT,External main oscillator monitoring enable" "0,1"
|
|
bitfld.long 0x8 2. "MOSCIE,External main oscillator fail interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "MOSCFAIL,External main oscillator fail interrupt" "0,1"
|
|
bitfld.long 0x8 0. "MOSCSTS,External main oscillator status" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 10. "LSEIE,Low speed external oscillator fail interrupt enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 9. "LSEFAIL,Low speed external oscillator fail interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 8. "LSESTS,Low speed external oscillator status" "0,1"
|
|
endif
|
|
bitfld.long 0x8 7. "MCLKMNT,MCLK monitoring enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MCLKIE,MCLK fail interrupt enable" "0,1"
|
|
bitfld.long 0x8 5. "MCLKFAIL,MCLK fail interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MCLKSTS,MCLK clock status" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 3. "HSEMNT,High speed external oscillator monitoring enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 2. "HSEIE,High speed external oscillator fail interrupt enable" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 1. "HSEFAIL,High speed external oscillator fail interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x8 0. "HSESTS,High speed external oscillator status" "0,1"
|
|
endif
|
|
line.long 0xC "NMIR,NMI control register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ACCESSCODE,This field enables writing access to this register."
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0xC 13. "SWAPERRSTS,Swap Error Interrupt condition status bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0xC 12. "CMPINTSTS,Comparator Interrupt condition status bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0xC 11. "T30INTSTS,TIMER30 Interrupt condition status bit" "0,1"
|
|
newline
|
|
endif
|
|
rbitfld.long 0xC 10. "WDTINTSTS,WDT Interrupt condition status bit" "0,1"
|
|
rbitfld.long 0xC 9. "MCLKFAILSTS,MCLK Fail condition status bit" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 8. "LVDSTS,LVD condition status bit" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 5. "SWAPERRIEN,Swap Error interrupt condition enable for NMI interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 4. "CMPINTEN,Comparator interrupt condition enable for NMI interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0xC 3. "T30IEN,TIMER30 interrupt condition enable for NMI interrupt" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 2. "WDTINTEN,WDT Interrupt condition enable for NMI interrupt" "0,1"
|
|
bitfld.long 0xC 1. "MCLKFAILEN,MCLK Fail condition enable for NMI interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "LVDEN,LVD Fail condition enable for NMI interrupt" "0,1"
|
|
line.long 0x10 "COR,Clock Output Control register"
|
|
bitfld.long 0x10 4. "CLKOEN,Clock output enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "CLKODIV,Clock output divider value"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "PLLCON,PLL Control register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK status" "0,1"
|
|
bitfld.long 0x0 23. "PLLRSTB,PLL reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "PLLEN,PLL enable" "0,1"
|
|
bitfld.long 0x0 21. "BYPASSB,FIN bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PLLMODE,PLL VCO mode" "0,1"
|
|
bitfld.long 0x0 16.--18. "PREDIV,FIN predivider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "POSTDIV1,Feedback control 1 (N1)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "POSTDIV2,Feedback control 1 (N2)"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "OUTDIV,output divider control (P)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "VDCCON,VDC Control register"
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0x4 20.--23. 1. "VDC15_WTIDKY,VDC15 Write Identification Key"
|
|
bitfld.long 0x4 19. "VDC15_PDBGR,VDC15 1.2V BGR / 1.0V Buffer Power Down Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "VDC15_STOP,VDC15 STOP Mode Control Signal" "0,1"
|
|
bitfld.long 0x4 16. "VDC15_IDLE,VDC15 STOP1 Mode Control Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "VDC15_LOCK,VDC15 VDCLOCK Control Signal for *BGR Stabilization" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "VDCWDLY,VDC warm-up delay count value."
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x4 20.--23. 1. "VDC_WTIDKY,VDC Write Identification Key"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 19. "VDC_PDBGR,BGR Buffer Deep-sleep Signal Selection" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 17. "VDC_STOP,VDC STOP Mode Control Signal" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 16. "VDC_IDLE,VDC STOP1 Mode Control Signal" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 15. "VDC_LOCK,VDC VDCLOCK Control Signal for *BGR Stabilization" "0,1"
|
|
endif
|
|
bitfld.long 0x4 8. "VDCWDLY_WEN,VDCWDLY value write enable. VDCWDLY value can be written with writing '1' to VDCWDLY_WEN bit simultaneously." "0,1"
|
|
newline
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "VDCWDLY,VDC warm-up delay count value."
|
|
endif
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LSICON,LSI Control Register"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 1. "EN_LDO,Internal LDO On/Off" "0,1"
|
|
endif
|
|
bitfld.long 0x0 0. "SKIP_LS,Internal Level Shifter control signal" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "EOSCR,External Oscillator control register"
|
|
bitfld.long 0x0 15. "ESEN,Write enable for External SOSC" "0,1"
|
|
bitfld.long 0x0 12.--13. "ESISEL,Internal Level Shifter control signal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "ESNCBYPS,Noise Cancel Bypass enable for External SOSC" "0,1"
|
|
bitfld.long 0x0 7. "EMEN,Write enable for External MOSC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ISE,Select current for External MOSC" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "NCOPT,Noise Cancel delay Option for External MOSC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "NCSKIP,Noise Cancel Bypass enable for External SOSC" "0,1"
|
|
line.long 0x4 "EMODR,External mode pin read register"
|
|
sif (cpuis("A31G21*"))
|
|
rbitfld.long 0x4 2. "SCANMD,SCAN Mode level" "0,1"
|
|
rbitfld.long 0x4 1. "TEST,TEST Mode level" "0,1"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x4 0. "BOOT,BOOT pin level" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "RSTDBCR,Pin Reset Debounce Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,On writes write 0x0514 to these bits otherwise the write is ignored."
|
|
hexmask.long.byte 0x0 8.--13. 1. "CLKCNT,Noise cancel delay option for pin reset N : N clock checking for debounce by LSI(500kHz)"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Pin reset debounce enable bit" "0,1"
|
|
endif
|
|
group.long 0x90++0x17
|
|
line.long 0x0 "MCCR1,Miscellaneous Clock Control Register 1"
|
|
bitfld.long 0x0 24.--26. "TEXT1CSEL,TIMER1n EXT Clock source select bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TEXT1DIV,TIMER1n EXT Clock N divider"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "STCSEL,systick clock source sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STDIV,SYSTICK Clock N divider"
|
|
line.long 0x4 "MCCR2,Miscellaneous Clock Control Register 2"
|
|
bitfld.long 0x4 24.--26. "TEXT3CSEL,TIMER 30 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "TEXT3DIV,TIMER 30 EXT Clock N divider"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "TEXT2CSEL,TEXT2CSEL" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEXT2DIV,TIMER 20 EXT Clock N divider"
|
|
line.long 0x8 "MCCR3,Miscellaneous Clock Control Register 3"
|
|
bitfld.long 0x8 24.--26. "WTEXTCSEL,WTEXTCSEL" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 16.--23. 1. "WTEXTCDIV,WT External Clock N divider"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "WDTCSEL,WDT clock sel" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDTDIV,WDT Clock N divider"
|
|
line.long 0xC "MCCR4,Miscellaneous Clock Control Register 4"
|
|
bitfld.long 0xC 24.--26. "PD1CSEL,Debounce Clock for PORT source select bit (PD PE PF)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PD1DIV,PORT Debounce Clock N divider (PD PE PF)"
|
|
newline
|
|
bitfld.long 0xC 8.--10. "PD0CSEL,Debounce Clock for PORT source select bit (PA PB PC)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PD0DIV,PORT Debounce Clock N divider (PA PB PC)"
|
|
line.long 0x10 "MCCR5,Miscellaneous Clock Control Register 5"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 24.--26. "LCDSEL,LCD Clock source selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x10 16.--23. 1. "LCDDIV,LCD Clock N divider"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 14.--15. "TSRCSEL,Temperature Sensor reference clock selection bit" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 12.--13. "TSSCSEL,Temperature Sensor sensing clock selection bit" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x10 11. "TSSLSITSEN,Enable temperature sensing oscillator (LSI_TS)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x10 8.--10. "LEDCSEL,LED Clock source select bit" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LEDDIV,LED Clock N divider"
|
|
endif
|
|
line.long 0x14 "MCCR6,Miscellaneous Clock Control Register 6"
|
|
bitfld.long 0x14 8. "T3CAPSEL,Timer30 Capture Enable bit" "0,1"
|
|
bitfld.long 0x14 4. "TSEN,Temperature Sensor enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "TSPRES,Temperature Sensor period" "0,1,2,3"
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "MCCR7,Miscellaneous Clock Control Register 7"
|
|
bitfld.long 0x0 24.--26. "ADCCSEL,ADC Clock source select bit" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADCCDIV,ADC Clock N divider"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "HSITRIM,Internal OSC Trim Register"
|
|
bitfld.long 0x0 31. "BISCON,Built in self calibration function enable" "0,1"
|
|
bitfld.long 0x0 30. "REFSEL,Reference clock select for self-calibrarion" "0,1"
|
|
line.long 0x4 "BISCCON,Build in self calibration contrl register"
|
|
hexmask.long.word 0x4 16.--31. 1. "HSIOSC_COMP,Built in self calibration function enable"
|
|
hexmask.long.word 0x4 0.--15. 1. "REF_COMP,Reference clock Compare value"
|
|
endif
|
|
tree.end
|
|
tree "SCUCC (Chip Configuration)"
|
|
base ad:0x4000F000
|
|
rgroup.long 0x0++0xB
|
|
line.long 0x0 "VENDORID,Vendor Identification Register"
|
|
hexmask.long 0x0 0.--31. 1. "VENDID,Vendor Identification bits"
|
|
line.long 0x4 "CHIPID,Chip Identification Register"
|
|
hexmask.long 0x4 0.--31. 1. "CHIPID,Chip Identification bits. 0x4D31F000: 32k bytes flash memory for program 0x4D31F001: 16k bytes flash memory for program"
|
|
line.long 0x8 "REVNR,Revision Number Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "REVNO,Chip Revision Number. These bits are fixed by manufacturer."
|
|
tree.end
|
|
tree "SCULV (LVI and LVR)"
|
|
base ad:0x40005100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "LVICR,Low Voltage Indicator Control Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "LVIFLAG,LVI Interrupt Flag bit. This bit is clear by writing '1' to this bit." "0,1"
|
|
endif
|
|
bitfld.long 0x0 7. "LVIEN,LVI Enable bit" "0,1"
|
|
bitfld.long 0x0 5. "LVINTEN,LVI Interrupt Enable bit" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 4. "LVIST,LVI Interrupt Status Flag bit. This bit is cleared to '0' when VDDEXT level is over than LVI level." "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 4. "LVIFLAG,LVI Interrupt Flag bit" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--3. 1. "LVIVS,LVI Voltage Selection bits"
|
|
line.long 0x4 "LVRCR,Low Voltage Reset Control Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LVREN,LVR Enable bits"
|
|
line.long 0x8 "LVRCNFIG,Configuration for Low Voltage Reset"
|
|
hexmask.long.word 0x8 16.--31. 1. "WTIDKY,Write Identification Key"
|
|
hexmask.long.byte 0x8 8.--15. 1. "LVRENM,LVR Reset Operation Control Master Configuration"
|
|
sif (cpuis("A31G22*"))
|
|
hexmask.long.byte 0x8 0.--3. 1. "LVRVS,LVR Voltage Selection bits"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "LVRVS,LVR Voltage Selection bits"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI20"
|
|
base ad:0x40004C00
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI2 n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Received Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 18. "TXDIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "RXDIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
|
|
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
|
|
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
|
|
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
|
|
line.long 0xC "EN,SPI n Enable Register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
|
|
line.long 0x10 "LR,SPI n Delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
|
|
tree.end
|
|
tree "SPI21"
|
|
base ad:0x40004D00
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "TDR,SPI2 n Transmit Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "TDR,Transmit Data Bit"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RDR,SPI n Received Data Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "RDR,Received Data Bit"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR,SPI Control Register"
|
|
bitfld.long 0x0 20. "TXBC,Tx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 19. "RXBC,Rx Buffer Clear Bit" "0,1"
|
|
bitfld.long 0x0 18. "TXDIE,DMA Tx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "RXDIE,DMA Rx Complete Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "SSCIE,SS Edge Changed Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "TXIE,Transmit Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "RXIE,Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "SSMOD,SS Auto/Manual Output Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 12. "SSOUT,SS Output Signal Control Bit" "0,1"
|
|
bitfld.long 0x0 11. "LBE,Loop-back Mode Selection Bit in Master Mode" "0,1"
|
|
bitfld.long 0x0 10. "SSMASK,SS Signal Masking in Slave Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSMO,SS Output Signal Selection Bit" "0,1"
|
|
bitfld.long 0x0 8. "SSPOL,SS Signal Polarity Selection Bit" "0,1"
|
|
bitfld.long 0x0 5. "MS,Master/Slave Selection Bit" "0,1"
|
|
bitfld.long 0x0 4. "MSBF,MSB/LSB Transmit Advance Selection Bit" "0,1"
|
|
bitfld.long 0x0 3. "CPHA,SPI Clock Phase Bit" "0,1"
|
|
bitfld.long 0x0 2. "CPOL,SPI Clock Polarity Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "BITSZ,Transmit/Receive Bit Size Selection Bit" "0: Size is 8 bit,1: Size is 9 bit,2: Size is 16 bit,3: Size is 17 bit"
|
|
line.long 0x4 "SR,SPI n Status Register"
|
|
bitfld.long 0x4 9. "TXDMAF,DMA Transmit Operation Complete Flag" "0,1"
|
|
bitfld.long 0x4 8. "RXDMAF,DMA Received Operation Complete Flag" "0,1"
|
|
rbitfld.long 0x4 7. "SBUSY,Transmit/Received Operating Flag" "0,1"
|
|
bitfld.long 0x4 6. "SSDET,SS Signal Rising or Falling Edge Detected Flag" "0,1"
|
|
bitfld.long 0x4 5. "SSON,SS Signal Status Flag" "0,1"
|
|
bitfld.long 0x4 4. "OVRF,Received Overrun Error Flag" "0,1"
|
|
bitfld.long 0x4 3. "UDRF,Transmit Underrun Error Flag" "0,1"
|
|
rbitfld.long 0x4 2. "TXIDLE,Transmit Operating Flag" "0,1"
|
|
rbitfld.long 0x4 1. "TRDY,Transmit Buffer Empty Flag" "0,1"
|
|
rbitfld.long 0x4 0. "RRDY,Received Buffer Empty Flag" "0,1"
|
|
line.long 0x8 "BR,SPI n Baud Rate Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BR,Baud Rate Setting Bit"
|
|
line.long 0xC "EN,SPI n Enable Register"
|
|
bitfld.long 0xC 0. "ENABLE,SPI Enable Bit" "0,1"
|
|
line.long 0x10 "LR,SPI n Delay Length Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "SPL,SPI STOP Length Value Bit"
|
|
hexmask.long.byte 0x10 8.--15. 1. "BTL,SPI Burst Length Value Bit"
|
|
hexmask.long.byte 0x10 0.--7. 1. "STL,SPI Start Length Value Bit"
|
|
tree.end
|
|
tree.end
|
|
tree "TIMER (Timer/Counter)"
|
|
base ad:0x0
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER10"
|
|
base ad:0x40002100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER11"
|
|
base ad:0x40002200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER12"
|
|
base ad:0x40002300
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER13"
|
|
base ad:0x40002700
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER20"
|
|
base ad:0x40002500
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER21"
|
|
base ad:0x40002600
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
tree "TIMER30"
|
|
base ad:0x40002400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR,Timer/Counter 30 Control Register"
|
|
bitfld.long 0x0 15. "T30EN,Timer 30 Operation Enable bit" "0: Disable timer 30 operation,1: Enable timer 30 operation (Counter clear and.."
|
|
bitfld.long 0x0 14. "T30CLK,Timer 30 Clock Selection bit (Note: This bit should be changed during T30EN bit is '0b'.)" "0: Select an internal prescaler clock,1: Select an external clock"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "T30MS,Timer 30 Operation Mode Selection bits (Note: These bits should be changed during T30EN bit is '0b'.)" "0: Interval mode (All match interrupts can occur),1: Capture mode (The Period-match interrupt can..,2: Back-to-back mode (All interrupts can occur),?"
|
|
bitfld.long 0x0 11. "T30ECE,Timer 30 External Clock Edge Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "FORCA,Timer 30 Output Mode Selection bit. This bit should be changed when the T30EN is '0b'. Note: If this bit is changed on operation it shall apply from the next period." "0,1"
|
|
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0,1"
|
|
bitfld.long 0x0 6.--7. "T30CPOL,Timer 30 Capture Polarity Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection (Note: A period match counter is cleared as 0x00 when the T3nCLR bit is set or the PMOC[2:0] bits are changed.)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0. "T30CLR,Timer 30 Counter and Prescaler Clear bit" "0: No effect,1: Clear timer 30 counter and prescaler.."
|
|
line.long 0x4 "PDR,Timer/Counter 30 Period Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PDATA,Timer/Counter 30 Period Data bits. The range is 0x0002 to 0xFFFF."
|
|
line.long 0x8 "ADR,Timer/Counter 30 A Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ADATA,Timer/Counter 30 A Data bits. The range is 0x0000 to 0xFFFF."
|
|
line.long 0xC "BDR,Timer/Counter 30 B Data Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BDATA,Timer/Counter 30 B Data bits. The range is 0x0000 to 0xFFFF."
|
|
line.long 0x10 "CDR,Timer/Counter 30 C Data Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CDATA,Timer/Counter 30 C Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter 30 Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter 30 Capture Data bits."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter 30 Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter 30 Prescaler Data bits."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Timer/Counter 30 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter 30 Counter bits."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "OUTCR,Timer/Counter 30 Output Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0xE06C to these bits otherwise the write is ignored."
|
|
bitfld.long 0x0 15. "POLB,PWM30xB Output Polarity Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "POLA,PWM30xA Output Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 13. "PABOE,PWM30AB Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PBBOE,PWM30BB Output Enable bit" "0,1"
|
|
bitfld.long 0x0 11. "PCBOE,PWM30CB Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PAAOE,PWM30AA Output Enable bit" "0,1"
|
|
bitfld.long 0x0 9. "PBAOE,PWM30BA Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCAOE,PWM30CA Output Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "LVLAB,Configure PWM30AB output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LVLBB,Configure PWM30BB output When Disable" "0,1"
|
|
bitfld.long 0x0 4. "LVLCB,Configure PWM30CB output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LVLAA,Configure PWM30AA output When Disable" "0,1"
|
|
bitfld.long 0x0 1. "LVLBA,Configure PWM30BA output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVLCA,Configure PWM30CA output When Disable" "0,1"
|
|
line.long 0x4 "DLY,Timer/Counter 30 PWM Output Delay Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "DLY,Timer/Counter 30 PWM Delay Data bits. Delay time: DLY[9:0]/fT30"
|
|
line.long 0x8 "INTCR,Timer/Counter 30 Interrupt Control Register"
|
|
bitfld.long 0x8 6. "HIZIEN,Timer 30 Output High-Impedance Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 5. "T30CIEN,Timer 30 Capture Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "T30BTIEN,Timer 30 Bottom Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 3. "T30PMIEN,Timer 30 Period Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "T30AMIEN,Timer 30 A-ch Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 1. "T30BMIEN,Timer 30 B-ch Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "T30CMIEN,Timer 30 C-ch Match Interrupt Enable bit" "0,1"
|
|
line.long 0xC "INTFLAG,Timer/Counter 30 Interrupt Flag Register"
|
|
bitfld.long 0xC 6. "HIZIFLAG,Timer 30 Output High-Impedance Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 5. "T30CIFLAG,Timer 30 Capture Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "T30BTIFLAG,Timer 30 Bottom Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 3. "T30PMIFLAG,Timer 30 Period Match Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "T30AMIFLAG,Timer 30 A-ch Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 1. "T30BMIFLAG,Timer 30 B-ch Match Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "T30CMIFLAG,Timer 30 C-ch Match Interrupt Flag bit" "0,1"
|
|
line.long 0x10 "HIZCR,Timer/Counter 30 High-Impedance Control Register"
|
|
bitfld.long 0x10 7. "HIZEN,PWM30xA/PWM30xB Output High-Impedance Enable bit" "0,1"
|
|
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0,1"
|
|
rbitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear bit" "0,1"
|
|
line.long 0x14 "ADTCR,Timer/Counter 30 A/DC Trigger Control Register"
|
|
bitfld.long 0x14 4. "T30BTTG,Select Timer 30 Bottom for A/DC Trigger Signal Generator" "0,1"
|
|
bitfld.long 0x14 3. "T30PMTG,Select Timer 30 Period Match for A/DC Trigger Signal Generator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "T30AMTG,Select Timer 30 A-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
bitfld.long 0x14 1. "T30BMTG,Select Timer 30 B-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "T30CMTG,Select Timer 30 C-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
line.long 0x18 "ADTDR,Timer/Counter 30 A/DC Trigger Generator Data Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,Timer/Counter 30 A/DC Trigger Generation Data bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER30"
|
|
base ad:0x40002400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR,Timer/Counter 30 Control Register"
|
|
bitfld.long 0x0 15. "EN,Timer 30 Operation Enable bit" "0: Disable timer 30 operation,1: Enable timer 30 operation (Counter clear and.."
|
|
bitfld.long 0x0 14. "CLK,Timer 30 Clock Selection bit (Note: This bit should be changed during T30EN bit is 0b.)" "0: Select an internal prescaler clock,1: Select an external clock"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "MS,Timer 30 Operation Mode Selection bits (Note: These bits should be changed during T30EN bit is 0b.)" "0: Interval mode (All match interrupts can occur),1: Capture mode (The Period-match interrupt can..,2: Back-to-back mode (All interrupts can occur),?"
|
|
bitfld.long 0x0 11. "ECE,Timer 30 External Clock Edge Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "FORCA,Timer 30 Output Mode Selection bit. This bit should be changed when the T30EN is 0b. Note: If this bit is changed on operation it shall apply from the next period." "0,1"
|
|
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer 30 Capture Polarity Selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection (Note: A period match counter is cleared as 0x00 when the T3nCLR bit is set or the PMOC[2:0] bits are changed.)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0. "CLR,Timer 30 Counter and Prescaler Clear bit" "0: No effect,1: Clear timer 30 counter and prescaler.."
|
|
line.long 0x4 "PDR,Timer/Counter 30 Period Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PDATA,Timer/Counter 30 Period Data bits. The range is 0x0002 to 0xFFFF."
|
|
line.long 0x8 "ADR,Timer/Counter 30 A Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ADATA,Timer/Counter 30 A Data bits. The range is 0x0000 to 0xFFFF."
|
|
line.long 0xC "BDR,Timer/Counter 30 B Data Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BDATA,Timer/Counter 30 B Data bits. The range is 0x0000 to 0xFFFF."
|
|
line.long 0x10 "CDR,Timer/Counter 30 C Data Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CDATA,Timer/Counter 30 C Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter 30 Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter 30 Capture Data bits."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter 30 Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter 30 Prescaler Data bits."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Timer/Counter 30 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter 30 Counter bits."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "OUTCR,Timer/Counter 30 Output Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0xE06C to these bits otherwise the write is ignored."
|
|
bitfld.long 0x0 15. "POLB,PWM30xB Output Polarity Selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "POLA,PWM30xA Output Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 13. "PABOE,PWM30AB Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PBBOE,PWM30BB Output Enable bit" "0,1"
|
|
bitfld.long 0x0 11. "PCBOE,PWM30CB Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PAAOE,PWM30AA Output Enable bit" "0,1"
|
|
bitfld.long 0x0 9. "PBAOE,PWM30BA Output Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCAOE,PWM30CA Output Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "LVLAB,Configure PWM30AB output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LVLBB,Configure PWM30BB output When Disable" "0,1"
|
|
bitfld.long 0x0 4. "LVLCB,Configure PWM30CB output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LVLAA,Configure PWM30AA output When Disable" "0,1"
|
|
bitfld.long 0x0 1. "LVLBA,Configure PWM30BA output When Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVLCA,Configure PWM30CA output When Disable" "0,1"
|
|
line.long 0x4 "DLY,Timer/Counter 30 PWM Output Delay Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "DLY,Timer/Counter 30 PWM Delay Data bits. Delay time: DLY[9:0]/fT30"
|
|
line.long 0x8 "INTCR,Timer/Counter 30 Interrupt Control Register"
|
|
bitfld.long 0x8 6. "HIZIEN,Timer 30 Output High-Impedance Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 5. "CIEN,Timer 30 Capture Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "BTIEN,Timer 30 Bottom Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 3. "PMIEN,Timer 30 Period Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AMIEN,Timer 30 A-ch Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x8 1. "BMIEN,Timer 30 B-ch Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CMIEN,Timer 30 C-ch Match Interrupt Enable bit" "0,1"
|
|
line.long 0xC "INTFLAG,Timer/Counter 30 Interrupt Flag Register"
|
|
bitfld.long 0xC 6. "HIZIFLAG,Timer 30 Output High-Impedance Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 5. "CIFLAG,Timer 30 Capture Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "BTIFLAG,Timer 30 Bottom Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 3. "PMIFLAG,Timer 30 Period Match Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "AMIFLAG,Timer 30 A-ch Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0xC 1. "BMIFLAG,Timer 30 B-ch Match Interrupt Flag bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "CMIFLAG,Timer 30 C-ch Match Interrupt Flag bit" "0,1"
|
|
line.long 0x10 "HIZCR,Timer/Counter 30 High-Impedance Control Register"
|
|
bitfld.long 0x10 7. "HIZEN,PWM30xA/PWM30xB Output High-Impedance Enable bit" "0,1"
|
|
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0,1"
|
|
bitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear bit" "0,1"
|
|
line.long 0x14 "ADTCR,Timer/Counter 30 A/DC Trigger Control Register"
|
|
bitfld.long 0x14 4. "BTTG,Select Timer 30 Bottom for A/DC Trigger Signal Generator" "0,1"
|
|
bitfld.long 0x14 3. "PMTG,Select Timer 30 Period Match for A/DC Trigger Signal Generator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "AMTG,Select Timer 30 A-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
bitfld.long 0x14 1. "BMTG,Select Timer 30 B-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "CMTG,Select Timer 30 C-ch Match for A/DC Trigger Signal Generator" "0,1"
|
|
line.long 0x18 "ADTDR,Timer/Counter 30 A/DC Trigger Generator Data Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,Timer/Counter 30 A/DC Trigger Generation Data bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER10"
|
|
base ad:0x40002100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER11"
|
|
base ad:0x40002200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER12"
|
|
base ad:0x40002300
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER13"
|
|
base ad:0x40002700
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER14"
|
|
base ad:0x40002800
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER15"
|
|
base ad:0x40002900
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER16"
|
|
base ad:0x40002A00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 31. "SSYNC,Synchronized start counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 30. "CSYNC,Synchronization clear counter with TIMER30" "0,1"
|
|
bitfld.long 0x0 15. "EN,Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write 0x0000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER20"
|
|
base ad:0x40002500
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "EN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 9.--10. "CAPSEL,Capture Signal Selection bit(olny timer20)" "0,1,2,3"
|
|
bitfld.long 0x0 8. "OPOL,Timer n Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000002 to 0xFFFFFFFF. Note: Do not write 0x00000000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
tree "TIMER21"
|
|
base ad:0x40002600
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Timer/Counter n Control Register"
|
|
bitfld.long 0x0 15. "EN,Timer n Operation Enable bit" "0,1"
|
|
bitfld.long 0x0 14. "CLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is 0b.)" "0,1"
|
|
bitfld.long 0x0 12.--13. "MS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is 0b.)" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ECE,Timer n External Clock Edge Selection bit" "0,1"
|
|
bitfld.long 0x0 9.--10. "CAPSEL,Capture Signal Selection bit(olny timer20)" "0,1,2,3"
|
|
bitfld.long 0x0 8. "OPOL,Timer n Polarity Selection bit" "0,1"
|
|
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
|
|
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
|
|
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
|
|
line.long 0x4 "ADR,Timer/Counter n A Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000002 to 0xFFFFFFFF. Note: Do not write 0x00000000 in the TnADR register when PPG mode."
|
|
line.long 0x8 "BDR,Timer/Counter n B Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CNT,Timer/Counter n Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x40004000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
|
|
endif
|
|
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
|
|
line.long 0x4 "IIR,UART Interrupt ID Register"
|
|
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
|
|
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
|
|
line.long 0x8 "LCR,UART Line Control Register"
|
|
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
|
|
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
|
|
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
|
|
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
|
|
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
|
|
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
|
|
line.long 0xC "DCR,UART Data Control Register"
|
|
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
|
|
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
|
|
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
|
|
line.long 0x10 "LSR,UART Line Status Register"
|
|
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
|
|
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
|
|
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
|
|
bitfld.long 0x10 3. "FE,frame error" "0,1"
|
|
bitfld.long 0x10 2. "PE,parity error" "0,1"
|
|
bitfld.long 0x10 1. "OE,overrun error" "0,1"
|
|
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
|
|
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 0.--1. "WAITVAL,wait time is decied by this value" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40004100
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "THR,Transmit Data Hold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
|
|
endif
|
|
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
|
|
line.long 0x4 "IIR,UART Interrupt ID Register"
|
|
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
|
|
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
|
|
line.long 0x8 "LCR,UART Line Control Register"
|
|
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
|
|
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
|
|
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
|
|
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
|
|
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
|
|
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
|
|
line.long 0xC "DCR,UART Data Control Register"
|
|
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
|
|
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
|
|
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
|
|
line.long 0x10 "LSR,UART Line Status Register"
|
|
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
|
|
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
|
|
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
|
|
bitfld.long 0x10 3. "FE,frame error" "0,1"
|
|
bitfld.long 0x10 2. "PE,parity error" "0,1"
|
|
bitfld.long 0x10 1. "OE,overrun error" "0,1"
|
|
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
|
|
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
|
|
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable bit" "0,1"
|
|
bitfld.long 0x0 6. "DMS,Data Bit Multi sampling enable" "0,1"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 0.--1. "WAITVAL,wait time is decied by this value" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "USART10"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,USARTn Control Register 1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
newline
|
|
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
|
|
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14.--15. "MS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12.--13. "PG,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9.--11. "DLEN,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "ORD,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "CPOL,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "CPHA,(null)The CPOL and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 5. "DRIE,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 4. "TXCIE,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "RXCIE,Receive Complete Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "TXE,Enables the Transmitter unit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "RXE,Enables the Receiver unit" "0,1"
|
|
endif
|
|
line.long 0x4 "CR2,USARTn Control Register 2"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DMATXIE,DMA Tx Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DMARXIE,DMA Rx Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "RTOIE,RTO Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "RTOEN,Active RTO Block by supplying. After RTO is occur this bit is clear" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BFREN,Activate Baud-Rate Fraction Counter Register" "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
|
|
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "EN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBLS,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 7. "MASTER,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 6. "LOOPS,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 5. "DISSCK,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 4. "SSEN,This bit controls the SSn pin operation (only SPI mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 3. "FXCH,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 2. "SB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 1. "TX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 0. "RX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
endif
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "ST,USARTn Status Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
|
|
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "DRE,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "TXC,Transmit Complete Interrupt Flag" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 5. "RXC,Receive Complete Interrupt Flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to 0 when write 1" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 2. "DOR,This bit is set if data OverRun occurs" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "FE,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "PE,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
|
|
line.long 0x8 "DR,USARTn Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "BFR,USARTn Baud-Rate Fraction Count Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BFC,USART Baud-Rate Fraction Counter"
|
|
line.long 0x4 "RTO,USARTn Receive Time Out Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART Receive Time Out"
|
|
endif
|
|
tree.end
|
|
tree "USART11"
|
|
base ad:0x40003900
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,USARTn Control Register 1"
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
newline
|
|
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
|
|
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 14.--15. "MS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 12.--13. "PG,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9.--11. "DLEN,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "ORD,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "CPOL,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "CPHA,(null)The CPOL and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 5. "DRIE,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 4. "TXCIE,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "RXCIE,Receive Complete Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "TXE,Enables the Transmitter unit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "RXE,Enables the Receiver unit" "0,1"
|
|
endif
|
|
line.long 0x4 "CR2,USARTn Control Register 2"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 14. "DMATXIE,DMA Tx Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 13. "DMARXIE,DMA Rx Interrupt Enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 12. "RTOIE,RTO Interrupt Enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 11. "RTOEN,Active RTO Block by supplying. After RTO is occur this bit is clear" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 10. "BFREN,Activate Baud-Rate Fraction Counter Register" "0,1"
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
|
|
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 9. "EN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 8. "DBLS,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 7. "MASTER,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 6. "LOOPS,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 5. "DISSCK,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 4. "SSEN,This bit controls the SSn pin operation (only SPI mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 3. "FXCH,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 2. "SB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 1. "TX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x4 0. "RX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
endif
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "ST,USARTn Status Register"
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G21*"))
|
|
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
|
|
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 7. "DRE,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 6. "TXC,Transmit Complete Interrupt Flag" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 5. "RXC,Receive Complete Interrupt Flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to 0 when write 1" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
rbitfld.long 0x0 2. "DOR,This bit is set if data OverRun occurs" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 1. "FE,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
sif (cpuis("A31G22*"))
|
|
bitfld.long 0x0 0. "PE,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
endif
|
|
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
|
|
line.long 0x8 "DR,USARTn Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
|
|
sif (cpuis("A31G22*"))
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "BFR,USARTn Baud-Rate Fraction Count Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BFC,USART Baud-Rate Fraction Counter"
|
|
line.long 0x4 "RTO,USARTn Receive Time Out Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART Receive Time Out"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("A31G22*"))
|
|
tree "USART12"
|
|
base ad:0x40003A00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,USARTn Control Register 1"
|
|
bitfld.long 0x0 14.--15. "MS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
bitfld.long 0x0 12.--13. "PG,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
bitfld.long 0x0 9.--11. "DLEN,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
bitfld.long 0x0 8. "ORD,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
bitfld.long 0x0 7. "CPOL,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
bitfld.long 0x0 6. "CPHA,(null)The CPOL and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
bitfld.long 0x0 5. "DRIE,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TXCIE,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCIE,Receive Complete Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "TXE,Enables the Transmitter unit" "0,1"
|
|
bitfld.long 0x0 0. "RXE,Enables the Receiver unit" "0,1"
|
|
line.long 0x4 "CR2,USARTn Control Register 2"
|
|
bitfld.long 0x4 14. "DMATXIE,DMA Tx Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 13. "DMARXIE,DMA Rx Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 12. "RTOIE,RTO Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 11. "RTOEN,Active RTO Block by supplying. After RTO is occur this bit is clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BFREN,Activate Baud-Rate Fraction Counter Register" "0,1"
|
|
bitfld.long 0x4 9. "EN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
bitfld.long 0x4 8. "DBLS,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
bitfld.long 0x4 7. "MASTER,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LOOPS,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
bitfld.long 0x4 5. "DISSCK,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
bitfld.long 0x4 4. "SSEN,This bit controls the SSn pin operation (only SPI mode)" "0,1"
|
|
bitfld.long 0x4 3. "FXCH,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
bitfld.long 0x4 1. "TX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register" "0,1"
|
|
bitfld.long 0x4 0. "RX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "ST,USARTn Status Register"
|
|
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
|
|
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
|
|
bitfld.long 0x0 7. "DRE,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXC,Transmit Complete Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXC,Receive Complete Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to 0 when write 1" "0,1"
|
|
rbitfld.long 0x0 2. "DOR,This bit is set if data OverRun occurs" "0,1"
|
|
bitfld.long 0x0 1. "FE,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
|
|
line.long 0x8 "DR,USARTn Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
|
|
line.long 0xC "BFR,USARTn Baud-Rate Fraction Count Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BFC,USART Baud-Rate Fraction Counter"
|
|
line.long 0x10 "RTO,USARTn Receive Time Out Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,USART Receive Time Out"
|
|
tree.end
|
|
tree "USART13"
|
|
base ad:0x40003B00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,USARTn Control Register 1"
|
|
bitfld.long 0x0 14.--15. "MS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
|
|
bitfld.long 0x0 12.--13. "PG,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
|
|
bitfld.long 0x0 9.--11. "DLEN,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
|
|
bitfld.long 0x0 8. "ORD,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
|
|
newline
|
|
bitfld.long 0x0 7. "CPOL,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
|
|
bitfld.long 0x0 6. "CPHA,(null)The CPOL and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
|
|
bitfld.long 0x0 5. "DRIE,Transmit Data Register Empty Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "TXCIE,Transmit Complete Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCIE,Receive Complete Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "TXE,Enables the Transmitter unit" "0,1"
|
|
bitfld.long 0x0 0. "RXE,Enables the Receiver unit" "0,1"
|
|
line.long 0x4 "CR2,USARTn Control Register 2"
|
|
bitfld.long 0x4 14. "DMATXIE,DMA Tx Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 13. "DMARXIE,DMA Rx Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 12. "RTOIE,RTO Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x4 11. "RTOEN,Active RTO Block by supplying. After RTO is occur this bit is clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BFREN,Activate Baud-Rate Fraction Counter Register" "0,1"
|
|
bitfld.long 0x4 9. "EN,(nActivate USARTn Block by supplyingull)" "0,1"
|
|
bitfld.long 0x4 8. "DBLS,Selects receiver sampling rate (only UART mode)" "0,1"
|
|
bitfld.long 0x4 7. "MASTER,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LOOPS,Control the Loop Back mode of USARTn for test mode" "0,1"
|
|
bitfld.long 0x4 5. "DISSCK,In synchronous mode operation selects the waveform of SCK output" "0,1"
|
|
bitfld.long 0x4 4. "SSEN,This bit controls the SSn pin operation (only SPI mode)" "0,1"
|
|
bitfld.long 0x4 3. "FXCH,SPI port function exchange control bit (only SPI mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
|
|
bitfld.long 0x4 1. "TX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USARTn_DR register" "0,1"
|
|
bitfld.long 0x4 0. "RX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "ST,USARTn Status Register"
|
|
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
|
|
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
|
|
bitfld.long 0x0 7. "DRE,Transmit Data Register Empty Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXC,Transmit Complete Interrupt Flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXC,Receive Complete Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to 0 when write 1" "0,1"
|
|
rbitfld.long 0x0 2. "DOR,This bit is set if data OverRun occurs" "0,1"
|
|
bitfld.long 0x0 1. "FE,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
|
|
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
|
|
line.long 0x8 "DR,USARTn Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
|
|
line.long 0xC "BFR,USARTn Baud-Rate Fraction Count Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BFC,USART Baud-Rate Fraction Counter"
|
|
line.long 0x10 "RTO,USARTn Receive Time Out Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,USART Receive Time Out"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40001A00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Watch-dog Timer Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x5A69 to these bits otherwise the write is ignored."
|
|
hexmask.long.byte 0x0 10.--15. 1. "RSTEN,Watch-dog Timer Reset Enable bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "CNTEN,Watch-dog Timer Counter Enable bits"
|
|
bitfld.long 0x0 3. "WINMIEN,Watch-dog Timer Window Match Interrupt Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UNFIEN,Watch-dog Timer Underflow Interrupt Enable bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "CLKDIV,Watch-dog Timer Clock Divider bits The clock which is selected by PPCLKSR[0]" "0,1,2,3"
|
|
line.long 0x4 "SR,Watch-dog Timer Status Register"
|
|
bitfld.long 0x4 7. "DBGCNTEN,Watch-dog Timer Counter Enable bit. When the core is halted in the debug mode. Note: This bit is cleared to '0b' only by POR reset." "0: The watch-dog timer counter continues even if..,1: The watch-dog timer counter is stopped when the.."
|
|
bitfld.long 0x4 1. "WINMIFLAG,Watch-dog Timer Window Match Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
|
|
newline
|
|
bitfld.long 0x4 0. "UNFIFLAG,Watch-dog Timer Underflow Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
|
|
line.long 0x8 "DR,Watch-dog Timer Data Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Watch-dog Timer Data bits. The range is 0x000000 to 0xFFFFFF."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CNT,Watch-dog Timer Counter Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Watch-dog Timer Counter bits."
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group.long 0x10++0x3
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line.long 0x0 "WINDR,Watch-dog Timer Window Data Register (Note: Once any value is written to this window data register. the register can't be changed until a system reset.)"
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hexmask.long.tbyte 0x0 0.--23. 1. "WDATA,Watch-dog Timer Window Data bits. The range is 0x000000 to 0xFFFFFF."
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wgroup.long 0x14++0x3
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line.long 0x0 "CNTR,Watch-dog Timer Counter Reload Register"
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hexmask.long.byte 0x0 0.--7. 1. "CNTR,Watch-dog Timer Counter Reload bits."
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tree.end
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tree "WT (Watch Timer)"
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base ad:0x40002000
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group.long 0x0++0x7
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line.long 0x0 "CR,Watch Timer Control Register"
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bitfld.long 0x0 7. "WTEN,Watch Timer Operation Enable bit" "0: Disable watch timer operation,1: Enable watch timer operation"
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bitfld.long 0x0 4.--5. "WTINTV,Watch Timer Interval Selection bits." "0: fWT/2^7,1: fWT/2^13,2: fWT/2^14,3: fWT/(2^14x(WTDR value + 1))"
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newline
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bitfld.long 0x0 3. "WTIEN,Watch Timer Interrupt Enable bit" "0: Disable watch timer interrupt,1: Enable watch timer interrupt"
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bitfld.long 0x0 1. "WTIFLAG,Watch Timer Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
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newline
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bitfld.long 0x0 0. "WTCLR,Watch Timer Counter and Divider Clear bit" "0: No effect,1: Clear the counter and divider (Automatically.."
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line.long 0x4 "DR,Watch Timer Data Register"
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hexmask.long.word 0x4 0.--11. 1. "WTDATA,Watch Timer Data bits. The range is 0x001 to 0xFFF."
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rgroup.long 0x8++0x3
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line.long 0x0 "CNT,Watch Timer Counter Register"
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hexmask.long.word 0x0 0.--11. 1. "CNT,Watch Timer Counter bits."
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tree.end
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AUTOINDENT.OFF
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