390 lines
13 KiB
Plaintext
390 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: CY8C4XXX-BL Specific Menu
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; @Props: Released
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; @Author: TRJ
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; @Changelog: 2017-05-31 TRJ
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Core: Cortex-M0
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; @Chip: CY8C4127FNI-BL483, CY8C4127FNI-BL493, CY8C4127LQI-BL453, CY8C4127LQI-BL473
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; CY8C4127LQI-BL483, CY8C4127LQI-BL493, CY8C4128FNI-BL443, CY8C4128FNI-BL453
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; CY8C4128FNI-BL473, CY8C4128FNI-BL483, CY8C4128FNI-BL493, CY8C4128FNI-BL543
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; CY8C4128FNI-BL553, CY8C4128FNI-BL563, CY8C4128FNI-BL573, CY8C4128FNI-BL583
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; CY8C4128FNI-BL593, CY8C4128LQI-BL443, CY8C4128LQI-BL453, CY8C4128LQI-BL473
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; CY8C4128LQI-BL483, CY8C4128LQI-BL493, CY8C4128LQI-BL543, CY8C4128LQI-BL553
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; CY8C4128LQI-BL563, CY8C4128LQI-BL573, CY8C4128LQI-BL583, CY8C4128LQI-BL593
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; CY8C4247FNI-BL483, CY8C4247FNI-BL493, CY8C4247LQI-BL453, CY8C4247LQI-BL463
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; CY8C4247LQI-BL473, CY8C4247LQI-BL483, CY8C4247LQI-BL493, CY8C4248FLI-BL483
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; CY8C4248FLI-BL583, CY8C4248FNI-BL453, CY8C4248FNI-BL463, CY8C4248FNI-BL473
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; CY8C4248FNI-BL483, CY8C4248FNI-BL493, CY8C4248FNI-BL543, CY8C4248FNI-BL553
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; CY8C4248FNI-BL563, CY8C4248FNI-BL573, CY8C4248FNI-BL583, CY8C4248FNI-BL593
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; CY8C4248FNQ-BL583
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menpsoc4xx8ble.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control"""
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menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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if (cpuis("CY8C42*-BL*"))
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(
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menuitem "BCTL" "per , ""BCTL (UDB Array Bank Control)"""
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)
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menuitem "BLELL" "per , ""BLELL (BLE Link Layer)"""
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menuitem "BLERD" "per , ""BLERD (BLE Radio)"""
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menuitem "BLESS" "per , ""BLESS (BLE Sub System)"""
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menuitem "BLESS2" "per , ""BLESS2 (BLE Sub System Version 2)"""
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popup "CNT"
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(
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menuitem "CNT 0" "per , ""CNT (TCPWM - Individual Counter),CNT 0"""
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menuitem "CNT 1" "per , ""CNT (TCPWM - Individual Counter),CNT 1"""
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menuitem "CNT 2" "per , ""CNT (TCPWM - Individual Counter),CNT 2"""
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menuitem "CNT 3" "per , ""CNT (TCPWM - Individual Counter),CNT 3"""
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)
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menuitem "SRSS" "per , ""SRSS (System Resources Sub System)"""
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menuitem "CPUSS" "per , ""CPUSS (CPU Sub System)"""
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menuitem "DMAC" "per , ""DMAC (DMA Controller)"""
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menuitem "DMAD" "per , ""DMAD (DMA Descriptor)"""
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if (cpuis("CY8C4*-BL453")||cpuis("CY8C4*-BL483")||cpuis("CY8C4*-BL493"))
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(
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menuitem "CSD" "per , ""CSD (CapSense Sigma Delta)"""
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)
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if (!cpuis("CY8C4*-BL443"))
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(
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if (cpuis("CY8C41*-BL*"))
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(
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menuitem "CTBM" "per , ""CTBM (Continuous Time Block Mini)"""
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)
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if (cpuis("CY8C42*-BL*"))
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(
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popup "CTBM"
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(
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menuitem "CTBM0" "per , ""CTBM (Continuous Time Block Mini),CTBM0"""
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menuitem "CTBM1" "per , ""CTBM (Continuous Time Block Mini),CTBM1"""
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)
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)
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)
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menuitem "DSAB" "per , ""DSAB (Deep Sleep Amplifier Bias)"""
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if (cpuis("CY8C42*-BL*"))
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(
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menuitem "DSI" "per , ""DSI (Digital System Interconnect)"""
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)
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popup "GPIO"
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(
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menuitem "GPIO" "per , ""GPIO (General Purpose Input/Output)"""
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popup "GPIO - PS"
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(
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menuitem "PRT0" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT0"""
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menuitem "PRT1" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT1"""
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menuitem "PRT2" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT2"""
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menuitem "PRT3" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT3"""
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menuitem "PRT4" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT4"""
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menuitem "PRT5" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT5"""
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menuitem "PRT6" "per , ""GPIO (General Purpose Input/Output),Port Specific,PRT6"""
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)
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)
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popup "HSIOM"
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(
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menuitem "HSIOM" "per , ""HSIOM (High Speed IO Matrix),HSIOM"""
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menuitem "HSIOM - Port Specific" "per , ""HSIOM (High Speed IO Matrix),HSIOM - Port Specific"""
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)
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if (cpuis("CY8C4*-BL463")||cpuis("CY8C4*-BL483")||cpuis("CY8C4*-BL493"))
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(
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menuitem "LCD" "per , ""LCD (Liquid Crystal Display)"""
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)
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if (!cpuis("CY8C4128LQI-BL443")&&!cpuis("CY8C4128FNI-BL443"))
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(
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menuitem "LPCOMP" "per , ""LPCOMP (Low Power Comparator)"""
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)
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if (cpuis("CY8C42*-BL*"))
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(
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menuitem "PA" "per , ""PA (Port Adaptor)"""
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)
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menuitem "PASS MMIO" "per , ""PASS MMIO (Programmable Analog Sub System MMIO)"""
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menuitem "PERI" "per , ""PERI (Peripheral Interconnect)"""
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menuitem "ROM" "per , ""ROM Table"""
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if (cpuis("CY8C42*-BL*"))
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(
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popup "ROUTE"
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(
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menuitem "ROUTE0" "per , ""ROUTE,ROUTE0"""
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menuitem "ROUTE1" "per , ""ROUTE,ROUTE1"""
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)
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)
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menuitem "SAR" "per , ""SAR (Successive Approximation Register)"""
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popup "SCB"
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(
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menuitem "SCB0" "per , ""SCB (Serial Communication Block),SCB0"""
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menuitem "SCB1" "per , ""SCB (Serial Communication Block),SCB1"""
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)
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menuitem "SFLASH" "per , ""SFLASH (Supervisory Flash)"""
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menuitem "SPCIF" "per , ""SPCIF (SPC Interface)"""
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menuitem "TCPWM" "per , ""(Timer Counter PWM)"""
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menuitem "TST" "per , ""TST (Test)"""
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if (cpuis("CY8C42*-BL*"))
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(
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menuitem "UDBIF" "per , ""UDBIF (UDB Interface)"""
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menuitem "UDB" "per , ""UDB (Universal Digital Block)"""
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popup "UDBSNG"
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(
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menuitem "UDB P0 U0" "per , ""UDBSNG (Single UDB),UDB P0 U0"""
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menuitem "UDB P0 U1" "per , ""UDBSNG (Single UDB),UDB P0 U1"""
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menuitem "UDB P1 U0" "per , ""UDBSNG (Single UDB),UDB P1 U0"""
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menuitem "UDB P1 U1" "per , ""UDBSNG (Single UDB),UDB P1 U1"""
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)
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menuitem "WRK8" "per , ""WRK8 (UDB 8-Bit Working)"""
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menuitem "WRK16CAT" "per , ""WRK16CAT (UDB 16-bit Concatenated Working)"""
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menuitem "WRK16DEF" "per , ""WRK16DEF (UDB 16-bit Working)"""
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menuitem "WRK32" "per , ""WRK32 (UDB 32-bit Working)"""
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)
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)
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)
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