377 lines
7.6 KiB
ArmAsm
377 lines
7.6 KiB
ArmAsm
.text
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.globl _start
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.globl _exit.crt0
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.globl watchdogTrigger
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#ifdef __thumb__
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# define subs sub
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#endif
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.macro WEAK_FUNCTION name
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.weak \name
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.thumb_func
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\name :
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.endm
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_start:
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/* disable interrupts, enable faults */
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cpsid i
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cpsie f
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mov r0, #0
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msr BASEPRI, r0
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/* set stack and frame pointer */
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ldr r1, .SP
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mov r0, #7
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bic r1, r0
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mov r0, #0
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mov sp, r1
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mov fp, r0
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mov lr, r0
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#if defined(__ARM_ARCH_7M__)||defined(__ARM_ARCH_7EM__)||defined(__ARM_ARCH_8M_BASE__)||defined(__ARM_ARCH_8M_MAIN__)
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/* set NVIC Base */
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ldr r4, .VTOR
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ldr r0, .NVIC_BASE
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str r0, [r4]
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#if (__ARM_FP==4)||(__ARM_FP==5)
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/* enable FPU */
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ldr r4, .CPACR
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ldr r1, .CPACR_FPU_EN
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ldr r0,[r4]
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orr r0, r1
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str r0,[r4]
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#endif
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#endif
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/* early initialize Watchdog */
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ldr r3, .WDG_INIT_EARLY
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cmp r3, #0
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beq wdg_init_early_done
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bl crt0_veneer
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wdg_init_early_done:
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#if defined(ENABLE_ICACHE)&&(defined(__ARM_ARCH_7M__)||defined(__ARM_ARCH_7EM__)||defined(__ARM_ARCH_8M_MAIN__))
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bl enableIC
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#endif
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#if defined(RAM_ECC_LONG)||defined(RAM_ECC_SHORT)
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ldr r2, .ECC_RAMSTART
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ldr r1, .ECC_RAMSIZE
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ldr r4, .DATA_S
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ldr r5, .DATA_LADDR
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cmp r4, r5
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b ecc_check
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ecc_clear:
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#if defined(RAM_ECC_LONG)
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subs r1, r1, #0x4
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str r0, [r2, r1]
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#elif defined(RAM_ECC_SHORT)
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subs r1, r1, #0x2
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strh r0, [r2, r1]
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#endif
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ecc_check:
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bne ecc_clear
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#endif
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#if defined(ENABLE_DCACHE)&&(defined(__ARM_ARCH_7M__)||defined(__ARM_ARCH_7EM__)||defined(__ARM_ARCH_8M_MAIN__))
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bl enableDC
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#endif
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/* copy data from FLASH to SRAM */
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ldr r4, .DATA_S
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ldr r5, .DATA_LADDR
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ldr r6, .DATA_SIZE
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cmp r4, r5
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beq data_done
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data_copy:
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ldrb r0, [r5]
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strb r0, [r4]
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add r4, r4, #1
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add r5, r5, #1
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subs r6, r6, #1
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bne data_copy
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data_done:
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/* clear .bss-section */
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ldr r4, .BSS_S
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ldr r5, .BSS_E
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mov r0, #0
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b bss_check
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bss_clear:
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strb r0, [r4]
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add r4, r4, #1
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bss_check:
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cmp r5, r4
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bne bss_clear
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bss_done:
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/* initialize Watchdog */
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ldr r3, .WDG_INIT
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cmp r3, #0
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beq wdg_init_done
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bl crt0_veneer
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wdg_init_done:
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/* register the WatchdogHook */
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ldr r3, .WDG_TRIGGER
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ldr r4, .WDG_HOOK
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str r3, [r4]
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/* initialization of e.g. static objects */
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ldr r4, .INIT_S
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ldr r5, .INIT_LADDR
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ldr r6, .INIT_SIZE
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cmp r6, #0
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beq init_done
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add r7, r6, #4
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cmp r4, r5
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beq init_check
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init_copy:
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subs r6, r6, #1
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ldrb r0, [r5, r6]
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strb r0, [r4, r6]
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bne init_copy
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b init_check
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init:
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ldm r4!, {r3}
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bl crt0_veneer
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init_check:
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subs r7, r7, #4
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bne init
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init_done:
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gomain:
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ldr r3, .MAIN
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bl crt0_veneer
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nop
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_exit.crt0:
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/* we should never get here */
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b _exit.crt0
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/* intended fallthrough for all weak default handlers */
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WEAK_FUNCTION NMI_Handler
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WEAK_FUNCTION HardFault_Handler
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WEAK_FUNCTION MemManage_Handler
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WEAK_FUNCTION BusFault_Handler
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WEAK_FUNCTION UsageFault_Handler
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WEAK_FUNCTION SVC_Handler
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WEAK_FUNCTION PendSV_Handler
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WEAK_FUNCTION SysTick_Handler
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WEAK_FUNCTION _exit
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.thumb_func
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_hang:
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/* default fault handler */
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b _hang
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crt0_veneer:
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/* make a THUMB/ARM generic veneer call to r3 */
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/* lr is set by preceding bl instruction */
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mov r0, #0
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mov r1, #0
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bx r3
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.org 0x100
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_start_secondary:
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/* set stack and frame pointer */
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/* _start_secondary-_start = 0x100 -> SP is placed 0x100 bytes after SP of Core0 */
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ldr r1, .SP
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mov r0, #0
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mov sp, r1
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mov fp, r0
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bl background
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b _exit.crt0
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.align 2
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.SP:
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.word __stack_end
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.BSS_S:
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.word __bss_start
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.BSS_E:
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.word __bss_end
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.INIT_S:
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.word __init_vaddr
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.INIT_LADDR:
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.word __init_laddr
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.INIT_SIZE:
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.word __init_size
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.DATA_S:
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.word __data_vaddr
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.DATA_LADDR:
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.word __data_laddr
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.DATA_SIZE:
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.word __data_size
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#ifndef WATCHDOG
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.WDG_INIT:
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.word 0x0
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.WDG_INIT_EARLY:
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.word 0x0
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.WDG_TRIGGER:
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.word 0x0
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#else
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.WDG_INIT:
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.word WatchdogInit
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.WDG_INIT_EARLY:
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.word WatchdogInitEarly
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.WDG_TRIGGER:
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.word WatchdogTrigger
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#endif
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.WDG_HOOK:
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.word watchdogTrigger
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.MAIN:
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.word main
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.NVIC_BASE:
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.word __nvic_base
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.VTOR:
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.word 0xe000ed08
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.CPACR:
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.word 0xe000ed88
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.CPACR_FPU_EN:
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.word 0x00f00000
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.ECC_RAMSTART:
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.word __SRAM_start
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#ifdef RAMSIZE
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.ECC_RAMSIZE:
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.word RAMSIZE
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#else
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.ECC_RAMSIZE:
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.word __SRAM_size
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#endif
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.section .exception_vector
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.word __stack_end /* 0x00 initial SP */
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.word _start+1 /* 0x04 Reset */
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.word NMI_Handler /* 0x08 NMI */
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.word HardFault_Handler /* 0x0c Hard fault */
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.word MemManage_Handler /* 0x10 MPU */
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.word BusFault_Handler /* 0x14 Bus fault */
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.word UsageFault_Handler /* 0x18 Usage fault */
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.word 0 /* 0x1C Reserved */
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.word 0 /* 0x20 Reserved */
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.word 0 /* 0x24 Reserved */
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.word 0 /* 0x28 Reserved */
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.word SVC_Handler /* 0x2c SVCall */
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.word 0 /* 0x30 Reserved */
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.word 0 /* 0x34 Reserved */
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.word PendSV_Handler /* 0x38 PendSV */
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.word SysTick_Handler /* 0x3c Systick */
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/* 0x40 onwards NVIC table Interrupts */
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.section .text
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.weak background
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background:
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nop
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1:
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wfe
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b 1b
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#if defined(__ARM_ARCH_7M__)||defined(__ARM_ARCH_7EM__)||defined(__ARM_ARCH_8M_MAIN__)
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.section .text
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.thumb_func
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enableIC:
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/* check for ICache */
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ldr r1, .CLIDR
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ldr r0, [r1]
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mov r1, #0x1
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tst r0, r1
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beq enable_ic_done
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/* invalidate ICache */
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mov r0, #0x0
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ldr r1, .ICIALLU
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str r0, [r1]
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dsb
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isb
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/* enalbe ICache */
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ldr r2, .CCR
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ldr r1, .CCR_IC
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ldr r0, [r2]
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orr r0, r1
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str r0, [r2]
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dsb
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isb
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enable_ic_done:
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bx r14
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.thumb_func
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enableDC:
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/* check for DCache */
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ldr r1, .CLIDR
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ldr r0, [r1]
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mov r1, #0x2
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tst r0, r1
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beq enable_dc_done
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/* detect DCache set & way*/
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mov r0, #0x0
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ldr r1, .CSSELR
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str r0, [r1]
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dsb
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ldr r1, .CCSIDR
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ldr r2, .CCSIDR_WAY_MASK
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ldr r3, .CCSIDR_SET_MASK
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ldr r5, [r1]
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mov r6, r5
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lsr r5, r5, #0x3
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mov r4, r5
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lsr r5, r5, #0xa
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and r4, r2 /* #Ways */
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and r5, r3 /* #Sets */
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mov r0, #0x7
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and r6, r0
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add r6, #0x2 /* #log2(Words) */
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clz r7, r4 /* WayShift */
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/* invalidate DCache */
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ldr r1, .DCISW
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1:
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mov r6, r5
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lsl r6, #0x5 /* DCISW.currentSet */
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mov r3, r4 /* currentWay */
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2:
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mov r0, r6
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mov r2, r3
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lsl r2, r7
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orr r0, r2
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str r0, [r1] /* DCISW */
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sub r3, #0x1
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bge 2b
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sub r5, #0x1
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bge 1b
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/* enable DCache */
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dsb
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isb
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ldr r2, .CCR
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ldr r1, .CCR_DC
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ldr r0, [r2]
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orr r0, r1
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str r0, [r2]
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dsb
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isb
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enable_dc_done:
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bx r14
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.align 2
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.CLIDR:
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.word 0xe000ed78
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.CCSIDR:
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.word 0xe000ed80
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.CCSIDR_WAY_MASK:
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.word 0x3ff
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.CCSIDR_SET_MASK:
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.word 0x7fff
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.CSSELR:
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.word 0xe000ed84
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.CCR:
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.word 0xe000ed14
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.CCR_IC:
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.word 0x00020000
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.CCR_DC:
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.word 0x00010000
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.ICIALLU:
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.word 0xe000ef50
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.DCISW:
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.word 0xe000ef60
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#endif
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.section .data
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watchdogTrigger:
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.word 0x0
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