227 lines
7.2 KiB
Plaintext
227 lines
7.2 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Xilinx ZEDBOARD(ZYNQ-7000) SPI Flash Programming CMM
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; @Description:
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; SPI Flash(SPANSION, S25FL256) is connected to the PS_MIO1 (CS1)
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; SPI Flash(SPANSION, S25FL256) is connected to the PS_MIO0 (CS2)
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; Code uses OnchipRam Mapped to
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; 0xFFFC0000--0xFFFFFFFF
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; LQSPI Tx Register : 0xE000D080
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; LQSPI Rx Register : 0xE000D020
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; LQSPI CS Register : 0xE000D000
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;
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; Prerequisites:
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; * Debugger or Combiprobe is connected to
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; 14pin JTAG header using LA-3881 adapter
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; * MIO[6..2]=0y00000 - JTAG BOOT
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; or
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; MIO[6..2]=0y01100 - SD BOOT and remove the SD-Card
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; * Please power-cycle the board before executing the script
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;
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; Note:
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; for Flash devices <64MB please adapt the FLASHFILE.CONFIG line (see comment)
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;
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; @Author: AME JIM
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: Zynq-7000
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; @Board: ZedBoard
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; @Keywords: Zynq Zynq7000 Spansion S25FL256 flash spi
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; --------------------------------------------------------------------------------
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; $Id: zc70x-spi64dual.cmm 10516 2022-02-02 11:39:30Z bschroefel $
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; $Rev: 10516 $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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LOCAL &ctrl_reg
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LOCAL &tx_reg
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LOCAL &rx_reg
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&ctrl_reg=0xE000D000
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&tx_reg=0xE000D080 ;Register TXD1 for the 1-byte instruction
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&rx_reg=0xE000D020
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WinCLEAR
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SYStem.RESet
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RESet
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SYStem.CPU ZYNQ-7000
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SYStem.MemAccess DAP
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; This selects the DAP for accessing the ARM cores
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; (accessing the TAP of the FPGA logic requires different settings)
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SYStem.CONFIG.DAPIRPRE 6.
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SYStem.CONFIG.DAPIRPOST 0.
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SYStem.CONFIG.DAPDRPRE 1.
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SYStem.CONFIG.DAPDRPOST 0.
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TrOnchip.Set.RESET OFF
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TrOnchip.Set.UNDEF OFF
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TrOnchip.Set.DABORT OFF
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TrOnchip.Set.PABORT OFF
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SYStem.JtagClock Ctck 10.0MHz
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CORE.ASSIGN 1.
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SYStem.Mode.Attach
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IF STATE.RUN()
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Break.direct
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//disable MMU & Cache
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PER.Set C15:0x1 %Long 0x18c52c78
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; PC should be around 0xfffc0000--0xffffffff
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; SLCR - UNLOCK WRITE
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Data.Set ASD:0XF8000008 %Long 0x0000DF0D
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; Assert Reset of Second core - we are save to remap memories
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Data.Set ASD:0xF8000244 %Long 0x2
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; MMU disable, Exception Vectors HIGH
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Data.Set C15:0x1 %Long 0x18C52478
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; OCM_CFG - ALL RAMS HIGH 0xfffc0000
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Data.Set AZSD:0xF8000910 %Long 0x1F
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; exception Vectors
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Data.Assemble R:0xffff0000 b $+0
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Data.Assemble , b $+0
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Data.Assemble , b $+0
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Data.Assemble , b $+0
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Data.Assemble , b $+0
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Data.Assemble , b $+0
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Data.Assemble , b $+0
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; set PC to a endless loop in OCM - prevent issues with XIP mode
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Register.Set PC 0xffff0020
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Data.Assemble R:0xffff0020 b $+0
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//spi pin configuration
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Data.Set ASD:0xF8000700 %Long %LE 0x00003302 ; PS_MIO0 -> QSPI2_CS
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Data.Set ASD:0xF8000704 %Long %LE 0x00003302 ; PS_MIO1 -> QSPI1_CS
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Data.Set ASD:0xF8000708 %Long %LE 0x00000302 ; PS_MIO2 -> QSPI1_IO0
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Data.Set ASD:0xF800070C %Long %LE 0x00000302 ; PS_MIO3 -> QSPI1_IO1
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Data.Set ASD:0xF8000710 %Long %LE 0x00000302 ; PS_MIO4 -> QSPI1_IO2
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Data.Set ASD:0xF8000714 %Long %LE 0x00000302 ; PS_MIO5 -> QSPI1_IO3
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Data.Set ASD:0xF8000718 %Long %LE 0x00002302 ; PS_MIO6 -> QSPI1_CLK
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Data.Set ASD:0xF8000724 %Long %LE 0x00002302 ; PS_MIO9 -> QSPI2_CLK
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Data.Set ASD:0xF8000728 %Long %LE 0x00000302 ; PS_MIO10 -> QSPI2_IO0
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Data.Set ASD:0xF800072C %Long %LE 0x00000302 ; PS_MIO11 -> QSPI2_IO1
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Data.Set ASD:0xF8000730 %Long %LE 0x00000302 ; PS_MIO12 -> QSPI2_IO2
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Data.Set ASD:0xF8000734 %Long %LE 0x00000302 ; PS_MIO13 -> QSPI2_IO3
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;Data.Set AZSD:0xF800014C %LE %Long 0x2821 ;default clk for qspi
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Data.Set AZSD:0xF800014C %LE %Long 0x521 ; 173Mhz clk for qspi
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Data.Set AZSD:0xF800012C %LE %Long Data.Long(AZSD:0xF800012C)|0x800000 ; Enable Clock of QSPI
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Data.Set AZSD:0xF8000230 %LE %Long 0x3 ; assert RESET
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WAIT 100.ms
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Data.Set AZSD:0xF8000230 %LE %Long 0x0 ; deassert RESET
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WAIT 100.ms
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Data.Set AZSD:0xE000D014 %LE %Long 0x0 ; Disable QSPI
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Data.Set AZSD:0xE000D000 %LE %Long 0x80020021 ; Configuration SPI, CS0, 8bits, Master Mode
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Data.Set AZSD:0xE000D000 %LE %Long Data.Long(AZSD:0xE000D000)|(0x1<<14.) ;manual CS mode
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Data.Set AZSD:0xE000D008 %LE %Long 0xFF ; Enable SPI Interupt
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Data.Set AZSD:0xE000D0A0 %Long 0x60000003 ; disable LQ_MODE, enable TWO_MEM & SEP_BUS for dual spi devices
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Data.Set AZSD:0xE000D028 %Long 0x1
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Data.Set AZSD:0xE000D02C %Long 0x1
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Data.Set AZSD:0xE000D038 %Long 0x33
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Data.Set AZSD:0xE000D014 %LE %Long 0x1 ; Enable QSPI
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//FLASH READ ID TEST
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AREA.view
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GOSUB READ_ID_TEST
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DIALOG.YESNO "Is the flash ID correctly shown in the AREA window?"
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LOCAL &result
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ENTRY &result
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IF !&result
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(
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PRINT "Please check your register configuration to enable your flash controller"
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ENDDO
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)
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programFlash:
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;support Dual Flash parallel only for the 3B address
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FLASHFILE.RESet
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FLASHFILE.CONFIG 0xE000D080 0xE000D020 0xE000D000
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FLASHFILE.TARGET 0xFFFC0000++0x3FFF 0xFFFD0000++0x41FF ~~/demo/arm/flash/byte/spi64_pele.bin /KEEP ; 3B address mode
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;not support Dual Flash parallel for the 4B address
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;for S25FL256 (Spansion)
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;FLASHFILE.TARGET 0xFFFC0000++0x3FFF 0xFFFD0000++0x41FF ~~/demo/arm/flash/byte/spi4b64_pele.bin /KEEP ; 4B address mode
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;for N25Q00 (Micron) , Zynq does not support the 4B address mode for N25Q00 type
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;FLASHFILE.TARGET 0xFFFC0000++0x3FFF 0xFFFD0000++0x41FF ~~/demo/arm/flash/byte/spin25q00_pele.bin /KEEP ; 4B address mode
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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//Dump window for Serial FLASH
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FLASHFILE.DUMP 0x0 ; Also can read the spi flash data at 0xFC00_0000 after LQSPI_CFG.LQ_MODE is enabled
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//Erase Serial FLASH
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;FLASHFILE.ERASE 0x0--0x1FFFFF
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//Write Serial FLASH
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;FLASHFILE.LOAD boot.bin 0x0
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;FLASHFILE.LOAD boot.bin 0x0 /ComPare
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ENDDO
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READ_ID_TEST:
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LOCAL &data
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&data=Data.Long(A:&ctrl_reg)
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PRINT "ctrl_reg : &data "
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Data.Set &ctrl_reg %Long (&data&(~(0x1<<10.))) ; cs low
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Data.Set &tx_reg %Byte 0x9F
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT " 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &tx_reg %Byte 0x00
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT "1st : 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &tx_reg %Byte 0x00
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT "2nd : 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &tx_reg %Byte 0x00
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT "3rd : 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &tx_reg %Byte 0x00
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT "4th : 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &tx_reg %Byte 0x00
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&data=Data.Long(A:&ctrl_reg)
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Data.Set &ctrl_reg %Long (&data|(0x1<<16.)) ; start cmd
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WAIT 1.ms
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PRINT "5th : 0x" FORMAT.HEX(2,(Data.Long(A:&rx_reg)>>24.)&0xFF)
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Data.Set &ctrl_reg %Long (&data|(0x1<<10.)) ; cs high
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RETURN
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