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Gen4_R-Car_Trace32/2_Trunk/perwpr1516.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: WPR1516 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2023-02-07 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated (SVD2PER 1.8.6), based on: MWPR1516.svd (Ver. 1.6)
; @Core: Cortex-M0+
; @Chip: WPR1516
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perwpr1516.per 15729 2023-02-07 15:10:03Z kwisniewski $
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ACMP0 (Analog comparator)"
base ad:0x40073000
group.byte 0x00++0x00
line.byte 0x00 "CS,ACMP Control and Status Register"
bitfld.byte 0x00 7. "ACE,Analog Comparator Enable" "0: The ACMP is disabled,1: The ACMP is enabled"
bitfld.byte 0x00 6. "HYST,Analog Comparator Hysterisis Selection" "0: 20 mV,1: 30 mV"
newline
bitfld.byte 0x00 5. "ACF,ACMP Interrupt Flag Bit" "0,1"
bitfld.byte 0x00 4. "ACIE,ACMP Interrupt Enable" "0: Disable the ACMP Interrupt,1: Enable the ACMP Interrupt"
newline
rbitfld.byte 0x00 3. "ACO,ACMP Output" "0,1"
bitfld.byte 0x00 2. "ACOPE,ACMP Output Pin Enable" "0: ACMP output cannot be placed onto external pin,1: ACMP output can be placed onto external pin"
newline
bitfld.byte 0x00 0.--1. "ACMOD,ACMP MOD" "0: ACMP interrupt on output falling edge,1: ACMP interrupt on output rising edge,2: ACMP interrupt on output falling edge,3: ACMP interrupt on output falling or rising edge"
group.byte 0x01++0x00
line.byte 0x00 "C0,ACMP Control Register 0"
bitfld.byte 0x00 4.--5. "ACPSEL,ACMP Positive Input Select" "0: External reference 0,1: External reference 1,2: External reference 2,3: DAC output"
bitfld.byte 0x00 0.--1. "ACNSEL,ACMP Negative Input Select" "0: External reference 0,1: External reference 1,2: External reference 2,3: DAC output"
group.byte 0x02++0x00
line.byte 0x00 "C1,ACMP Control Register 1"
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: The DAC is disabled,1: The DAC is enabled"
bitfld.byte 0x00 6. "DACREF,DAC Reference Select" "0: The DAC selects VREFH as the reference,1: The DAC selects VDDA as the reference"
newline
bitfld.byte 0x00 0.--5. "DACVAL,DAC Output Level Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x03++0x00
line.byte 0x00 "C2,ACMP Control Register 2"
bitfld.byte 0x00 0.--2. "ACIPE,ACMP Input Pin Enable" "0: The corresponding external analog input is..,1: The corresponding external analog input is..,?..."
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x4003B000
group.byte 0x00++0x00
line.byte 0x00 "TIM,ADC Timing Register"
hexmask.byte 0x00 0.--6. 1. "PRS,ADC Clock Prescaler"
group.byte 0x01++0x00
line.byte 0x00 "STS,ADC Status Register"
bitfld.byte 0x00 7. "CSL_SEL,Command Sequence List Select bit" "0: ADC Command List 0 is active,1: ADC Command List 1 is active"
bitfld.byte 0x00 6. "RVL_SEL,Result Value List Select Bit" "0: ADC Result List 0 is active,1: ADC Result List 1 is active"
newline
rbitfld.byte 0x00 3. "READY,Ready For Restart Event Flag" "0: ADC not in idle state,1: ADC is in idle state"
group.byte 0x02++0x00
line.byte 0x00 "CTL1,ADC Control Register 1"
bitfld.byte 0x00 7. "CSL_BMOD,CSL Buffer Mode Select Bit" "0: CSL single buffer mode,1: CSL double buffer mode"
bitfld.byte 0x00 6. "RVL_BMOD,RVL Buffer Mode Select Bit" "0: RVL single buffer mode,1: RVL double buffer mode"
newline
bitfld.byte 0x00 5. "SMOD_ACC,Special Mode Access Control Bit" "0: Normal user access - Register write..,1: Special access - Register write restrictions.."
bitfld.byte 0x00 4. "AUT_RSTA,Automatic Restart Event after exit from MCU Stop and Wait Mode (SWAI set)" "0: No automatic restart event after exit from..,1: Automatic restart event occurs after exit.."
group.byte 0x03++0x00
line.byte 0x00 "CTL0,ADC Control Register 0"
bitfld.byte 0x00 7. "ADC_EN,ADC Enable Bit" "0: ADC disabled,1: ADC enabled"
bitfld.byte 0x00 6. "ADC_SR,ADC Soft-Reset" "0: No ADC Soft-Reset issued,1: Issue ADC Soft-Reset"
newline
bitfld.byte 0x00 5. "FRZ_MOD,Freeze Mode Configuration" "0: ADC continues conversion in Freeze mode,1: ADC freezes the conversion at next conversion.."
bitfld.byte 0x00 4. "SWAI,Wait Mode Configuration" "0: ADC continues conversion in Wait mode,1: ADC halts the conversion at next conversion.."
newline
bitfld.byte 0x00 2.--3. "ACC_CFG,ADC_FLWCTL Register Access Configuration" "0: None of the access paths is enabled (default..,1: Single access mode - internal..,2: Single access mode - data bus(ADC_FLWCTL..,3: Dual access mode(ADC_FLWCTL register access.."
bitfld.byte 0x00 1. "STR_SEQA,Control Of Conversion Result Storage and RSTAR_EIF flag setting at Sequence Abort or Restart Event" "0,1"
newline
bitfld.byte 0x00 0. "MOD_CFG,(Conversion Flow Control) Mode Configuration" "0: Restart Mode selected,1: Trigger Mode selected"
group.byte 0x04++0x00
line.byte 0x00 "IE,ADC Interrupt Enable Register"
bitfld.byte 0x00 7. "SEQAD_IE,Conversion Sequence Abort Done Interrupt Enable Bit" "0: Conversion sequence abort event done..,1: Conversion sequence abort event done.."
bitfld.byte 0x00 6. "CONIF_OIE,ADCCONIF Register Flags Overrun Interrupt Enable" "0: No ADC_CONIF Register Flag overrun is occurred,1: ADC_CONIF Register Flag overrun is occurred"
group.byte 0x05++0x00
line.byte 0x00 "EIE,ADC Error Interrupt Enable Register"
bitfld.byte 0x00 7. "WA_EIE,Write Access Error Interrupt Enable Bit" "0: Write access error interrupt is disabled,1: Write access error interrupt is enabled"
bitfld.byte 0x00 6. "CMD_EIE,Command Value Error Interrupt Enable Bit" "0: Command value interrupt is disabled,1: Command value interrupt is enabled"
newline
bitfld.byte 0x00 5. "EOL_EIE,End Of List Error Interrupt Enable Bit" "0: End Of List error interrupt is disabled,1: End Of List error interrupt is enabled"
bitfld.byte 0x00 3. "TRIG_EIE,Conversion Sequence Trigger Error Interrupt Enable Bit" "0: Conversion sequence trigger error interrupt..,1: Conversion sequence trigger error interrupt.."
newline
bitfld.byte 0x00 2. "RSTAR_EIE,Restart Request Error Interrupt Enable Bit" "0: Restart Request error interrupt is disabled,1: Restart Request error interrupt is enabled"
bitfld.byte 0x00 1. "LDOK_EIE,Load OK Error Interrupt Enable Bit" "0: Load OK error interrupt is disabled,1: Load OK error interrupt is enabled"
newline
bitfld.byte 0x00 0. "RA_EIE,Read Access Error Interrupt Enable Bit" "0: Read access error interrupt is disabled,1: Read access error interrupt is enabled"
group.byte 0x06++0x00
line.byte 0x00 "FLWCTL,ADC Conversion Flow Control Register"
bitfld.byte 0x00 7. "SEQA,Conversion Sequence Abort Event" "0: No conversion sequence abort request,1: Conversion sequence abort request"
bitfld.byte 0x00 6. "TRIG,Conversion Sequence Trigger Bit" "0: No conversion sequence trigger,1: Trigger to start conversion sequence"
newline
bitfld.byte 0x00 5. "RSTA,Restart Event (Restart from Top of Command Sequence List)" "0: Continue with commands from active Sequence..,1: Restart from top of active Sequence Command.."
bitfld.byte 0x00 4. "LDOK,Load OK for alternative Command Sequence List" "0: Load of alternative list done,1: Load alternative list"
group.byte 0x07++0x00
line.byte 0x00 "FMT,ADC Format Register"
bitfld.byte 0x00 7. "DJM,Result Register Data Justification" "0: Left justified data in the conversion result..,1: Right justified data in the conversion result.."
bitfld.byte 0x00 0.--2. "SRES,ADC Resolution Select" "0: 8-bit data,?,2: 10-bit data,?,4: 12-bit data,?..."
group.byte 0x08++0x00
line.byte 0x00 "CONIE1,ADC Conversion Interrupt Enable Register 1"
hexmask.byte 0x00 1.--7. 1. "CON_IE,Conversion Interrupt Enable Bits 7:1"
bitfld.byte 0x00 0. "EOL_IE,End Of List Interrupt Enable Bit" "0: End of list interrupt is disabled,1: End of list interrupt is enabled"
group.byte 0x09++0x00
line.byte 0x00 "CONIE0,ADC Conversion Interrupt Enable Register 0"
hexmask.byte 0x00 0.--7. 1. "CON_IE,Conversion Interrupt Enable Bits 15:8"
group.byte 0x0A++0x00
line.byte 0x00 "IF,ADC Interrupt Flag Register"
bitfld.byte 0x00 7. "SEQAD_IF,Conversion Sequence Abort Done Interrupt Flag" "0: No conversion sequence abort request occurred,1: A conversion sequence abort request occurred"
bitfld.byte 0x00 6. "CONIF_OIF,ADCCONIF Register Flags Overrun Interrupt Flag" "0: No ADCCONIF register flag overrun occurred,1: ADCCONIF register flag overrun occurred"
group.byte 0x0B++0x00
line.byte 0x00 "EIF,ADC Error Interrupt Flag Register"
rbitfld.byte 0x00 7. "WA_EIF,Write Access Error Interrupt Flag" "0: No write access error occurred,1: A write access error occurred"
rbitfld.byte 0x00 6. "CMD_EIF,Command Value Error Interrupt Flag" "0: Valid conversion command is loaded,1: Invalid conversion command is loaded"
newline
rbitfld.byte 0x00 5. "EOL_EIF,End Of List Error Interrupt Flag" "0: No End Of List error,1: End Of List command type 'is missing in.."
rbitfld.byte 0x00 3. "TRIG_EIF,Trigger Error Interrupt Flag" "0: No trigger error occurred,1: A trigger error occurred"
newline
bitfld.byte 0x00 2. "RSTAR_EIF,Restart Request Error Interrupt Flag" "0: No Restart request error situation occurred,1: Restart request error situation occurred"
bitfld.byte 0x00 1. "LDOK_EIF,Load OK Error Interrupt Flag" "0: No Load OK error situation occurred,1: Load OK error situation occurred"
newline
rbitfld.byte 0x00 0. "RA_EIF,Read Access Error Interrupt Flag" "0: No read access error occurred,1: A read access error occurred"
rgroup.byte 0x0C++0x00
line.byte 0x00 "IMDRI1,ADC Intermediate Result Information Register 1"
bitfld.byte 0x00 0.--5. "RIDX_IMD,RES_IDX Value At Intermediate Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.byte 0x0D++0x00
line.byte 0x00 "IMDRI0,ADC Intermediate Result Information Register 0"
bitfld.byte 0x00 7. "CSL_IMD,Active CSL At Intermediate Event" "0: CSL_0 is active (used) when a conversion..,1: CSL_1 is active (used) when a conversion.."
bitfld.byte 0x00 6. "RVL_IMD,Active RVL At Intermediate Event" "0: RVL_0 is active (used) when a conversion..,1: RVL_1 is active (used) when a conversion.."
group.byte 0x0E++0x00
line.byte 0x00 "CONIF1,ADC Conversion Interrupt Flag Register 1"
hexmask.byte 0x00 1.--7. 1. "CON_IF,Conversion Interrupt Flags 7:1"
bitfld.byte 0x00 0. "EOL_IF,End Of List Interrupt Flag" "0,1"
group.byte 0x0F++0x00
line.byte 0x00 "CONIF0,ADC Conversion Interrupt Flag Register 0"
hexmask.byte 0x00 0.--7. 1. "CON_IF,Conversion Interrupt Flags 15:8"
rgroup.byte 0x13++0x00
line.byte 0x00 "EOLRI,ADC End Of List Result Information Register"
bitfld.byte 0x00 7. "CSL_EOL,Active CSL When End Of List Command Type Executed" "0: CSL_0 is active when End Of List command type..,1: CSL_1 is active when End Of List command type.."
bitfld.byte 0x00 6. "RVL_EOL,Active RVL When End Of List Command Type Executed" "0: RVL_0 is active when End Of List command type..,1: RVL_1 is active when End Of List command type.."
group.byte 0x15++0x00
line.byte 0x00 "CMD2,ADC Command Register 2"
bitfld.byte 0x00 3.--7. "SMP,Sample Time Select Bits" "0: Sample time in 4 ADC clock cycles,1: Sample time in 5 ADC clock cycles,2: Sample time in 6 ADC clock cycles,3: Sample time in 7 ADC clock cycles,4: Sample time in 8 ADC clock cycles,5: Sample time in 9 ADC clock cycles,6: Sample time in 10 ADC clock cycles,7: Sample time in 11 ADC clock cycles,8: Sample time in 12 ADC clock cycles,9: Sample time in 13 ADC clock cycles,10: Sample time in 14 ADC clock cycles,11: Sample time in 15 ADC clock cycles,12: Sample time in 16 ADC clock cycles,13: Sample time in 17 ADC clock cycles,14: Sample time in 18 ADC clock cycles,15: Sample time in 19 ADC clock cycles,16: Sample time in 20 ADC clock cycles,17: Sample time in 21 ADC clock cycles,18: Sample time in 22 ADC clock cycles,19: Sample time in 23 ADC clock cycles,20: Sample time in 24 ADC clock cycles,?..."
group.byte 0x16++0x00
line.byte 0x00 "CMD1,ADC Command Register 1"
bitfld.byte 0x00 7. "VRH_SEL,Reference High Voltage Select Bit" "0: VRH_0 input is selected as high voltage..,1: VRH_1 input is selected as high voltage.."
bitfld.byte 0x00 6. "INTFLG_SEL,Reference Low Voltage Select Bit" "0: VRL_0 input is selected as low voltage..,1: VRL_1 input is selected as low voltage.."
newline
bitfld.byte 0x00 0.--5. "CH_SEL,ADC Input Channel Select Bits" "0: VRL_0/1,1: VRH_0/1,2: (VRH_0/1 + VRL_0/1) / 2,?,?,?,?,?,8: Internal_0 (ADC temperature sense),9: Internal_1,10: Internal_2,11: Internal_3,12: Internal_4,13: Internal_5,14: Internal_6,15: Internal_7,16: ANx,17: ANx,18: ANx,19: ANx,20: ANx,21: ANx,22: ANx,23: ANx,24: ANx,25: ANx,26: ANx,27: ANx,28: ANx,29: ANx,30: ANx,31: ANx,?..."
group.byte 0x17++0x00
line.byte 0x00 "CMD0,ADC Command Register 0"
bitfld.byte 0x00 6.--7. "CMD_SEL,Conversion Command Select Bits" "0: Normal conversion,1: End of sequence (wait for trigger to execute..,2: End of list (automatic wrap to top of CSL and..,3: End of list (wrap to top of CSL and: in.."
bitfld.byte 0x00 0.--3. "INTFLG_SEL,Conversion Interrupt Flag Select Bits" "0: No flag set,1: CON_IF[0x0001] is selected,2: CON_IF[0x0002] is selected,3: CON_IF[0x0004] is selected,4: CON_IF[0x0008] is selected,5: CON_IF[0x0010] is selected,6: CON_IF[0x0020] is selected,7: CON_IF[0x0040] is selected,8: CON_IF[0x0080] is selected,9: CON_IF[0x0100] is selected,10: CON_IF[0x0200] is selected,11: CON_IF[0x0400] is selected,12: CON_IF[0x0800] is selected,13: CON_IF[0x1000] is selected,14: CON_IF[0x2000] is selected,15: CON_IF[0x4000] is selected"
group.byte 0x1C++0x00
line.byte 0x00 "CBP2,ADC Command Base Pointer Register 2"
bitfld.byte 0x00 2.--7. "CMD_PTR,ADC Command Base Pointer Address [7:2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1D++0x00
line.byte 0x00 "CBP1,ADC Command Base Pointer Register 1"
hexmask.byte 0x00 0.--7. 1. "CMD_PTR,ADC Command Base Pointer Address [15:8]"
group.byte 0x1E++0x00
line.byte 0x00 "CBP0,ADC Command Base Pointer Register 0"
bitfld.byte 0x00 7. "CMD_PTR,ADC Command Base Pointer Address [23]" "0,1"
rgroup.byte 0x1F++0x00
line.byte 0x00 "CIDX,ADC Command Index Register"
bitfld.byte 0x00 0.--5. "CMD_IDX,ADC Command Index Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x20++0x00
line.byte 0x00 "RBP2,ADC Result Base Pointer Register 2"
bitfld.byte 0x00 2.--7. "RES_PTR,ADC Result Base Pointer Address [7:2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x21++0x00
line.byte 0x00 "RBP1,ADC Result Base Pointer Register 1"
hexmask.byte 0x00 0.--7. 1. "RES_PTR,ADC Result Base Pointer Address [15:8]"
group.byte 0x23++0x00
line.byte 0x00 "RIDX,ADC Result Index Register"
bitfld.byte 0x00 0.--5. "RES_IDX,ADC Result Index Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x26++0x00
line.byte 0x00 "CROFF1,ADC Command and Result Offset Register 1"
hexmask.byte 0x00 0.--6. 1. "CMDRES_OFF1,ADC Command and Result Offset Value"
rgroup.byte 0x27++0x00
line.byte 0x00 "CROFF0,ADC Command and Result Offset Register 0"
hexmask.byte 0x00 0.--6. 1. "CMDRES_OFF0,ADC Command and Result Offset Value"
tree.end
tree "CNC (Communication and Clamp Controller)"
base ad:0x4006E000
group.word 0x00++0x01
line.word 0x00 "CR,Control Register"
bitfld.word 0x00 15. "ZCDE,Zero-Crossing Detection Enable" "0: Zero-crossing detection is disabled,1: Zero-crossing detection is enabled"
bitfld.word 0x00 14. "ADANE,AD_IN Detection Enable" "0: Analog is disabled for AD_IN check,1: Analog is enabled for AD_IN check"
newline
bitfld.word 0x00 13. "OVIE,VREC Overvoltage Interrupt Enable" "0: VREC overvoltage interrupt is disabled,1: VREC overvoltage interrupt is enabled"
bitfld.word 0x00 12. "LVIE,VREC Low Voltage Interrupt Enable" "0: VREC low voltage interrupt is disabled,1: VREC low voltage interrupt is enabled"
newline
bitfld.word 0x00 10. "ADE,Adapter Switch Enable" "0: Adapter switch is disabled,1: Adapter switch is enabled"
bitfld.word 0x00 9. "SWADS,Software Adapter Switch" "0: Software does not assert the adapter switch,1: Software asserts the adapter switch"
newline
bitfld.word 0x00 8. "VADVDIE,AD_IN Voltage Valid state change Interrupt Enable" "0: AD_IN voltage valid state change interrupt is..,1: AD_IN voltage valid state change interrupt is.."
bitfld.word 0x00 7. "VRECDE,VREC Detection Enable" "0: Analog is disabled for VREC range check,1: Analog is enabled for VREC range check"
newline
bitfld.word 0x00 6. "EXTCLPDE,External Clamp Drive Enable" "0: External clamp drive is disabled,1: External clamp drive is enabled"
bitfld.word 0x00 5. "CLPDPE,Clamp Drive Port Enable" "0: The port for clamp drive is disabled,1: The port for clamp drive is enabled"
newline
bitfld.word 0x00 0. "SWCLPD,Software sets Clamp Drive" "0: Software does not set clamp drive directly,1: Clamp drive is set by software"
group.word 0x02++0x01
line.word 0x00 "ANACFG1,Analog Configuration Register 1"
bitfld.word 0x00 14.--15. "ZCDHYST,Hysteresis control for FSK Zero-Crossing Detection" "0: Hysteresis level 0,1: Hysteresis level 1,2: Hysteresis level 2,3: Hysteresis level 3"
bitfld.word 0x00 13. "AC1DIVOE,AC1 Divided Output Enable" "0: AC1 divided output is disabled,1: AC1 divided output is enabled"
newline
bitfld.word 0x00 11.--12. "VRECOVLVL,VREC Over Voltage Level Configuration" "0: Over-voltage level 0,1: Over-voltage level 1,2: Over-voltage level 2,3: Over-voltage level 3"
bitfld.word 0x00 3.--4. "VADOVTRM,Trim value set for the AD_IN overvoltage (VADOV5P5) detection" "0: Overvoltage threshold trim level 0,1: Overvoltage threshold trim level 1,2: Overvoltage threshold trim level 2,3: Overvoltage threshold trim level 3"
newline
bitfld.word 0x00 1.--2. "VADLVTRM,Trim value set for the AD_IN low voltage (VADOK4P5) detection" "0: Low voltage threshold trim level 0,1: Low voltage threshold trim level 1,2: Low voltage threshold trim level 2,3: Low voltage threshold trim level 3"
bitfld.word 0x00 0. "VADDIVOE,AD_IN Divided Output Enable" "0: The AD_IN divided output is disabled,1: The AD_IN divided output is enabled"
group.word 0x04++0x01
line.word 0x00 "ANACFG2,Analog Configuration Register 2"
bitfld.word 0x00 9. "VAOHY40,40 mV Hysteresis control for the comparator to compare AD_IN and VOUT" "0: There is no 40 mV hysteresis applied,1: 40 mV hysteresis is applied to the comparator"
bitfld.word 0x00 8. "VAOHY20,20 mV Hysteresis control for the comparator to compare AD_IN and VOUT" "0: There is no 20 mV hysteresis applied,1: 20 mV hysteresis is applied to the comparator"
newline
bitfld.word 0x00 7. "BIAE,Bias Enable for the CNC module" "0: The current bias is disabled,1: The current bias is enabled"
bitfld.word 0x00 6. "ACFLTE,AC Filter Enable" "0: The AC filter is disabled,1: The AC filter is enabled"
newline
bitfld.word 0x00 4.--5. "ACFLTC,AC Filter Configuration" "0: AC filter configuration 0,1: AC filter configuration 1,2: AC filter configuration 2,3: AC filter configuration 3"
bitfld.word 0x00 0.--3. "ACDIV,AC Divider selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x06++0x01
line.word 0x00 "STAS,Status Register"
rbitfld.word 0x00 7. "VRECLVS,VREC Low Voltage State" "0,1"
rbitfld.word 0x00 6. "VRECOVS,VREC Overvoltage State" "0,1"
newline
bitfld.word 0x00 5. "VRECLVF,VREC Low Voltage Flag" "0,1"
bitfld.word 0x00 4. "VRECOVF,VREC Overvoltage Flag" "0,1"
newline
bitfld.word 0x00 3. "VADCHGF,AD_IN Change status Flag" "0,1"
rbitfld.word 0x00 2. "VADOK4P5,AD_IN above 4.5 V state" "0,1"
newline
rbitfld.word 0x00 1. "VADOV5P5,AD_IN above 5.5 V state" "0,1"
rbitfld.word 0x00 0. "FSKO,FSK AC1/AC2 zero-crossing status" "0,1"
group.word 0x08++0x01
line.word 0x00 "VRECOE,VREC Overvoltage clamp drive Enable Register"
bitfld.word 0x00 0. "VRECOVE,VREC Overvoltage clamp drive Enable" "0: VREC overvoltage is not enabled for the clamp..,1: VREC overvoltage is enabled for the clamp drive"
group.word 0x0A++0x01
line.word 0x00 "VRECFLTC,VREC Filter Control Register"
hexmask.word 0x00 0.--15. 1. "CNT,Filter sample Count for VREC overvoltage or low voltage detection"
group.word 0x0C++0x01
line.word 0x00 "VADFLTC,AD_IN Filter Control Register"
hexmask.word 0x00 0.--15. 1. "CNT,Filter sample Count for AD_IN overvoltage or low voltage detection"
tree.end
tree "FSKDT (FSK Demodulation Timer)"
base ad:0x40034000
group.word 0x00++0x01
line.word 0x00 "CR,Control Register"
bitfld.word 0x00 15. "EN,FSK demodulation Enable" "0: FSK demodulation is disabled,1: FSK demodulation is enabled"
bitfld.word 0x00 13.--14. "NST,Number of Shift Times to measure" "0: 4 cycles of FSK are grouped in one phase,1: 8 cycles of FSK are grouped in one phase,2: 16 cycles of FSK are grouped in one phase,3: 32 cycles of FSK are grouped in one phase"
newline
bitfld.word 0x00 12. "SWRST,Software Reset" "0,1"
bitfld.word 0x00 3. "ERRIE,Interrupt Enable when Error happens" "0: Interrupt is not enabled when an error happens,1: Interrupt is enabled when an error happens"
newline
bitfld.word 0x00 2. "EOAMIE,End-Of-All phases Measurement Interrupt Enable" "0: End-of-all 3-phase measurement interrupt is..,1: End-of-all 3-phase measurement interrupt is.."
bitfld.word 0x00 1. "EOSMIE,End-Of-Single phase Measurement Interrupt Enable" "0: End-of-single phase measurement interrupt is..,1: End-of-single phase measurement interrupt is.."
newline
bitfld.word 0x00 0. "OPIE,Out-of-Period Interrupt Enable" "0: Out-of-Period Interrupt is disabled,1: Out-of-Period Interrupt is enabled"
group.word 0x02++0x01
line.word 0x00 "SR,Status Register"
bitfld.word 0x00 3. "ERRF,Error happens during measurement" "0: No error happens,1: Error happens and the software needs to check.."
bitfld.word 0x00 2. "EOAMF,End-Of-All Measurement Flag" "0: The 3-phase measurement is not completed,1: A complete 3-phase measurement finishes"
newline
bitfld.word 0x00 1. "EOSMF,End-Of-Single Measurement Flag" "0: The one-phase measurement is not completed,1: A complete one-phase measurement finishes"
bitfld.word 0x00 0. "OPF,Out-of-Period Flag" "0: The counter value hasn't the changes larger..,1: The counter value has significant change that.."
rgroup.word 0x04++0x01
line.word 0x00 "PH0,Phase0 counter value"
hexmask.word 0x00 0.--15. 1. "PH0CNTR,Counter values for Phase 0 measurement"
rgroup.word 0x06++0x01
line.word 0x00 "PH1,Phase1 counter value"
hexmask.word 0x00 0.--15. 1. "PH1CNTR,Counter values for Phase 1 measurement"
rgroup.word 0x08++0x01
line.word 0x00 "PH2,Phase2 counter value"
hexmask.word 0x00 0.--15. 1. "PH2CNTR,Counter values for phase 2 measurement"
rgroup.word 0x0A++0x01
line.word 0x00 "CURPOS,Current Position Register"
hexmask.word 0x00 0.--15. 1. "CURPOS,Current Position"
group.word 0x0C++0x01
line.word 0x00 "OPCTH,Out-of-Period Counter Threshold Register"
hexmask.word 0x00 0.--9. 1. "OPCTH,Out-of-Period Counter threshold"
group.word 0x0E++0x01
line.word 0x00 "ERRTH,Error Threshold Register"
hexmask.word 0x00 6.--15. 1. "HILMT,High Limitation"
bitfld.word 0x00 0.--5. "LOLMT,Low Limitation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x10++0x01
line.word 0x00 "DATA,Demodulation Data Register"
bitfld.word 0x00 15. "NBIE,New Bit decoding Interrupt Enable" "0: Interrupt is not enabled when decoding one..,1: Interrupt is enabled when decoding one new.."
bitfld.word 0x00 14. "WBNBIE,Whole Byte Bits decoding finish Interrupt Enable" "0: Interrupt is not enabled when decoding one..,1: Interrupt is enabled when decoding one whole.."
newline
bitfld.word 0x00 13. "BM,Package Byte Mode" "0: 11-bit mode,1: 8-bit mode"
hexmask.word 0x00 0.--10. 1. "DATA,The demodulated FSK data"
group.word 0x12++0x01
line.word 0x00 "DSR,Demodulation Data Status Register"
bitfld.word 0x00 15. "NBF,New Bit shift to DATA Flag" "0,1"
bitfld.word 0x00 14. "WBNF,New Whole Byte decoded Flag" "0,1"
newline
rbitfld.word 0x00 0.--3. "TCNTD,Total Count for bits that have been Decoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "FTM (FlexTimer Module)"
repeat 2. (list 0. 1.) (list ad:0x40038000 ad:0x4003A000)
tree "FTM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "SC,Status And Control"
rbitfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
newline
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: System clock,2: Fixed frequency clock,3: External clock"
newline
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
group.long 0x04++0x03
line.long 0x00 "CNT,Counter"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
group.long 0x08++0x03
line.long 0x00 "MOD,Modulo"
hexmask.long.word 0x00 0.--15. 1. "MOD,no description available"
group.long 0x0C++0x03
line.long 0x00 "C0SC,Channel (n) Status And Control"
rbitfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
newline
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
newline
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
group.long 0x14++0x03
line.long 0x00 "C1SC,Channel (n) Status And Control"
rbitfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
newline
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
newline
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
group.long 0x10++0x03
line.long 0x00 "C0V,Channel (n) Value"
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
group.long 0x18++0x03
line.long 0x00 "C1V,Channel (n) Value"
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
group.long 0x6C++0x03
line.long 0x00 "EXTTRIG,FTM External Trigger"
bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
tree.end
repeat.end
tree.end
tree "FTMRE (Flash Memory)"
base ad:0x40020000
group.byte 0x01++0x00
line.byte 0x00 "FCCOBIX,Flash CCOB Index Register"
bitfld.byte 0x00 0.--2. "CCOBIX,Common Command Register Index" "0,1,2,3,4,5,6,7"
rgroup.byte 0x02++0x00
line.byte 0x00 "FSEC,Flash Security Register"
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable Bits" "0: Disabled,1: Disabled,2: Enabled,3: Disabled"
bitfld.byte 0x00 0.--1. "SEC,Flash Security Bits" "0: Secured,1: Secured,2: Unsecured,3: Secured"
group.byte 0x03++0x00
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
rbitfld.byte 0x00 7. "FDIVLD,Clock Divider Loaded" "0: FCLKDIV register has not been written since..,1: FCLKDIV register has been written since the.."
bitfld.byte 0x00 6. "FDIVLCK,Clock Divider Locked" "0: FDIV field is open for writing,1: FDIV value is locked and cannot be changed"
newline
bitfld.byte 0x00 0.--5. "FDIV,Clock Divider Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x05++0x00
line.byte 0x00 "FSTAT,Flash Status Register"
bitfld.byte 0x00 7. "CCIF,Command Complete Interrupt Flag" "0: Flash command is in progress,1: Flash command has completed"
bitfld.byte 0x00 5. "ACCERR,Flash Access Error Flag" "0: No access error is detected,1: Access error is detected"
newline
bitfld.byte 0x00 4. "FPVIOL,Flash Protection Violation Flag" "0: No protection violation is detected,1: Protection violation is detected"
rbitfld.byte 0x00 3. "MGBUSY,Memory Controller Busy Flag" "0: Memory controller is idle,1: Memory controller is busy executing a flash.."
newline
rbitfld.byte 0x00 0.--1. "MGSTAT,Memory Controller Command Completion Status Flag" "0,1,2,3"
group.byte 0x07++0x00
line.byte 0x00 "FCNFG,Flash Configuration Register"
bitfld.byte 0x00 7. "CCIE,Command Complete Interrupt Enable" "0: Command complete interrupt is disabled,1: An interrupt will be requested whenever the.."
rbitfld.byte 0x00 5. "ERSAREQ,Debugger Mass Erase Request" "0: No request or request complete,1: Request to run the Erase All Blocks command.."
group.byte 0x08++0x00
line.byte 0x00 "FCCOBLO,Flash Common Command Object Register: Low"
hexmask.byte 0x00 0.--7. 1. "CCOB,Common Command Object Bit 7:0"
group.byte 0x09++0x00
line.byte 0x00 "FCCOBHI,Flash Common Command Object Register:High"
hexmask.byte 0x00 0.--7. 1. "CCOB,Common Command Object Bit 15:8"
group.byte 0x0B++0x00
line.byte 0x00 "FPROT,Flash Protection Register"
bitfld.byte 0x00 7. "FPOPEN,Flash Protection Operation Enable" "0: When FPOPEN is clear the FPLDIS field defines..,1: When FPOPEN is set the FPLDIS field enables.."
rbitfld.byte 0x00 6. "RNV6,Reserved Nonvolatile Bit" "0,1"
newline
rbitfld.byte 0x00 3.--5. "RNV,Reserved Nonvolatile Bit" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2. "FPLDIS,Flash Protection Lower Address Range Disable" "0: Protection/Unprotection enabled,1: Protection/Unprotection disabled"
newline
bitfld.byte 0x00 0.--1. "FPLS,Flash Protection Lower Address Size" "0,1,2,3"
rgroup.byte 0x0F++0x00
line.byte 0x00 "FOPT,Flash Option Register"
hexmask.byte 0x00 0.--7. 1. "NV,Nonvolatile Bits"
tree.end
tree "FTMRE_FLASHCONFIG (Flash configuration field)"
base ad:0x400
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
rgroup.byte ($2+0x00)++0x00
line.byte 0x00 "BACKKEY$1,Backdoor Comparison Key $1"
hexmask.byte 0x00 0.--7. 1. "KEY,Backdoor Comparison Key"
repeat.end
rgroup.byte 0x0D++0x00
line.byte 0x00 "FPROT,Non-volatile P-Flash Protection Register"
bitfld.byte 0x00 7. "FPOPEN,no description available" "0: FPHDIS and FPLDIS bits define unprotected..,1: FPHDIS and FPLDIS bits enable protection for.."
bitfld.byte 0x00 5. "FPHDIS,no description available" "0: Protection/Unprotection enabled,1: Protection/Unprotection disabled"
bitfld.byte 0x00 3.--4. "FPHS,no description available" "0: Address range,1: Address range,2: Address range,3: Address range"
newline
bitfld.byte 0x00 2. "FPLDIS,no description available" "0: Protection/Unprotection enabled,1: Protection/Unprotection disabled"
bitfld.byte 0x00 0.--1. "FPLS,no description available" "0: Address range,1: Address range,2: Address range,3: Address range"
rgroup.byte 0x0E++0x00
line.byte 0x00 "FSEC,Non-volatile Flash Security Register"
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable" "?,?,2: Backdoor key access enabled,3: Backdoor key access disabled"
bitfld.byte 0x00 0.--1. "SEC,Flash Security" "?,?,2: MCU security status is unsecure,3: MCU security status is secure"
rgroup.byte 0x0F++0x00
line.byte 0x00 "FOPT,Non-volatile Flash Option Register"
tree.end
tree "GPIOA (General Purpose Input/Output)"
base ad:0x4000F000
group.long 0x00++0x03
line.long 0x00 "PDOR,Port Data Output Register"
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
wgroup.long 0x04++0x03
line.long 0x00 "PSOR,Port Set Output Register"
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
wgroup.long 0x08++0x03
line.long 0x00 "PCOR,Port Clear Output Register"
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
wgroup.long 0x0C++0x03
line.long 0x00 "PTOR,Port Toggle Output Register"
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
rgroup.long 0x10++0x03
line.long 0x00 "PDIR,Port Data Input Register"
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
group.long 0x14++0x03
line.long 0x00 "PDDR,Port Data Direction Register"
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
group.long 0x18++0x03
line.long 0x00 "PIDR,Port Input Disable Register"
hexmask.long 0x00 0.--31. 1. "PID,Port Input Disable"
tree.end
tree "I2C0 (Inter-Integrated Circuit)"
base ad:0x40066000
group.byte 0x00++0x00
line.byte 0x00 "A1,I2C Address Register 1"
hexmask.byte 0x00 1.--7. 1. "AD,Address"
group.byte 0x01++0x00
line.byte 0x00 "F,I2C Frequency Divider register"
bitfld.byte 0x00 6.--7. "MULT,Multiplier Factor" "0: mul = 1,1: mul = 2,2: mul = 4,?..."
bitfld.byte 0x00 0.--5. "ICR,ClockRate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x02++0x00
line.byte 0x00 "C1,I2C Control Register 1"
bitfld.byte 0x00 7. "IICEN,I2C Enable" "0: Disabled,1: Enabled"
bitfld.byte 0x00 6. "IICIE,I2C Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.byte 0x00 5. "MST,Master Mode Select" "0: Slave mode,1: Master mode"
bitfld.byte 0x00 4. "TX,Transmit Mode Select" "0: Receive,1: Transmit"
newline
bitfld.byte 0x00 3. "TXAK,Transmit Acknowledge Enable" "0: An acknowledge signal is sent to the bus on..,1: No acknowledge signal is sent to the bus on.."
bitfld.byte 0x00 2. "RSTA,Repeat START" "0,1"
newline
bitfld.byte 0x00 1. "WUEN,Wakeup Enable" "0: Normal operation,1: Enables the wakeup function in low power mode"
group.byte 0x03++0x00
line.byte 0x00 "S,I2C Status register"
rbitfld.byte 0x00 7. "TCF,Transfer Complete Flag" "0: Transfer in progress,1: Transfer complete"
bitfld.byte 0x00 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave"
newline
rbitfld.byte 0x00 5. "BUSY,Bus Busy" "0: Bus is idle,1: Bus is busy"
bitfld.byte 0x00 4. "ARBL,Arbitration Lost" "0: Standard bus operation,1: Loss of arbitration"
newline
bitfld.byte 0x00 3. "RAM,Range Address Match" "0: Not addressed,1: Addressed as a slave"
rbitfld.byte 0x00 2. "SRW,Slave Read/" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave"
newline
bitfld.byte 0x00 1. "IICIF,Interrupt Flag" "0: No interrupt pending,1: Interrupt pending"
rbitfld.byte 0x00 0. "RXAK,Receive Acknowledge" "0: Acknowledge signal was received after the..,1: No acknowledge signal detected"
group.byte 0x04++0x00
line.byte 0x00 "D,I2C Data I/O register"
hexmask.byte 0x00 0.--7. 1. "DATA,Data"
group.byte 0x05++0x00
line.byte 0x00 "C2,I2C Control Register 2"
bitfld.byte 0x00 7. "GCAEN,General Call Address Enable" "0: Disabled,1: Enabled"
bitfld.byte 0x00 6. "ADEXT,Address Extension" "0: 7-bit address scheme,1: 10-bit address scheme"
newline
bitfld.byte 0x00 4. "SBRC,Slave Baud Rate Control" "0: The slave baud rate follows the master baud..,1: Slave baud rate is independent of the master.."
bitfld.byte 0x00 3. "RMEN,Range Address Matching Enable" "0: Range mode disabled,1: Range mode enabled"
newline
bitfld.byte 0x00 0.--2. "AD,Slave Address" "0,1,2,3,4,5,6,7"
group.byte 0x06++0x00
line.byte 0x00 "FLT,I2C Programmable Input Glitch Filter Register"
bitfld.byte 0x00 7. "SHEN,Stop Hold Enable" "0: Stop holdoff is disabled,1: Stop holdoff is enabled"
bitfld.byte 0x00 6. "STOPF,I2C Bus Stop Detect Flag" "0: No stop happens on I2C bus,1: Stop detected on I2C bus"
newline
bitfld.byte 0x00 5. "SSIE,I2C Bus Stop or Start Interrupt Enable" "0: Stop or start detection interrupt is disabled,1: Stop or start detection interrupt is enabled"
bitfld.byte 0x00 4. "STARTF,I2C Bus Start Detect Flag" "0: No start happens on I2C bus,1: Start detected on I2C bus"
newline
bitfld.byte 0x00 0.--3. "FLT,I2C Programmable Filter Factor" "0: No filter/bypass,?..."
group.byte 0x07++0x00
line.byte 0x00 "RA,I2C Range Address register"
hexmask.byte 0x00 1.--7. 1. "RAD,Range Slave Address"
group.byte 0x08++0x00
line.byte 0x00 "SMB,I2C SMBus Control and Status register"
bitfld.byte 0x00 7. "FACK,Fast NACK/ACK Enable" "0: An ACK or NACK is sent on the following..,1: Writing 0 to TXAK after receiving a data byte.."
bitfld.byte 0x00 6. "ALERTEN,SMBus Alert Response Address Enable" "0: SMBus alert response address matching is..,1: SMBus alert response address matching is.."
newline
bitfld.byte 0x00 5. "SIICAEN,Second I2C Address Enable" "0: I2C address register 2 matching is disabled,1: I2C address register 2 matching is enabled"
bitfld.byte 0x00 4. "TCKSEL,Timeout Counter Clock Select" "0: Timeout counter counts at the frequency of..,1: Timeout counter counts at the frequency of.."
newline
bitfld.byte 0x00 3. "SLTF,SCL Low Timeout Flag" "0: No low timeout occurs,1: Low timeout occurs"
rbitfld.byte 0x00 2. "SHTF1,SCL High Timeout Flag 1" "0: No SCL high and SDA high timeout occurs,1: SCL high and SDA high timeout occurs"
newline
bitfld.byte 0x00 1. "SHTF2,SCL High Timeout Flag 2" "0: No SCL high and SDA low timeout occurs,1: SCL high and SDA low timeout occurs"
bitfld.byte 0x00 0. "SHTF2IE,SHTF2 Interrupt Enable" "0: SHTF2 interrupt is disabled,1: SHTF2 interrupt is enabled"
group.byte 0x09++0x00
line.byte 0x00 "A2,I2C Address Register 2"
hexmask.byte 0x00 1.--7. 1. "SAD,SMBus Address"
group.byte 0x0A++0x00
line.byte 0x00 "SLTH,I2C SCL Low Timeout Register High"
hexmask.byte 0x00 0.--7. 1. "SSLT,SSLT[15:8]"
group.byte 0x0B++0x00
line.byte 0x00 "SLTL,I2C SCL Low Timeout Register Low"
hexmask.byte 0x00 0.--7. 1. "SSLT,SSLT[7:0]"
tree.end
tree "ICS (Clock management)"
base ad:0x40064000
group.byte 0x00++0x00
line.byte 0x00 "C1,ICS Control Register 1"
bitfld.byte 0x00 6.--7. "CLKS,Clock Source Select" "0: Output of FLL is selected,1: Internal reference clock is selected,2: External reference clock is selected,3: Reserved defaults to 00"
bitfld.byte 0x00 3.--5. "RDIV,Reference Divider" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 2. "IREFS,Internal Reference Select" "0: External reference clock is selected,1: Internal reference clock is selected"
bitfld.byte 0x00 1. "IRCLKEN,Internal Reference Clock Enable" "0: ICSIRCLK is inactive,1: ICSIRCLK is active"
newline
bitfld.byte 0x00 0. "IREFSTEN,Internal Reference Stop Enable" "0: Internal reference clock is disabled in Stop..,1: Internal reference clock stays enabled in.."
group.byte 0x01++0x00
line.byte 0x00 "C2,ICS Control Register 2"
bitfld.byte 0x00 5.--7. "BDIV,Bus Frequency Divider" "0: Encoding 0-Divides the selected clock by 1,1: Encoding 1-Divides the selected clock by 2..,2: Encoding 2-Divides the selected clock by 4,3: Encoding 3-Divides the selected clock by 8,4: Encoding 4-Divides the selected clock by 16,5: Encoding 5-Divides the selected clock by 32,6: Encoding 6-Divides the selected clock by 64,7: Encoding 7-Divides the selected clock by 128"
bitfld.byte 0x00 4. "LP,Low Power Select" "0: FLL is not disabled in bypass mode,1: FLL is disabled in bypass modes unless debug.."
group.byte 0x02++0x00
line.byte 0x00 "C3,ICS Control Register 3"
hexmask.byte 0x00 0.--7. 1. "SCTRIM,Slow Internal Reference Clock Trim Setting"
group.byte 0x03++0x00
line.byte 0x00 "C4,ICS Control Register 4"
bitfld.byte 0x00 7. "LOLIE,Loss of Lock Interrupt" "0: No request on loss of lock,1: Generates an interrupt request on loss of lock"
bitfld.byte 0x00 5. "CME,Clock Monitor Enable" "0: Clock monitor is disabled,1: Generates a reset request on loss of external.."
newline
bitfld.byte 0x00 0. "SCFTRIM,Slow Internal Reference Clock Fine Trim" "0,1"
group.byte 0x04++0x00
line.byte 0x00 "S,ICS Status Register"
bitfld.byte 0x00 7. "LOLS,Loss of Lock Status" "0: FLL has not lost lock since LOLS was last..,1: FLL has lost lock since LOLS was last cleared"
rbitfld.byte 0x00 6. "LOCK,Lock Status" "0: FLL is currently unlocked,1: FLL is currently locked"
newline
rbitfld.byte 0x00 4. "IREFST,Internal Reference Status" "0: Source of reference clock is external clock,1: Source of reference clock is internal clock"
rbitfld.byte 0x00 2.--3. "CLKST,Clock Mode Status" "0: Output of FLL is selected,1: FLL Bypassed internal reference clock is..,2: FLL Bypassed external reference clock is..,?..."
tree.end
tree "IRQ (Interrupt)"
base ad:0x40031000
group.byte 0x00++0x00
line.byte 0x00 "SC,Interrupt Pin Request Status and Control Register"
bitfld.byte 0x00 6. "IRQPDD,Interrupt Request (IRQ) Pull Device Disable" "0: IRQ pull device enabled if IRQPE = 1,1: IRQ pull device disabled if IRQPE = 1"
bitfld.byte 0x00 5. "IRQEDG,Interrupt Request (IRQ) Edge Select" "0: IRQ is falling-edge or falling-edge/low-level..,1: IRQ is rising-edge or rising-edge/high-level.."
newline
bitfld.byte 0x00 4. "IRQPE,IRQ Pin Enable" "0: IRQ pin function is disabled,1: IRQ pin function is enabled"
rbitfld.byte 0x00 3. "IRQF,IRQ Flag" "0: No IRQ request,1: IRQ event is detected"
newline
bitfld.byte 0x00 2. "IRQACK,IRQ Acknowledge" "0,1"
bitfld.byte 0x00 1. "IRQIE,IRQ Interrupt Enable" "0: Interrupt request when IRQF set is disabled..,1: Interrupt requested whenever IRQF = 1"
newline
bitfld.byte 0x00 0. "IRQMOD,IRQ Detection Mode" "0: IRQ event is detected only on falling/rising..,1: IRQ event is detected on falling/rising edges.."
tree.end
tree "LDO (Low Dropout Regulator)"
base ad:0x40070000
group.word 0x00++0x01
line.word 0x00 "CR,Control Register"
bitfld.word 0x00 15. "LDOEN,LDO controller Enable" "0: LDO controller is disabled,1: LDO controller is enabled"
bitfld.word 0x00 14. "CPEN,Charge Pump Enable" "0: Charge pump is disabled,1: Charge pump is enabled"
newline
bitfld.word 0x00 13. "LDOREGEN,LDO internal Regulator Enable" "0: LDO regulator is disabled,1: LDO regulator is enabled"
bitfld.word 0x00 10.--12. "OCTHLD,Overcurrent Threshold Selection" "0: Level 0,1: Level 1,2: Level 2,3: Level 3,4: Level 4,5: Level 5,6: Level 6,7: Level 7"
newline
bitfld.word 0x00 9. "BASHDN,Block the Automatic Shutdown" "0: Allows the automatically shutting down the..,1: Blocks the automatic shutdown function from.."
bitfld.word 0x00 8. "OCDTE,Overcurrent Detection Enable" "0: Overcurrent detection is disabled,1: Overcurrent detection is enabled"
newline
bitfld.word 0x00 6.--7. "OVTHLD,Overvoltage Threshold Selection" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
bitfld.word 0x00 3.--4. "CPCLKPS,Prescaler bits of the Clock to be divided for Charge Pump" "0: The division factor is 4,1: The division factor is 8,2: The division factor is 16,3: The division factor is 32"
newline
bitfld.word 0x00 2. "OCIE,Overcurrent Interrupt Enable" "0: No interrupt gets asserted when the current..,1: An interrupt gets asserted when the current.."
bitfld.word 0x00 1. "OVIE,Overvoltage Interrupt Enable" "0: No interrupt gets asserted when the voltage..,1: An interrupt gets asserted when the voltage.."
newline
bitfld.word 0x00 0. "OVDTE,Overvoltage Detection Enable" "0: Overvoltage detection is disabled,1: Overvoltage detection is enabled"
group.word 0x02++0x01
line.word 0x00 "SR,Status Register"
rbitfld.word 0x00 15. "CPOKF,Charge Pump OK status Flag" "0: Indicates the internal charge pump is not in..,1: Indicates the internal charge pump is OK"
rbitfld.word 0x00 3. "OCST,Overcurrent Status" "0,1"
newline
rbitfld.word 0x00 2. "OVST,Overvoltage Status" "0,1"
bitfld.word 0x00 1. "OCF,Current loop Overcurrent Flag" "0: The current loop output is not over the..,1: The current loop output is over the current.."
newline
bitfld.word 0x00 0. "OVF,Voltage loop Overvoltage Flag" "0: The voltage loop output is not over the..,1: The voltage loop output is over the voltage.."
group.word 0x04++0x01
line.word 0x00 "CTRM,Current Trim Register"
bitfld.word 0x00 14.--15. "CSHTM,Current Sensor High-side offset Trim" "0: 0 mV,1: 3 mV,2: 6 mV,3: 9 mV"
bitfld.word 0x00 11.--12. "CSLTM,Current Sensor Low-side offset Trim" "0: 0 mV,1: 3 mV,2: 6 mV,3: 9 mV"
newline
hexmask.word 0x00 0.--8. 1. "CTRM,Current loop configuration"
group.word 0x06++0x01
line.word 0x00 "VTRM,Voltage Trim Register"
hexmask.word 0x00 0.--8. 1. "VTRM,Voltage loop configuration"
group.word 0x08++0x01
line.word 0x00 "OCFILT,Overcurrent Filter Register"
hexmask.word 0x00 0.--15. 1. "CNT,Filter sample count for the overcurrent detection"
group.word 0x0A++0x01
line.word 0x00 "OVFILT,Overvoltage Filter Register"
hexmask.word 0x00 0.--15. 1. "CNT,Filter sample count for the overvoltage detection"
group.word 0x0C++0x01
line.word 0x00 "SCR,Shutdown Control Register"
bitfld.word 0x00 2. "EXTSDE,External Shutdown Enable" "0: External shutdown request is disabled to turn..,1: External shutdown request is enabled to turn.."
bitfld.word 0x00 1. "OVASDE,no description available" "0: Voltage loop and current loop are not..,1: Voltage loop and current loop are.."
newline
bitfld.word 0x00 0. "OCASDE,no description available" "0: Voltage loop and current loop are not..,1: Voltage loop and current loop are.."
tree.end
tree "MCM (Core Platform Miscellaneous Control Module)"
base ad:0xF0003000
rgroup.word 0x08++0x01
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
rgroup.word 0x0A++0x01
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
group.long 0x0C++0x03
line.long 0x00 "PLACR,Platform Control Register"
bitfld.long 0x00 16. "ESFC,Enable Stalling Flash Controller" "0: Disable stalling flash controller when flash..,1: Enable stalling flash controller when flash.."
bitfld.long 0x00 15. "DFCS,Disable Flash Controller Speculation" "0: Enable flash controller speculation,1: Disable flash controller speculation"
bitfld.long 0x00 14. "EFDS,Enable Flash Data Speculation" "0: Disable flash data speculation,1: Enable flash data speculation"
newline
bitfld.long 0x00 9. "ARB,Arbitration select" "0: Fixed-priority arbitration for the crossbar..,1: Round-robin arbitration for the crossbar.."
tree.end
tree "OSC (Oscillator)"
base ad:0x40065000
group.byte 0x00++0x00
line.byte 0x00 "CR,OSC Control Register"
bitfld.byte 0x00 7. "OSCEN,OSC Enable" "0: OSC module is disabled,1: OSC module is enabled"
bitfld.byte 0x00 5. "OSCSTEN,OSC Enable in Stop mode" "0: OSC clock is disabled in Stop mode,1: OSC clock stays enabled in Stop mode"
bitfld.byte 0x00 4. "OSCOS,OSC Output Select" "0: External clock source from EXTAL pin is..,1: Oscillator clock source is selected"
newline
bitfld.byte 0x00 2. "RANGE,Frequency Range Select" "0: Low frequency range of 32 kHz,1: High frequency range of 4-24 MHz"
bitfld.byte 0x00 1. "HGO,High Gain Oscillator Select" "0: Low-power mode,1: High-gain mode"
rbitfld.byte 0x00 0. "OSCINIT,OSC Initialization" "0: Oscillator initialization is not complete,1: Oscillator initialization is completed"
tree.end
tree "PGA (Programmable Gain Amplifier)"
base ad:0x40071000
group.byte 0x00++0x00
line.byte 0x00 "CTRL,Control Register"
bitfld.byte 0x00 1.--2. "GAIN,Programmable Gain" "0: The gain is 8,1: The gain is 10,2: The gain is 15,3: The gain is 20"
bitfld.byte 0x00 0. "PGAEN,Programmable Gain Amplifier Enable" "0: Disables the programmable amplifier,1: Enables the programmable amplifier"
tree.end
tree "PIT (Periodic Interrupt Timer)"
base ad:0x40037000
group.long 0x00++0x03
line.long 0x00 "MCR,PIT Module Control Register"
bitfld.long 0x00 1. "MDIS,Module Disable - (PIT section)" "0: Clock for standard PIT timers is enabled,1: Clock for standard PIT timers is disabled"
bitfld.long 0x00 0. "FRZ,Freeze" "0: Timers continue to run in Debug mode,1: Timers are stopped in Debug mode"
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
group.long ($2+0x100)++0x03
line.long 0x00 "LDVAL$1,Timer Load Value Register"
hexmask.long 0x00 0.--31. 1. "TSV,Timer Start Value"
repeat.end
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
rgroup.long ($2+0x104)++0x03
line.long 0x00 "CVAL$1,Current Timer Value Register"
hexmask.long 0x00 0.--31. 1. "TVL,Current Timer Value"
repeat.end
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
group.long ($2+0x108)++0x03
line.long 0x00 "TCTRL$1,Timer Control Register"
bitfld.long 0x00 2. "CHN,Chain Mode" "0: Timer is not chained,1: Timer is chained to previous timer"
bitfld.long 0x00 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from Timer n are disabled,1: Interrupt will be requested whenever TIF is set"
bitfld.long 0x00 0. "TEN,Timer Enable" "0: Timer n is disabled,1: Timer n is enabled"
repeat.end
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
group.long ($2+0x10C)++0x03
line.long 0x00 "TFLG$1,Timer Flag Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag" "0: Timeout has not yet occurred,1: Timeout has occurred"
repeat.end
tree.end
tree "PMC (Power Management Controller)"
base ad:0x4007D000
group.byte 0x00++0x00
line.byte 0x00 "CTRL,Control Register"
bitfld.byte 0x00 7. "GWREN,General Write protection Enable" "0: The general write protection is disabled,1: The general write protection is enabled"
bitfld.byte 0x00 2. "VREFDN,VREFH Down" "0: Enables the VREFH regulator,1: Disables the VREFH regulator"
newline
bitfld.byte 0x00 1. "RC20KENSTP,20 kHz RC oscillator Enable in Stop mode" "0: Disables 20 kHz RC oscillator in the Stop mode,1: Enables 20 kHz RC oscillator in the Stop mode"
group.byte 0x01++0x00
line.byte 0x00 "RST,Reset Flags Register"
bitfld.byte 0x00 6. "PORF,Power-on Reset Flag" "0: POR does not occur,1: POR occurs"
bitfld.byte 0x00 5. "LVRF,Low Voltage Reset (LVR) Flag" "0: Low voltage reset does not occur,1: Low voltage reset occurs"
group.byte 0x02++0x00
line.byte 0x00 "TPCTRLSTAT,Temperature Control and Status Register"
bitfld.byte 0x00 4. "SWON,Switch On" "0: Selects the temperature sensor output,1: Selects the bandgap output"
bitfld.byte 0x00 3. "TEMPEN,Temperature sensor Enable" "0: Disables the temperature sensor,1: Enables the temperature sensor"
newline
rbitfld.byte 0x00 2. "HTDS,High Temperature Detection Status" "0: Junction temperature is below the alert level,1: Junction temperature is above the alert level"
bitfld.byte 0x00 1. "HTIE,High Temperature Interrupt Enable" "0: Disables the high temperature interrupt,1: Enables the high temperature interrupt"
newline
bitfld.byte 0x00 0. "HTIF,High Temperature Interrupt Flag" "0: No change in the HTDS bit,1: The HTDS bit changes"
group.byte 0x03++0x00
line.byte 0x00 "TPTM,Temperature Offset Step Trim Register"
bitfld.byte 0x00 7. "TRMTPEN,Temperature offset Trim Enable" "0: The temperature sensor offset is disabled,1: The temperature sense offset is enabled"
bitfld.byte 0x00 0.--3. "TOT,Temperature Offset step Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x04++0x00
line.byte 0x00 "RC20KTRM,RC Oscillator Offset Step Trim Register"
bitfld.byte 0x00 0.--5. "OSCOT,RC Oscillator Offset step Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x05++0x00
line.byte 0x00 "LVCTLSTAT1,Low Voltage Control and Status Register 1 (system 5 V)"
rbitfld.byte 0x00 4. "SLVWF,Low Voltage Warning (LVW) Flag for VDDX" "0: Low voltage warning event is not detected,1: Low voltage warning event is detected"
bitfld.byte 0x00 3. "SLVWACK,Low Voltage Warning Acknowledge" "0,1"
newline
rbitfld.byte 0x00 2. "SLVWIE,Low Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when SLVWF = 1"
rbitfld.byte 0x00 1. "SLVWSEL,Low Voltage Warning Selection" "0: 4.2 V LVW threshold selected,1: 3.7 V LVW threshold selected"
group.byte 0x06++0x00
line.byte 0x00 "LVCTLSTAT2,Low Voltage Control and Status Register 2 (VREFH)"
rbitfld.byte 0x00 4. "RLVWF,Low Voltage Warning Flag for VREFH" "0: Low voltage warning event is not detected,1: Low voltage warning event is detected"
bitfld.byte 0x00 3. "RLVWACK,Low Voltage Warning Acknowledge" "0,1"
newline
rbitfld.byte 0x00 2. "RLVWIE,Low Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when RLVWF = 1"
group.byte 0x07++0x00
line.byte 0x00 "VREFHCFG,VREFH Configuration Register"
bitfld.byte 0x00 0.--5. "T5V,Trim 5 V reference voltage for ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x08++0x00
line.byte 0x00 "VREFHLVW,VREFH Low Voltage Warning (LVW) Configuration Register"
bitfld.byte 0x00 0.--1. "LVWCFG,VREFH LVW reference voltage Configuration" "0: 3.6 V LVW threshold,1: 3.7 V LVW threshold,2: 4.1 V LVW threshold,3: 4.4 V LVW threshold"
rgroup.byte 0x09++0x00
line.byte 0x00 "STAT,Status Register"
bitfld.byte 0x00 2. "HBGRDY,High-accuracy Bandgap Ready flag" "0: Below 0.8 V this bit is cleared,1: Above 1 V this bit is asserted"
bitfld.byte 0x00 0. "VREFRDY,VREFH Ready flag" "0: Below 3.0 V this bit is cleared,1: Above 3.45 V this bit is asserted"
tree.end
tree "PORT (Port control and interrupts)"
base ad:0x40049000
group.long 0x00++0x03
line.long 0x00 "IOFLT0,Port Filter Control Register 0"
bitfld.long 0x00 29.--31. "FLTDIV3,Filter Division Set 3" "0: LPOCLK,1: LPOCLK/2,2: LPOCLK/4,3: LPOCLK/8,4: LPOCLK/16,5: LPOCLK/32,6: LPOCLK/64,7: LPOCLK/128"
bitfld.long 0x00 26.--28. "FLTDIV2,Filter Division Set 2" "0: BUSCLK/32,1: BUSCLK/64,2: BUSCLK/128,3: BUSCLK/256,4: BUSCLK/512,5: BUSCLK/1024,6: BUSCLK/2048,7: BUSCLK/4096"
newline
bitfld.long 0x00 24.--25. "FLTDIV1,Filter Division Set 1" "0: BUSCLK/2,1: BUSCLK/4,2: BUSCLK/8,3: BUSCLK/16"
bitfld.long 0x00 0.--1. "FLTRST,Filter Selection for Input from RESET" "0: No filter,1: Selects FLTDIV1 and will switch to FLTDIV3 in..,2: Selects FLTDIV2 and will switch to FLTDIV3 in..,3: FLTDIV3"
group.long 0x04++0x03
line.long 0x00 "PUE0,Port Pullup Enable Register 0"
bitfld.long 0x00 12. "PTBPE4,Pull Enable for Port B Bit 4" "0: Pullup is disabled for port B bit 4,1: Pullup is enabled for port B bit 4"
bitfld.long 0x00 11. "PTBPE3,Pull Enable for Port B Bit 3" "0: Pullup is disabled for port B bit 3,1: Pullup is enabled for port B bit 3"
newline
bitfld.long 0x00 10. "PTBPE2,Pull Enable for Port B Bit 2" "0: Pullup is disabled for port B bit 2,1: Pullup is enabled for port B bit 2"
bitfld.long 0x00 9. "PTBPE1,Pull Enable for Port B Bit 1" "0: Pullup is disabled for port B bit 1,1: Pullup is enabled for port B bit 1"
newline
bitfld.long 0x00 8. "PTBPE0,Pull Enable for Port B Bit 0" "0: Pullup is disabled for port B bit 0,1: Pullup is enabled for port B bit 0"
bitfld.long 0x00 7. "PTAPE7,Pull Enable for Port A Bit 7" "0: Pullup is disabled for port A bit 7,1: Pullup is enabled for port A bit 7"
newline
bitfld.long 0x00 6. "PTAPE6,Pull Enable for Port A Bit 6" "0: Pullup is disabled for port A bit 6,1: Pullup is enabled for port A bit 6"
bitfld.long 0x00 5. "PTAPE5,Pull Enable for Port A Bit 5" "0: Pullup is disabled for port A bit 5,1: Pullup is enabled for port A bit 5"
newline
bitfld.long 0x00 4. "PTAPE4,Pull Enable for Port A Bit 4" "0: Pullup is disabled for port A bit 4,1: Pullup is enabled for port A bit 4"
bitfld.long 0x00 3. "PTAPE3,Pull Enable for Port A Bit 3" "0: Pullup is disabled for port A bit 3,1: Pullup is enabled for port A bit 3"
newline
bitfld.long 0x00 2. "PTAPE2,Pull Enable for Port A Bit 2" "0: Pullup is disabled for port A bit 2,1: Pullup is enabled for port A bit 2"
bitfld.long 0x00 1. "PTAPE1,Pull Enable for Port A Bit 1" "0: Pullup is disabled for port A bit 1,1: Pullup is enabled for port A bit 1"
newline
bitfld.long 0x00 0. "PTAPE0,Pull Enable for Port A Bit 0" "0: Pullup is disabled for port A bit 0,1: Pullup is enabled for port A bit 0"
tree.end
tree "RTC (Real-time Counter)"
base ad:0x4003D000
group.long 0x00++0x03
line.long 0x00 "SC,RTC Status and Control Register"
bitfld.long 0x00 14.--15. "RTCLKS,Real-Time Clock Source Select" "0: External clock source,1: Real-time clock source is 20 kHz (LPOCLK),2: Internal reference clock (ICSIRCLK),3: Bus clock"
bitfld.long 0x00 8.--10. "RTCPS,Real-Time Clock Prescaler Select" "0: 000,1: If RTCLKS = x0 it is 1 if RTCLKS = x1 it is 128,2: If RTCLKS = x0 it is 2 if RTCLKS = x1 it is 256,3: If RTCLKS = x0 it is 4 if RTCLKS = x1 it is 512,4: If RTCLKS = x0 it is 8 if RTCLKS = x1 it is..,5: If RTCLKS = x0 it is 16 if RTCLKS = x1 it is..,6: If RTCLKS = x0 it is 32 if RTCLKS = x1 it is..,7: If RTCLKS = x0 it is 64 if RTCLKS = x1 it is.."
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bitfld.long 0x00 7. "RTIF,Real-Time Interrupt Flag" "0: RTC counter has not reached the value in the..,1: RTC counter has reached the value in the RTC.."
bitfld.long 0x00 6. "RTIE,Real-Time Interrupt Enable" "0: Real-time interrupt requests are disabled,1: Real-time interrupt requests are enabled"
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bitfld.long 0x00 4. "RTCO,Real-Time Counter Output" "0: Real-time counter output disabled,1: Real-time counter output enabled"
group.long 0x04++0x03
line.long 0x00 "MOD,RTC Modulo Register"
hexmask.long.word 0x00 0.--15. 1. "MOD,RTC Modulo"
rgroup.long 0x08++0x03
line.long 0x00 "CNT,RTC Counter Register"
hexmask.long.word 0x00 0.--15. 1. "CNT,RTC Count"
tree.end
tree "SIM (System Integration Module)"
base ad:0x40048000
rgroup.long 0x00++0x03
line.long 0x00 "SRSID,System Reset Status and ID Register"
bitfld.long 0x00 28.--31. "FAMID,Wireless power controller Family ID" "0: Wireless power receiver (WPR),1: Wireless charger receiver (WCR),?,?,?,?,?,?,8: Wireless charger transmitter (WCT),?..."
bitfld.long 0x00 24.--27. "SUBFAMID,Wireless power controller Sub-family power ID" "0: 0000,1: 0001,2: 0010,?..."
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bitfld.long 0x00 13. "SACKERR,Stop Mode Acknowledge Error Reset" "0: Reset is not caused by peripheral failure to..,1: Reset is caused by peripheral failure to.."
bitfld.long 0x00 11. "MDMAP,MDM-AP System Reset Request" "0: Reset is not caused by the host debugger..,1: Reset is caused by the host debugger system.."
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bitfld.long 0x00 10. "SW,Software" "0: Reset is not caused by software setting of..,1: Reset caused by software setting of the.."
bitfld.long 0x00 9. "LOCKUP,Core Lockup" "0: Reset is not caused by core LOCKUP event,1: Reset is caused by core LOCKUP event"
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bitfld.long 0x00 7. "POR,Power-on Reset" "0: Reset not caused by POR,1: POR-caused reset"
bitfld.long 0x00 6. "PIN,External Reset Pin" "0: Reset is not caused by external reset pin,1: Reset originates from external reset pin"
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bitfld.long 0x00 5. "WDOG,Watchdog (WDOG)" "0: Reset is not caused by WDOG timeout,1: Reset is caused by WDOG timeout"
bitfld.long 0x00 2. "LOC,Internal Clock Source (ICS) Module Reset" "0: Reset is not caused by the ICS module,1: Reset is caused by the ICS module"
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bitfld.long 0x00 1. "LVD,Low Voltage Detection" "0: Reset is not caused by LVD trip or POR,1: Reset is caused by LVD trip or POR"
group.long 0x04++0x03
line.long 0x00 "SOPT0,System Options Register 0"
hexmask.long.byte 0x00 24.--31. 1. "DELAY,ADC external Trigger Delay"
rbitfld.long 0x00 23. "DLYACT,ADC external Trigger Delay Active" "0: The delay is inactive,1: The delay is active"
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bitfld.long 0x00 19. "CLKOE,Bus Clock Output Enable" "0: Bus clock output is disabled on PTA2,1: Bus clock output is enabled on PTA2"
bitfld.long 0x00 16.--18. "BUSREF,BUS Clock Output select" "0: 000,1: Bus divided by 2,2: Bus divided by 4,3: Bus divided by 8,4: Bus divided by 16,5: Bus divided by 32,6: Bus divided by 64,7: Bus divided by 128"
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bitfld.long 0x00 15. "SBARIN1EN,no description available" "0: SBAR_IN1 on PTA0 is disabled,1: SBAR_IN1 on PTA0 is enabled"
bitfld.long 0x00 14. "SBARIN0EN,no description available" "0: SBAR_IN0 on PTB1 is disabled,1: SBAR_IN0 on PTB1 is enabled"
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bitfld.long 0x00 13. "UARTTXEN,no description available" "0: UART_Tx on PTA7 is disabled,1: UART_Tx on PTA7 is enabled"
bitfld.long 0x00 12. "UARTRXEN,no description available" "0: UART_Rx on PTA6 is disabled,1: UART_Rx on PTA6 is enabled"
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bitfld.long 0x00 10.--11. "FTM1CHEN,FTM1 Channel mapping Enable" "0,1,2,3"
bitfld.long 0x00 8.--9. "FTM0CHEN,FTM0 Channel mapping Enable" "0,1,2,3"
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bitfld.long 0x00 3. "SWDE,Single Wire Debug port pin mapping Enable" "0: SWD_DIO pin mapping on PTA4 is disabled and..,1: PTA4 as SWD_DIO function and PTA5 as SWD_CLK.."
bitfld.long 0x00 2. "RSTPE,RESET Pin mapping Enable" "0: RESET pin mapping is disabled on PTB0,1: PTB0 pin functions as RESET"
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bitfld.long 0x00 1. "NMIE,NMI pin mapping Enable" "0: NMIE pin mapping is disabled on PTB0,1: PTB0 pin functions as NMI when RSTPE = 0"
group.long 0x08++0x03
line.long 0x00 "TBARCFG0,Trigger Crossbar Configuration Register 0"
bitfld.long 0x00 28.--31. "LDOSHUTDOWN2,LDO external Shutdown source 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "LDOSHUTDOWN1,LDO external Shutdown source 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "LDOSHUTDOWN0,LDO external Shutdown source 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CNCEXCLAMP,CNC External Clamp source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "ADCLOADOK,ADC LoadOK source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "ADCABORT,ADC sequence Abort source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "ADCRESTART,ADC Restart source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ADCTRIG,ADC Trigger source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "TBARCFG1,Trigger Crossbar Configuration Register 1"
bitfld.long 0x00 0.--3. "TBAROUT,TBAR_OUT source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "SBARCFG,Signal Crossbar Configuration Register"
bitfld.long 0x00 28.--31. "SBAROUT2,SBAR_OUT2 source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "SBAROUT1,SBAR_OUT1 source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "SBAROUT0,SBAR_OUT0 source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "UARTRX,UART_RxD source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "FTM1CH1IN,FTM1_CH1 Input source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "FTM1CH0IN,FTM1_CH0 Input source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "IRQ,IRQ input source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "FSKDTIN,FSKDT Input source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "XBARCFG,FSK Configuration Register"
bitfld.long 0x00 31. "FSKCLKEN,FSK glitch filter and divider Clock Enable control" "0: Disables the FSK filter/divider clock,1: Enables the FSK filter/divider clock"
hexmask.long.byte 0x00 16.--23. 1. "FILT1,The second glitch filter width configuration control"
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bitfld.long 0x00 12.--15. "FILT0,The first glitch filter width configuration control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--10. "TBARDIV,TBAR FSK Divider source control" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SBARDIV,SBAR FSK Divider source control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "SCGC,System Clock Gating Control Register"
bitfld.long 0x00 30. "ACMP0,ACMP0 Clock Gating Control" "0: Bus clock to the ACMP0 module is disabled,1: Bus clock to the ACMP0 module is enabled"
bitfld.long 0x00 29. "ADC,ADC Clock Gating Control" "0: Bus clock to the ADC module is disabled,1: Bus clock to the ADC module is enabled"
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bitfld.long 0x00 27. "IRQ,IRQ Clock Gating Control" "0: Bus clock to the IRQ module is disabled,1: Bus clock to the IRQ module is enabled"
bitfld.long 0x00 20. "UART0,UART0 Clock Gating Control" "0: Bus clock to the UART0 module is disabled,1: Bus clock to the UART0 module is enabled"
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bitfld.long 0x00 16. "I2C0,I2C0 Clock Gating Control" "0: Bus clock to the I2C0 module is disabled,1: Bus clock to the I2C0 module is enabled"
bitfld.long 0x00 13. "SWD,Single Wire Debugger (SWD) Clock Gating Control" "0: Bus clock to the SWD module is disabled,1: Bus clock to the SWD module is enabled"
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bitfld.long 0x00 12. "FLASH,Flash Clock Gating Control" "0: Bus clock to the Flash module is disabled,1: Bus clock to the Flash module is enabled"
bitfld.long 0x00 10. "LDO,LDO Clock Gating Control" "0: Bus clock to the LDO module is disabled,1: Bus clock to the LDO module is enabled"
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bitfld.long 0x00 9. "PGA,PGA Clock Gating Control" "0: Bus clock to the PGA module is disabled,1: Bus clock to the PGA module is enabled"
bitfld.long 0x00 8. "CNC,CNC Clock Gating Control" "0: Bus clock to the CNC module is disabled,1: Bus clock to the CNC module is enabled"
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bitfld.long 0x00 6. "FTM1,FTM1 Clock Gating Control" "0: Bus clock to the FTM1 module is disabled,1: Bus clock to the FTM1 module is enabled"
bitfld.long 0x00 5. "FTM0,FTM0 Clock Gating Control" "0: Bus clock to the FTM0 module is disabled,1: Bus clock to the FTM0 module is enabled"
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bitfld.long 0x00 4. "FSKDT,FSKDT Clock Gating Control" "0: Bus clock to the FSKDT module is disabled,1: Bus clock to the FSKDT module is enabled"
bitfld.long 0x00 1. "PIT,PIT Clock Gating Control" "0: Bus clock to the PIT module is disabled,1: Bus clock to the PIT module is enabled"
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bitfld.long 0x00 0. "RTC,RTC Clock Gating Control" "0: Bus clock to the RTC module is disabled,1: Bus clock to the RTC module is enabled"
group.long 0x1C++0x03
line.long 0x00 "RST,Reset control Register"
bitfld.long 0x00 30. "ACMP0,ACMP0 Reset Control" "0: Reset to the ACMP0 module is disabled,1: Reset to the ACMP0 module is enabled"
bitfld.long 0x00 27. "IRQ,IRQ Reset Control" "0: Reset to the IRQ module is disabled,1: Reset to the IRQ module is enabled"
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bitfld.long 0x00 20. "UART0,UART0 Reset Control" "0: Reset to the UART0 module is disabled,1: Reset to the UART0 module is enabled"
bitfld.long 0x00 16. "I2C0,I2C0 Reset Control" "0: Reset to the I2C0 module is disabled,1: Reset to the I2C0 module is enabled"
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bitfld.long 0x00 10. "LDO,LDO Reset Control" "0: Reset to the LDO module is disabled,1: Reset to the LDO module is enabled"
bitfld.long 0x00 8. "CNC,CNC Reset Control" "0: Reset to the CNC module is disabled,1: Reset to the CNC module is enabled"
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bitfld.long 0x00 6. "FTM1,FTM1 Reset Control" "0: Reset to the FTM1 module is disabled,1: Reset to the FTM1 module is enabled"
bitfld.long 0x00 5. "FTM0,FTM0 Reset Control" "0: Reset to the FTM0 module is disabled,1: Reset to the FTM0 module is enabled"
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bitfld.long 0x00 4. "FSKDT,FSKDT Reset Control" "0: Reset to the FSKDT module is disabled,1: Reset to the FSKDT module is enabled"
bitfld.long 0x00 1. "PIT,PIT Reset Control" "0: Reset to the PIT module is disabled,1: Reset to the PIT module is enabled"
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bitfld.long 0x00 0. "RTC,RTC Reset Control" "0: Reset to the RTC module is disabled,1: Reset to the RTC module is enabled"
group.long 0x20++0x03
line.long 0x00 "CLKDIV,Clock Divider Register"
bitfld.long 0x00 28.--29. "OUTDIV1,Clock 1 Output Divider value" "0: Same as ICSOUTCLK,1: ICSOUTCLK is divided by 2,2: ICSOUTCLK is divided by 3,3: ICSOUTCLK is divided by 4"
bitfld.long 0x00 24. "OUTDIV2,Clock 2 Output Divider value" "0: Not divided from Divider1,1: Divided by 2 from Divider1"
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bitfld.long 0x00 20. "OUTDIV3,Clock 3 Output Divider value" "0: Same as ICSOUTCLK,1: ICSOUTCLK is divided by 2"
group.long 0x24++0x03
line.long 0x00 "FLG,CNC external clamp and LDO external shutdown Flags Register"
bitfld.long 0x00 1. "ESHUTF,LDO External Shutdown status Flag" "0: LDO external shutdown is de-asserted,1: LDO external shutdown is asserted"
bitfld.long 0x00 0. "ECLAMPF,CNC External Clamp status Flag" "0: CNC external clamp is de-asserted,1: CNC external clamp is asserted"
group.long 0x28++0x03
line.long 0x00 "AOICFG,AOI function Configuration Register"
bitfld.long 0x00 30.--31. "PT0_AC,Product Term 0 A input Configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
bitfld.long 0x00 28.--29. "PT0_BC,Product Term 0 B input Configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
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bitfld.long 0x00 26.--27. "PT0_CC,Product Term 0 C input Configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
bitfld.long 0x00 24.--25. "PT0_DC,Product Term 0 D input Configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
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bitfld.long 0x00 22.--23. "PT1_AC,Product Term 1 A input Configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
bitfld.long 0x00 20.--21. "PT1_BC,Product Term 1 B input Configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
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bitfld.long 0x00 18.--19. "PT1_CC,Product Term 1 C input Configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
bitfld.long 0x00 16.--17. "PT1_DC,Product Term 1 D input Configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
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bitfld.long 0x00 14.--15. "PT2_AC,Product Term 2 A input Configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
bitfld.long 0x00 12.--13. "PT2_BC,Product Term 2 B input Configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
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bitfld.long 0x00 10.--11. "PT2_CC,Product Term 2 C input Configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
bitfld.long 0x00 8.--9. "PT2_DC,Product Term 2 D input Configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
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bitfld.long 0x00 6.--7. "PT3_AC,Product Term 3 A input Configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.."
bitfld.long 0x00 4.--5. "PT3_BC,Product Term 3 B input Configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.."
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bitfld.long 0x00 2.--3. "PT3_CC,Product Term 3 C input Configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.."
bitfld.long 0x00 0.--1. "PT3_DC,Product Term 3 D input Configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.."
group.long 0x2C++0x03
line.long 0x00 "CR,ACMP channel 2 Configuration and SIM_SCGC[ADC] write enable Register"
bitfld.long 0x00 24.--25. "ACMP0CH2SEL,ACMP0_IN[2] Selection" "0: 1/10 AC1,1: 1/4 ADP_IN,2: 1/8 VREC,3: 7/10 VOUT"
bitfld.long 0x00 8. "ADCGCWEN,ADC Clock Gating control bit Write Enable" "0: SIM_SCGC[ADC] cannot be changed,1: SIM_SCGC[ADC] can be changed"
rgroup.long 0x30++0x03
line.long 0x00 "UUIDL,Universally Unique Identifier Low Register"
hexmask.long 0x00 0.--31. 1. "ID,Universally Unique Identifier"
rgroup.long 0x34++0x03
line.long 0x00 "UUIDML,Universally Unique Identifier Middle Low Register"
hexmask.long 0x00 0.--31. 1. "ID,Universally Unique Identifier"
rgroup.long 0x38++0x03
line.long 0x00 "UUIDMH,Universally Unique Identifier Middle High Register"
hexmask.long.word 0x00 0.--15. 1. "ID,Universally Unique Identifier"
rgroup.long 0x3C++0x03
line.long 0x00 "IFR0,Peripherals IFR bits Register 0"
hexmask.long.word 0x00 21.--31. 1. "IFR0_31_21,no description available"
hexmask.long.word 0x00 10.--20. 1. "IFR0_20_10,no description available"
rgroup.long 0x40++0x03
line.long 0x00 "IFR1,Peripherals IFR bits Register 1"
bitfld.long 0x00 12.--17. "IFR1_17_12,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--11. "IFR1_11_6,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "IFR1_5_0,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x44++0x03
line.long 0x00 "IFR2,Peripherals IFR bits Register 2"
hexmask.long.word 0x00 11.--21. 1. "IFR2_21_11,no description available"
hexmask.long.word 0x00 0.--10. 1. "IFR2_10_0,no description available"
rgroup.long 0x48++0x03
line.long 0x00 "IFR3,Peripherals IFR bits Register 3"
hexmask.long.word 0x00 12.--22. 1. "IFR3_22_12,no description available"
hexmask.long.word 0x00 0.--11. 1. "IFR3_11_0,no description available"
tree.end
tree "UART0 (Universal Asynchronous Receiver/Transmitter (UART))"
base ad:0x4006A000
group.byte 0x00++0x00
line.byte 0x00 "BDH,UART Baud Rate Register: High"
bitfld.byte 0x00 7. "LBKDIE,LIN Break Detect Interrupt Enable (for LBKDIF)" "0: Hardware interrupts from UART_S2[LBKDIF]..,1: Hardware interrupt requested when.."
bitfld.byte 0x00 6. "RXEDGIE,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "0: Hardware interrupts from UART_S2[RXEDGIF]..,1: Hardware interrupt requested when.."
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bitfld.byte 0x00 5. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bit"
bitfld.byte 0x00 0.--4. "SBR,Baud Rate Modulo Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x01++0x00
line.byte 0x00 "BDL,UART Baud Rate Register: Low"
hexmask.byte 0x00 0.--7. 1. "SBR,Baud Rate Modulo Divisor"
group.byte 0x02++0x00
line.byte 0x00 "C1,UART Control Register 1"
bitfld.byte 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RxD and TxD use separate..,1: Loop mode or single-wire mode where.."
bitfld.byte 0x00 6. "UARTSWAI,UART Stops in Wait Mode" "0: UART clocks continue to run in Wait mode so..,1: UART clocks freeze while CPU is in Wait mode"
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bitfld.byte 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire UART mode where the TxD pin is.."
bitfld.byte 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Normal - start + 8 data bits (lsb first) + stop,1: Receiver and transmitter use 9-bit data.."
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bitfld.byte 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Idle-line wake-up,1: Address-mark wake-up"
bitfld.byte 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
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bitfld.byte 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
bitfld.byte 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
group.byte 0x03++0x00
line.byte 0x00 "C2,UART Control Register 2"
bitfld.byte 0x00 7. "TIE,Transmit Interrupt Enable for TDRE" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
bitfld.byte 0x00 6. "TCIE,Transmission Complete Interrupt Enable for TC" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
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bitfld.byte 0x00 5. "RIE,Receiver Interrupt Enable for RDRF" "0: Hardware interrupts from S1[RDRF] disabled..,1: Hardware interrupt requested when S1[RDRF].."
bitfld.byte 0x00 4. "ILIE,Idle Line Interrupt Enable for IDLE" "0: Hardware interrupts from S1[IDLE] disabled..,1: Hardware interrupt requested when S1[IDLE].."
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bitfld.byte 0x00 3. "TE,Transmitter Enable" "0: Transmitter off,1: Transmitter on"
bitfld.byte 0x00 2. "RE,Receiver Enable" "0: Receiver off,1: Receiver on"
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bitfld.byte 0x00 1. "RWU,Receiver Wakeup Control" "0: Normal UART receiver operation,1: UART receiver in standby waiting for wake-up.."
bitfld.byte 0x00 0. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
rgroup.byte 0x04++0x00
line.byte 0x00 "S1,UART Status Register 1"
bitfld.byte 0x00 7. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data register (buffer) full,1: Transmit data register (buffer) empty"
bitfld.byte 0x00 6. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
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bitfld.byte 0x00 5. "RDRF,Receive Data Register Full Flag" "0: Receive data register empty,1: Receive data register full"
bitfld.byte 0x00 4. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
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bitfld.byte 0x00 3. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new UART data lost)"
bitfld.byte 0x00 2. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
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bitfld.byte 0x00 1. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
bitfld.byte 0x00 0. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
group.byte 0x05++0x00
line.byte 0x00 "S2,UART Status Register 2"
bitfld.byte 0x00 7. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
bitfld.byte 0x00 6. "RXEDGIF,RxD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
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bitfld.byte 0x00 4. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
bitfld.byte 0x00 3. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1)..,1: During receive standby state (RWU = 1).."
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bitfld.byte 0x00 2. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
bitfld.byte 0x00 1. "LBKDE,LIN Break Detection Enable" "0: Break detection is disabled,1: Break detection is enabled (Break character.."
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rbitfld.byte 0x00 0. "RAF,Receiver Active Flag" "0: UART receiver idle waiting for a start bit,1: UART receiver active (RxD input not idle)"
group.byte 0x06++0x00
line.byte 0x00 "C3,UART Control Register 3"
rbitfld.byte 0x00 7. "R8,Ninth Data Bit for Receiver" "0,1"
bitfld.byte 0x00 6. "T8,Ninth Data Bit for Transmitter" "0,1"
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bitfld.byte 0x00 5. "TXDIR,TxD Pin Direction in Single-Wire Mode" "0: TxD pin is an input in single-wire mode,1: TxD pin is an output in single-wire mode"
bitfld.byte 0x00 4. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
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bitfld.byte 0x00 3. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
bitfld.byte 0x00 2. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling),1: Hardware interrupt requested when NF is set"
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bitfld.byte 0x00 1. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling),1: Hardware interrupt requested when FE is set"
bitfld.byte 0x00 0. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
group.byte 0x07++0x00
line.byte 0x00 "D,UART Data Register"
bitfld.byte 0x00 7. "R7T7,no description available" "0,1"
bitfld.byte 0x00 6. "R6T6,no description available" "0,1"
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bitfld.byte 0x00 5. "R5T5,no description available" "0,1"
bitfld.byte 0x00 4. "R4T4,no description available" "0,1"
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bitfld.byte 0x00 3. "R3T3,no description available" "0,1"
bitfld.byte 0x00 2. "R2T2,no description available" "0,1"
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bitfld.byte 0x00 1. "R1T1,no description available" "0,1"
bitfld.byte 0x00 0. "R0T0,no description available" "0,1"
tree.end
tree "WDOG (Watchdog Timer Unit)"
base ad:0x40052000
group.byte 0x00++0x00
line.byte 0x00 "CS1,Watchdog Control and Status Register 1"
bitfld.byte 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
bitfld.byte 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
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bitfld.byte 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
bitfld.byte 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
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bitfld.byte 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
bitfld.byte 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
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bitfld.byte 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
group.byte 0x01++0x00
line.byte 0x00 "CS2,Watchdog Control and Status Register 2"
bitfld.byte 0x00 7. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
bitfld.byte 0x00 6. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
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bitfld.byte 0x00 4. "PRES,Watchdog Prescalar" "0: 256 prescalar disabled,1: 256 prescalar enabled"
bitfld.byte 0x00 0.--1. "CLK,Watchdog Clock" "0: Bus clock,1: 20 kHz internal low-power oscillator (LPOCLK),2: 32 kHz internal oscillator (ICSIRCLK),3: External clock source"
group.word 0x02++0x01
line.word 0x00 "CNT,Watchdog Counter Register"
hexmask.word 0x00 0.--15. 1. "CNT,Watchdog Counter Value"
rgroup.byte 0x02++0x00
line.byte 0x00 "CNTH,Watchdog Counter Register: High"
hexmask.byte 0x00 0.--7. 1. "CNTHIGH,High byte of the Watchdog Counter"
rgroup.byte 0x03++0x00
line.byte 0x00 "CNTL,Watchdog Counter Register: Low"
hexmask.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
group.byte 0x04++0x00
line.byte 0x00 "TOVALH,Watchdog Timeout Value Register: High"
hexmask.byte 0x00 0.--7. 1. "TOVALHIGH,High byte of the timeout value"
group.word 0x04++0x01
line.word 0x00 "TOVAL,Watchdog Timeout Value Register"
hexmask.word 0x00 0.--15. 1. "TOVAL,Watchdog Timeout Value"
group.byte 0x05++0x00
line.byte 0x00 "TOVALL,Watchdog Timeout Value Register: Low"
hexmask.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
group.byte 0x06++0x00
line.byte 0x00 "WINH,Watchdog Window Register: High"
hexmask.byte 0x00 0.--7. 1. "WINHIGH,High byte of Watchdog Window"
group.word 0x06++0x01
line.word 0x00 "WIN,Watchdog Window Register"
hexmask.word 0x00 0.--15. 1. "WIN,Watchdog Window Value"
group.byte 0x07++0x00
line.byte 0x00 "WINL,Watchdog Window Register: Low"
hexmask.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
tree.end
autoindent.off
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