21251 lines
1.2 MiB
21251 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32WB On-Chip Peripherals
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; @Props: Released
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; @Author: DPR, DAB, NEJ
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; @Changelog: 2019-11-04 DPR
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; 2020-01-28 DAB
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; 2023-09-18 NEJ
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; 2024-01-19 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: Generated (TRACE32, build: 166062.), based on:
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; STM32WB10_CM4.svd (Ver. 1.4), STM32WB15_CM4.svd (Ver. 1.4),
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; STM32WB30_CM4.svd (Ver. 1.7), STM32WB35_CM4.svd (Ver. 1.7),
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; STM32WB50_CM4.svd (Ver. 1.7), STM32WB55_CM0P.svd (Ver. 2.0),
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; STM32WB55_CM4.svd (Ver. 2.0)
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; @Core: Cortex-M4F, Cortex-M0+
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; @Chip: STM32WB10CC-CM0+, STM32WB10CC-CM4, STM32WB15CC-CM0+, STM32WB15CC-CM4,
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; STM32WB30CE-CM0+, STM32WB30CE-CM4, STM32WB35CC-CM0+, STM32WB35CC-CM4,
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; STM32WB35CE-CM0+, STM32WB35CE-CM4, STM32WB50CG-CM0+, STM32WB50CG-CM4,
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; STM32WB55CC-CM0+, STM32WB55CC-CM4, STM32WB55CE-CM0+, STM32WB55CE-CM4,
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; STM32WB55CG-CM0+, STM32WB55CG-CM4, STM32WB55RC-CM0+, STM32WB55RC-CM4,
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; STM32WB55RE-CM0+, STM32WB55RE-CM4, STM32WB55RG-CM0+, STM32WB55RG-CM4,
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; STM32WB55VC-CM0+, STM32WB55VC-CM4, STM32WB55VE-CM0+, STM32WB55VE-CM4,
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; STM32WB55VG-CM0+, STM32WB55VG-CM4, STM32WB55VY-CM0+, STM32WB55VY-CM4,
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; STM32WB5MMG-CM0+, STM32WB5MMG-CM4
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32wb.per 17395 2024-01-25 15:39:09Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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sif (CORENAME()=="CORTEXM0+")
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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|
group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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|
textline " "
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|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
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|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (CORENAME()=="CORTEXM4F")
|
|
tree.close "Core Registers (Cortex-M4F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
base ad:0x40012400
|
|
elif (cpuis("STM32WB30*")||cpuis("STM32WB35*")||cpuis("STM32WB50*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
base ad:0x50040000
|
|
endif
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ISR,ADC interrupt and status register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 13. "CCRDY,CCRDY" "0,1"
|
|
bitfld.long 0x0 11. "EOCAL,EOCAL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue overflow flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue overflow flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue overflow flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue overflow flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue overflow flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence conversions flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence conversions flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence conversions flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence conversions flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence conversions flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary conversion flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary conversion flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary conversion flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary conversion flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary conversion flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,ADC interrupt enable register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 13. "CCRDYIE,CCRDYIE" "0,1"
|
|
bitfld.long 0x4 11. "EOCALIE,EOCALIE" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue overflow interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue overflow interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue overflow interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue overflow interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue overflow interrupt" "0,1"
|
|
endif
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence conversions interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence conversions interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence conversions interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence conversions interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence conversions interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary conversion interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary conversion interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary conversion interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary conversion interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary conversion interrupt" "0,1"
|
|
endif
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for calibration" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for calibration" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for calibration" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for calibration" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for calibration" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1"
|
|
endif
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 5. "JADSTP,ADC group injected conversion stop" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 5. "JADSTP,ADC group injected conversion stop" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 5. "JADSTP,ADC group injected conversion stop" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 5. "JADSTP,ADC group injected conversion stop" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 5. "JADSTP,ADC group injected conversion stop" "0,1"
|
|
endif
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 3. "JADSTART,ADC group injected conversion start" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 3. "JADSTART,ADC group injected conversion start" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 3. "JADSTART,ADC group injected conversion start" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 3. "JADSTART,ADC group injected conversion start" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 3. "JADSTART,ADC group injected conversion start" "0,1"
|
|
endif
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR1,ADC configuration register 1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH,AWD1CH"
|
|
bitfld.long 0x0 23. "AWD1EN,AWD1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0x0 21. "CHSELRMOD,CHSELRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0x0 15. "AUTOFF,AUTOFF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,WAIT" "0,1"
|
|
bitfld.long 0x0 13. "CONT,CONT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,OVRMOD" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--8. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5. "ALIGN,ALIGN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0x0 2. "SCANDIR,SCANDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0x0 0. "DMAEN,DMAEN" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SMPR,ADC sampling time register"
|
|
hexmask.long.tbyte 0x0 8.--26. 1. "SMPSEL,SMPSEL"
|
|
bitfld.long 0x0 4.--6. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CHSELR0,channel selection register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "CHSEL,CHSEL"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CHSELR1,channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,SQ7"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,SQ5"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,SQ3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,SQ1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR,ADC configuration register 1"
|
|
bitfld.long 0x0 31. "JQDIS,ADC group injected contexts queue disable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel selection"
|
|
newline
|
|
bitfld.long 0x0 25. "JAUTO,ADC group injected automatic trigger mode" "0,1"
|
|
bitfld.long 0x0 24. "JAWD1EN,ADC analog watchdog 1 enable on scope ADC group injected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a single channel or all channels" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "JQM,ADC group injected contexts queue mode" "0,1"
|
|
bitfld.long 0x0 20. "JDISCEN,ADC group injected sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "DISCNUM,ADC group regular sequencer discontinuous number of ranks" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AUTDLY,ADC low power auto wait" "0,1"
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "EXTSEL,ADC group regular external trigger source"
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x0 27.--29. "SMP9,ADC channel 9 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "SMP8,ADC channel 8 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "SMP7,ADC channel 7 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "SMP6,ADC channel 6 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "SMP5,ADC channel 5 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SMP4,ADC channel 4 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "SMP3,ADC channel 3 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "SMP2,ADC channel 2 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "SMP1,ADC channel 1 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x4 24.--26. "SMP18,ADC channel 18 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "SMP17,ADC channel 17 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "SMP16,ADC channel 16 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15.--17. "SMP15,ADC channel 15 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SMP14,ADC channel 14 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "SMP13,ADC channel 13 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SMP12,ADC channel 12 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3.--5. "SMP11,ADC channel 11 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SMP10,ADC channel 10 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold low"
|
|
line.long 0x4 "TR2,ADC analog watchdog 2 threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,ADC analog watchdog 2 threshold high"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,ADC analog watchdog 2 threshold low"
|
|
line.long 0x8 "TR3,ADC analog watchdog 3 threshold register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,ADC analog watchdog 3 threshold high"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,ADC analog watchdog 3 threshold low"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,ADC group regular sequencer ranks register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank 4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank 2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L3,L3"
|
|
line.long 0x4 "SQR2,ADC group regular sequencer ranks register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank 9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank 7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank 6"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank 5"
|
|
line.long 0x8 "SQR3,ADC group regular sequencer ranks register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank 14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank 12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank 11"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank 10"
|
|
line.long 0xC "SQR4,ADC group regular sequencer ranks register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank 16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank 15"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR,ADC configuration register 1"
|
|
bitfld.long 0x0 31. "JQDIS,ADC group injected contexts queue disable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel selection"
|
|
newline
|
|
bitfld.long 0x0 25. "JAUTO,ADC group injected automatic trigger mode" "0,1"
|
|
bitfld.long 0x0 24. "JAWD1EN,ADC analog watchdog 1 enable on scope ADC group injected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a single channel or all channels" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "JQM,ADC group injected contexts queue mode" "0,1"
|
|
bitfld.long 0x0 20. "JDISCEN,ADC group injected sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "DISCNUM,ADC group regular sequencer discontinuous number of ranks" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AUTDLY,ADC low power auto wait" "0,1"
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "EXTSEL,ADC group regular external trigger source"
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x0 27.--29. "SMP9,ADC channel 9 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "SMP8,ADC channel 8 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "SMP7,ADC channel 7 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "SMP6,ADC channel 6 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "SMP5,ADC channel 5 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SMP4,ADC channel 4 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "SMP3,ADC channel 3 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "SMP2,ADC channel 2 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "SMP1,ADC channel 1 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SMP0,ADC channel 0 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x4 24.--26. "SMP18,ADC channel 18 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "SMP17,ADC channel 17 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "SMP16,ADC channel 16 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15.--17. "SMP15,ADC channel 15 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SMP14,ADC channel 14 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "SMP13,ADC channel 13 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SMP12,ADC channel 12 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3.--5. "SMP11,ADC channel 11 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SMP10,ADC channel 10 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold low"
|
|
line.long 0x4 "TR2,ADC analog watchdog 2 threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,ADC analog watchdog 2 threshold high"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,ADC analog watchdog 2 threshold low"
|
|
line.long 0x8 "TR3,ADC analog watchdog 3 threshold register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,ADC analog watchdog 3 threshold high"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,ADC analog watchdog 3 threshold low"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,ADC group regular sequencer ranks register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank 4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank 2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L3,L3"
|
|
line.long 0x4 "SQR2,ADC group regular sequencer ranks register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank 9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank 7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank 6"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank 5"
|
|
line.long 0x8 "SQR3,ADC group regular sequencer ranks register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank 14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank 12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank 11"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank 10"
|
|
line.long 0xC "SQR4,ADC group regular sequencer ranks register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank 16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank 15"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR,ADC configuration register 1"
|
|
bitfld.long 0x0 31. "JQDIS,ADC group injected contexts queue disable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel selection"
|
|
newline
|
|
bitfld.long 0x0 25. "JAUTO,ADC group injected automatic trigger mode" "0,1"
|
|
bitfld.long 0x0 24. "JAWD1EN,ADC analog watchdog 1 enable on scope ADC group injected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a single channel or all channels" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "JQM,ADC group injected contexts queue mode" "0,1"
|
|
bitfld.long 0x0 20. "JDISCEN,ADC group injected sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "DISCNUM,ADC group regular sequencer discontinuous number of ranks" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AUTDLY,ADC low power auto wait" "0,1"
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "EXTSEL,ADC group regular external trigger source"
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x0 27.--29. "SMP9,ADC channel 9 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "SMP8,ADC channel 8 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "SMP7,ADC channel 7 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "SMP6,ADC channel 6 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "SMP5,ADC channel 5 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SMP4,ADC channel 4 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "SMP3,ADC channel 3 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "SMP2,ADC channel 2 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "SMP1,ADC channel 1 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x4 24.--26. "SMP18,ADC channel 18 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "SMP17,ADC channel 17 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "SMP16,ADC channel 16 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15.--17. "SMP15,ADC channel 15 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SMP14,ADC channel 14 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "SMP13,ADC channel 13 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SMP12,ADC channel 12 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3.--5. "SMP11,ADC channel 11 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SMP10,ADC channel 10 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold low"
|
|
line.long 0x4 "TR2,ADC analog watchdog 2 threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,ADC analog watchdog 2 threshold high"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,ADC analog watchdog 2 threshold low"
|
|
line.long 0x8 "TR3,ADC analog watchdog 3 threshold register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,ADC analog watchdog 3 threshold high"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,ADC analog watchdog 3 threshold low"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,ADC group regular sequencer ranks register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank 4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank 2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L3,L3"
|
|
line.long 0x4 "SQR2,ADC group regular sequencer ranks register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank 9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank 7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank 6"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank 5"
|
|
line.long 0x8 "SQR3,ADC group regular sequencer ranks register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank 14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank 12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank 11"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank 10"
|
|
line.long 0xC "SQR4,ADC group regular sequencer ranks register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank 16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank 15"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR,ADC configuration register 1"
|
|
bitfld.long 0x0 31. "JQDIS,ADC group injected contexts queue disable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel selection"
|
|
newline
|
|
bitfld.long 0x0 25. "JAUTO,ADC group injected automatic trigger mode" "0,1"
|
|
bitfld.long 0x0 24. "JAWD1EN,ADC analog watchdog 1 enable on scope ADC group injected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a single channel or all channels" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "JQM,ADC group injected contexts queue mode" "0,1"
|
|
bitfld.long 0x0 20. "JDISCEN,ADC group injected sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "DISCNUM,ADC group regular sequencer discontinuous number of ranks" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AUTDLY,ADC low power auto wait" "0,1"
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "EXTSEL,ADC group regular external trigger source"
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x0 27.--29. "SMP9,ADC channel 9 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "SMP8,ADC channel 8 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "SMP7,ADC channel 7 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "SMP6,ADC channel 6 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "SMP5,ADC channel 5 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SMP4,ADC channel 4 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "SMP3,ADC channel 3 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "SMP2,ADC channel 2 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "SMP1,ADC channel 1 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SMP0,ADC channel 0 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x4 24.--26. "SMP18,ADC channel 18 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "SMP17,ADC channel 17 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "SMP16,ADC channel 16 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15.--17. "SMP15,ADC channel 15 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SMP14,ADC channel 14 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "SMP13,ADC channel 13 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SMP12,ADC channel 12 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3.--5. "SMP11,ADC channel 11 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SMP10,ADC channel 10 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold low"
|
|
line.long 0x4 "TR2,ADC analog watchdog 2 threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,ADC analog watchdog 2 threshold high"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,ADC analog watchdog 2 threshold low"
|
|
line.long 0x8 "TR3,ADC analog watchdog 3 threshold register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,ADC analog watchdog 3 threshold high"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,ADC analog watchdog 3 threshold low"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,ADC group regular sequencer ranks register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank 4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank 2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L3,L3"
|
|
line.long 0x4 "SQR2,ADC group regular sequencer ranks register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank 9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank 7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank 6"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank 5"
|
|
line.long 0x8 "SQR3,ADC group regular sequencer ranks register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank 14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank 12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank 11"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank 10"
|
|
line.long 0xC "SQR4,ADC group regular sequencer ranks register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank 16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank 15"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CFGR,ADC configuration register 1"
|
|
bitfld.long 0x0 31. "JQDIS,ADC group injected contexts queue disable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel selection"
|
|
newline
|
|
bitfld.long 0x0 25. "JAUTO,ADC group injected automatic trigger mode" "0,1"
|
|
bitfld.long 0x0 24. "JAWD1EN,ADC analog watchdog 1 enable on scope ADC group injected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a single channel or all channels" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "JQM,ADC group injected contexts queue mode" "0,1"
|
|
bitfld.long 0x0 20. "JDISCEN,ADC group injected sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "DISCNUM,ADC group regular sequencer discontinuous number of ranks" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AUTDLY,ADC low power auto wait" "0,1"
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "EXTSEL,ADC group regular external trigger source"
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x0 27.--29. "SMP9,ADC channel 9 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "SMP8,ADC channel 8 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "SMP7,ADC channel 7 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "SMP6,ADC channel 6 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "SMP5,ADC channel 5 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SMP4,ADC channel 4 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "SMP3,ADC channel 3 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "SMP2,ADC channel 2 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "SMP1,ADC channel 1 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SMP0,ADC channel 0 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x4 24.--26. "SMP18,ADC channel 18 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "SMP17,ADC channel 17 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "SMP16,ADC channel 16 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15.--17. "SMP15,ADC channel 15 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SMP14,ADC channel 14 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "SMP13,ADC channel 13 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6.--8. "SMP12,ADC channel 12 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3.--5. "SMP11,ADC channel 11 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SMP10,ADC channel 10 sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold low"
|
|
line.long 0x4 "TR2,ADC analog watchdog 2 threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,ADC analog watchdog 2 threshold high"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,ADC analog watchdog 2 threshold low"
|
|
line.long 0x8 "TR3,ADC analog watchdog 3 threshold register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,ADC analog watchdog 3 threshold high"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,ADC analog watchdog 3 threshold low"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,ADC group regular sequencer ranks register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank 4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank 2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L3,L3"
|
|
line.long 0x4 "SQR2,ADC group regular sequencer ranks register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank 9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank 7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank 6"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank 5"
|
|
line.long 0x8 "SQR3,ADC group regular sequencer ranks register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank 14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank 12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank 11"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank 10"
|
|
line.long 0xC "SQR4,ADC group regular sequencer ranks register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank 16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank 15"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CFGR2,ADC configuration register 2"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 30.--31. "CKMODE,CKMODE" "0,1,2,3"
|
|
bitfld.long 0x0 29. "LFTRIG,LFTRIG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 10. "ROVSM,ADC oversampling mode managing interlaced conversions of ADC group regular and group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 10. "ROVSM,ADC oversampling mode managing interlaced conversions of ADC group regular and group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 10. "ROVSM,ADC oversampling mode managing interlaced conversions of ADC group regular and group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10. "ROVSM,ADC oversampling mode managing interlaced conversions of ADC group regular and group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10. "ROVSM,ADC oversampling mode managing interlaced conversions of ADC group regular and group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 9. "TOVS,TOVS" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,OVSS"
|
|
bitfld.long 0x0 2.--4. "OVSR,OVSR" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 9. "TOVS,ADC oversampling discontinuous mode (triggered mode) for ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 9. "TOVS,ADC oversampling discontinuous mode (triggered mode) for ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 9. "TOVS,ADC oversampling discontinuous mode (triggered mode) for ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 9. "TOVS,ADC oversampling discontinuous mode (triggered mode) for ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 9. "TOVS,ADC oversampling discontinuous mode (triggered mode) for ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 1. "JOVSE,ADC oversampler enable on scope ADC group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 1. "JOVSE,ADC oversampler enable on scope ADC group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 1. "JOVSE,ADC oversampler enable on scope ADC group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "JOVSE,ADC oversampler enable on scope ADC group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "JOVSE,ADC oversampler enable on scope ADC group injected" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 0. "OVSE,OVSE" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 0. "ROVSE,ADC oversampler enable on scope ADC group regular" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 0. "ROVSE,ADC oversampler enable on scope ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 0. "ROVSE,ADC oversampler enable on scope ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "ROVSE,ADC oversampler enable on scope ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "ROVSE,ADC oversampler enable on scope ADC group regular" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ADC_TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,HT2"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,LT2"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT3,HT3"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT3,LT3"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC data register"
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.word 0x0 7.--15. 1. "RDATA_7_15,15"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.word 0x0 7.--15. 1. "RDATA_7_15,15"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.word 0x0 7.--15. 1. "RDATA_7_15,15"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.word 0x0 7.--15. 1. "RDATA_7_15,15"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.word 0x0 7.--15. 1. "RDATA_7_15,15"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,DATA"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "RDATA_0_6,Regular Data converted 0_6"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "RDATA_0_6,Regular Data converted 0_6"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "RDATA_0_6,Regular Data converted 0_6"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "RDATA_0_6,Regular Data converted 0_6"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "RDATA_0_6,Regular Data converted 0_6"
|
|
endif
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "CALFACT,ADC Calibration factor"
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "CALFACT_D,ADC calibration factor in differential mode"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "CALFACT_D,ADC calibration factor in differential mode"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "CALFACT_D,ADC calibration factor in differential mode"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "CALFACT_D,ADC calibration factor in differential mode"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "CALFACT_D,ADC calibration factor in differential mode"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,CALFACT"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT_S,ADC calibration factor in single-ended mode"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT_S,ADC calibration factor in single-ended mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT_S,ADC calibration factor in single-ended mode"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT_S,ADC calibration factor in single-ended mode"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT_S,ADC calibration factor in single-ended mode"
|
|
endif
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBATEN" "0,1"
|
|
bitfld.long 0x0 23. "TSEN,TSEN" "0,1"
|
|
bitfld.long 0x0 22. "VREFEN,VREFEN" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,PRESC"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,ADC group injected sequencer register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "JSQ4,ADC group injected sequencer rank 4"
|
|
hexmask.long.byte 0x0 20.--24. 1. "JSQ3,ADC group injected sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "JSQ2,ADC group injected sequencer rank 2"
|
|
hexmask.long.byte 0x0 8.--12. 1. "JSQ1,ADC group injected sequencer rank 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "JEXTEN,ADC group injected external trigger polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "JEXTSEL,ADC group injected external trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan length" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,ADC offset number 1 register"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,ADC offset number 1 enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel selection"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,ADC offset number 1 offset level"
|
|
line.long 0x4 "OFR2,ADC offset number 2 register"
|
|
bitfld.long 0x4 31. "OFFSET2_EN,ADC offset number 2 enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,ADC offset number 2 channel selection"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET2,ADC offset number 2 offset level"
|
|
line.long 0x8 "OFR3,ADC offset number 3 register"
|
|
bitfld.long 0x8 31. "OFFSET3_EN,ADC offset number 3 enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,ADC offset number 3 channel selection"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET3,ADC offset number 3 offset level"
|
|
line.long 0xC "OFR4,ADC offset number 4 register"
|
|
bitfld.long 0xC 31. "OFFSET4_EN,ADC offset number 4 enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,ADC offset number 4 channel selection"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET4,ADC offset number 4 offset level"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,ADC group injected sequencer rank 1 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,ADC group injected sequencer rank 1 conversion data"
|
|
line.long 0x4 "JDR2,ADC group injected sequencer rank 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,ADC group injected sequencer rank 2 conversion data"
|
|
line.long 0x8 "JDR3,ADC group injected sequencer rank 3 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,ADC group injected sequencer rank 3 conversion data"
|
|
line.long 0xC "JDR4,ADC group injected sequencer rank 4 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,ADC group injected sequencer rank 4 conversion data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel selection"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel selection"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "DIFSEL,ADC channel differential or single-ended mode selection register"
|
|
rbitfld.long 0x0 16.--18. "DIFSEL_16_18,ADC channel differential or single-ended mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 1.--15. 1. "DIFSEL_1_15,ADC channel differential or single-ended mode for channels 1 to 15"
|
|
newline
|
|
rbitfld.long 0x0 0. "DIFSEL_0,ADC channel differential or single-ended mode for channel 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,ADC group injected sequencer register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "JSQ4,ADC group injected sequencer rank 4"
|
|
hexmask.long.byte 0x0 20.--24. 1. "JSQ3,ADC group injected sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "JSQ2,ADC group injected sequencer rank 2"
|
|
hexmask.long.byte 0x0 8.--12. 1. "JSQ1,ADC group injected sequencer rank 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "JEXTEN,ADC group injected external trigger polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "JEXTSEL,ADC group injected external trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan length" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,ADC offset number 1 register"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,ADC offset number 1 enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel selection"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,ADC offset number 1 offset level"
|
|
line.long 0x4 "OFR2,ADC offset number 2 register"
|
|
bitfld.long 0x4 31. "OFFSET2_EN,ADC offset number 2 enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,ADC offset number 2 channel selection"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET2,ADC offset number 2 offset level"
|
|
line.long 0x8 "OFR3,ADC offset number 3 register"
|
|
bitfld.long 0x8 31. "OFFSET3_EN,ADC offset number 3 enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,ADC offset number 3 channel selection"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET3,ADC offset number 3 offset level"
|
|
line.long 0xC "OFR4,ADC offset number 4 register"
|
|
bitfld.long 0xC 31. "OFFSET4_EN,ADC offset number 4 enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,ADC offset number 4 channel selection"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET4,ADC offset number 4 offset level"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,ADC group injected sequencer rank 1 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,ADC group injected sequencer rank 1 conversion data"
|
|
line.long 0x4 "JDR2,ADC group injected sequencer rank 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,ADC group injected sequencer rank 2 conversion data"
|
|
line.long 0x8 "JDR3,ADC group injected sequencer rank 3 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,ADC group injected sequencer rank 3 conversion data"
|
|
line.long 0xC "JDR4,ADC group injected sequencer rank 4 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,ADC group injected sequencer rank 4 conversion data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel selection"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel selection"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "DIFSEL,ADC channel differential or single-ended mode selection register"
|
|
rbitfld.long 0x0 16.--18. "DIFSEL_16_18,ADC channel differential or single-ended mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 1.--15. 1. "DIFSEL_1_15,ADC channel differential or single-ended mode for channels 1 to 15"
|
|
newline
|
|
rbitfld.long 0x0 0. "DIFSEL_0,ADC channel differential or single-ended mode for channel 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,ADC group injected sequencer register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "JSQ4,ADC group injected sequencer rank 4"
|
|
hexmask.long.byte 0x0 20.--24. 1. "JSQ3,ADC group injected sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "JSQ2,ADC group injected sequencer rank 2"
|
|
hexmask.long.byte 0x0 8.--12. 1. "JSQ1,ADC group injected sequencer rank 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "JEXTEN,ADC group injected external trigger polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "JEXTSEL,ADC group injected external trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan length" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,ADC offset number 1 register"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,ADC offset number 1 enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel selection"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,ADC offset number 1 offset level"
|
|
line.long 0x4 "OFR2,ADC offset number 2 register"
|
|
bitfld.long 0x4 31. "OFFSET2_EN,ADC offset number 2 enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,ADC offset number 2 channel selection"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET2,ADC offset number 2 offset level"
|
|
line.long 0x8 "OFR3,ADC offset number 3 register"
|
|
bitfld.long 0x8 31. "OFFSET3_EN,ADC offset number 3 enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,ADC offset number 3 channel selection"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET3,ADC offset number 3 offset level"
|
|
line.long 0xC "OFR4,ADC offset number 4 register"
|
|
bitfld.long 0xC 31. "OFFSET4_EN,ADC offset number 4 enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,ADC offset number 4 channel selection"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET4,ADC offset number 4 offset level"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,ADC group injected sequencer rank 1 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,ADC group injected sequencer rank 1 conversion data"
|
|
line.long 0x4 "JDR2,ADC group injected sequencer rank 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,ADC group injected sequencer rank 2 conversion data"
|
|
line.long 0x8 "JDR3,ADC group injected sequencer rank 3 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,ADC group injected sequencer rank 3 conversion data"
|
|
line.long 0xC "JDR4,ADC group injected sequencer rank 4 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,ADC group injected sequencer rank 4 conversion data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel selection"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel selection"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "DIFSEL,ADC channel differential or single-ended mode selection register"
|
|
rbitfld.long 0x0 16.--18. "DIFSEL_16_18,ADC channel differential or single-ended mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 1.--15. 1. "DIFSEL_1_15,ADC channel differential or single-ended mode for channels 1 to 15"
|
|
newline
|
|
rbitfld.long 0x0 0. "DIFSEL_0,ADC channel differential or single-ended mode for channel 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,ADC group injected sequencer register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "JSQ4,ADC group injected sequencer rank 4"
|
|
hexmask.long.byte 0x0 20.--24. 1. "JSQ3,ADC group injected sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "JSQ2,ADC group injected sequencer rank 2"
|
|
hexmask.long.byte 0x0 8.--12. 1. "JSQ1,ADC group injected sequencer rank 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "JEXTEN,ADC group injected external trigger polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "JEXTSEL,ADC group injected external trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan length" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,ADC offset number 1 register"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,ADC offset number 1 enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel selection"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,ADC offset number 1 offset level"
|
|
line.long 0x4 "OFR2,ADC offset number 2 register"
|
|
bitfld.long 0x4 31. "OFFSET2_EN,ADC offset number 2 enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,ADC offset number 2 channel selection"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET2,ADC offset number 2 offset level"
|
|
line.long 0x8 "OFR3,ADC offset number 3 register"
|
|
bitfld.long 0x8 31. "OFFSET3_EN,ADC offset number 3 enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,ADC offset number 3 channel selection"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET3,ADC offset number 3 offset level"
|
|
line.long 0xC "OFR4,ADC offset number 4 register"
|
|
bitfld.long 0xC 31. "OFFSET4_EN,ADC offset number 4 enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,ADC offset number 4 channel selection"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET4,ADC offset number 4 offset level"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,ADC group injected sequencer rank 1 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,ADC group injected sequencer rank 1 conversion data"
|
|
line.long 0x4 "JDR2,ADC group injected sequencer rank 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,ADC group injected sequencer rank 2 conversion data"
|
|
line.long 0x8 "JDR3,ADC group injected sequencer rank 3 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,ADC group injected sequencer rank 3 conversion data"
|
|
line.long 0xC "JDR4,ADC group injected sequencer rank 4 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,ADC group injected sequencer rank 4 conversion data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel selection"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel selection"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "DIFSEL,ADC channel differential or single-ended mode selection register"
|
|
rbitfld.long 0x0 16.--18. "DIFSEL_16_18,ADC channel differential or single-ended mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 1.--15. 1. "DIFSEL_1_15,ADC channel differential or single-ended mode for channels 1 to 15"
|
|
newline
|
|
rbitfld.long 0x0 0. "DIFSEL_0,ADC channel differential or single-ended mode for channel 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,ADC group injected sequencer register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "JSQ4,ADC group injected sequencer rank 4"
|
|
hexmask.long.byte 0x0 20.--24. 1. "JSQ3,ADC group injected sequencer rank 3"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "JSQ2,ADC group injected sequencer rank 2"
|
|
hexmask.long.byte 0x0 8.--12. 1. "JSQ1,ADC group injected sequencer rank 1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "JEXTEN,ADC group injected external trigger polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "JEXTSEL,ADC group injected external trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan length" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,ADC offset number 1 register"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,ADC offset number 1 enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel selection"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,ADC offset number 1 offset level"
|
|
line.long 0x4 "OFR2,ADC offset number 2 register"
|
|
bitfld.long 0x4 31. "OFFSET2_EN,ADC offset number 2 enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,ADC offset number 2 channel selection"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET2,ADC offset number 2 offset level"
|
|
line.long 0x8 "OFR3,ADC offset number 3 register"
|
|
bitfld.long 0x8 31. "OFFSET3_EN,ADC offset number 3 enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,ADC offset number 3 channel selection"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET3,ADC offset number 3 offset level"
|
|
line.long 0xC "OFR4,ADC offset number 4 register"
|
|
bitfld.long 0xC 31. "OFFSET4_EN,ADC offset number 4 enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,ADC offset number 4 channel selection"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET4,ADC offset number 4 offset level"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,ADC group injected sequencer rank 1 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,ADC group injected sequencer rank 1 conversion data"
|
|
line.long 0x4 "JDR2,ADC group injected sequencer rank 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,ADC group injected sequencer rank 2 conversion data"
|
|
line.long 0x8 "JDR3,ADC group injected sequencer rank 3 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,ADC group injected sequencer rank 3 conversion data"
|
|
line.long 0xC "JDR4,ADC group injected sequencer rank 4 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,ADC group injected sequencer rank 4 conversion data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel selection"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel selection"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "DIFSEL,ADC channel differential or single-ended mode selection register"
|
|
rbitfld.long 0x0 16.--18. "DIFSEL_16_18,ADC channel differential or single-ended mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 1.--15. 1. "DIFSEL_1_15,ADC channel differential or single-ended mode for channels 1 to 15"
|
|
newline
|
|
rbitfld.long 0x0 0. "DIFSEL_0,ADC channel differential or single-ended mode for channel 0" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32WB15*")||cpuis("STM32WB30*")||cpuis("STM32WB35*")||cpuis("STM32WB50*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "AES (AES Hardware Accelerator)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32WB15*")||cpuis("STM32WB30*"))
|
|
tree "AES2"
|
|
base ad:0x58001800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUT,Data output register"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
endif
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Data Output Register (LSB key [31:0])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
endif
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x4 0.--31. 1. "KEY,AES key register (key [63:32])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
endif
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x8 0.--31. 1. "KEY,AES key register (key [95:64])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
endif
|
|
line.long 0xC "KEYR3,key register 3"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0xC 0.--31. 1. "KEY,AES key register (MSB key [127:96])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
endif
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x10 0.--31. 1. "IVI,initialization vector register (LSB IVR [31:0])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
endif
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x14 0.--31. 1. "IVI,Initialization Vector Register (IVR [63:32])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
endif
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x18 0.--31. 1. "IVI,Initialization Vector Register (IVR [95:64])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
endif
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x1C 0.--31. 1. "IVI,Initialization Vector Register (MSB IVR [127:96])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
endif
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x20 0.--31. 1. "KEY,AES key register (MSB key [159:128])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
endif
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x24 0.--31. 1. "KEY,AES key register (MSB key [191:160])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
endif
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x28 0.--31. 1. "KEY,AES key register (MSB key [223:192])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
endif
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x2C 0.--31. 1. "KEY,AES key register (MSB key [255:224])"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
endif
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x30 0.--31. 1. "SUSP0,AES suspend register 0"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
endif
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x34 0.--31. 1. "SUSP1,AES suspend register 1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
endif
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x38 0.--31. 1. "SUSP2,AES suspend register 2"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
endif
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x3C 0.--31. 1. "SUSP3,AES suspend register 3"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
endif
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x40 0.--31. 1. "SUSP4,AES suspend register 4"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
endif
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x44 0.--31. 1. "SUSP5,AES suspend register 5"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
endif
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x48 0.--31. 1. "SUSP6,AES suspend register 6"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
endif
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long 0x4C 0.--31. 1. "SUSP7,AES suspend register 7"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
tree "AES1"
|
|
base ad:0x50060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
tree "AES2"
|
|
base ad:0x58001800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
tree "AES2"
|
|
base ad:0x58001800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "AES1"
|
|
base ad:0x50060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
tree "AES2"
|
|
base ad:0x58001800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "AES1"
|
|
base ad:0x50060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
tree "AES2"
|
|
base ad:0x58001800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of payload"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key [159:128])"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key [191:160])"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key [223:192])"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key [255:224])"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB15*")||cpuis("STM32WB35*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "COMP (Comparator)"
|
|
base ad:0x40010200
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "COMP1_CSR,Comparator control and status register"
|
|
bitfld.long 0x0 31. "COMP1_LOCK,Comparator lock" "0,1"
|
|
rbitfld.long 0x0 30. "COMP1_VALUE,Comparator output level" "0,1"
|
|
bitfld.long 0x0 25.--26. "COMP1_INMESEL,Comparator input minus extended selection" "0,1,2,3"
|
|
bitfld.long 0x0 23. "COMP1_SCALEN,Comparator scaler bridge enable" "0,1"
|
|
bitfld.long 0x0 22. "COMP1_BRGEN,Comparator voltage scaler enable" "0,1"
|
|
bitfld.long 0x0 18.--20. "COMP1_BLANKING,Comparator blanking source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "COMP1_HYST,Comparator hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "COMP1_POLARITY,Comparator output polarity" "0,1"
|
|
bitfld.long 0x0 7.--8. "COMP1_INPSEL,Comparator input plus selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "COMP1_INMSEL,Comparator input minus selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "COMP1_PWRMODE,Comparator power mode" "0,1,2,3"
|
|
bitfld.long 0x0 0. "COMP1_EN,Comparator enable" "0,1"
|
|
line.long 0x4 "COMP2_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x4 31. "COMP2_LOCK,CSR register lock bit" "0,1"
|
|
rbitfld.long 0x4 30. "COMP2_VALUE,Comparator 2 output status bit" "0,1"
|
|
bitfld.long 0x4 25.--26. "COMP2_INMESEL,comparator 2 input minus extended selection bits." "0,1,2,3"
|
|
bitfld.long 0x4 23. "COMP2_SCALEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x4 22. "COMP2_BRGEN,Scaler bridge enable" "0,1"
|
|
bitfld.long 0x4 18.--20. "COMP2_BLANKING,Comparator 2 blanking source selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. "COMP2_HYST,Comparator 2 hysteresis selection bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 15. "COMP2_POLARITY,Comparator 2 polarity selection bit" "0,1"
|
|
bitfld.long 0x4 9. "COMP2_WINMODE,Windows mode selection bit" "0,1"
|
|
bitfld.long 0x4 7.--8. "COMP2_INPSEL,Comparator 1 input plus selection bit" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "COMP2_INMSEL,Comparator 2 input minus selection bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "COMP2_PWRMODE,Power Mode of the comparator 2" "0,1,2,3"
|
|
bitfld.long 0x4 0. "COMP2_EN,Comparator 2 enable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
tree.end
|
|
sif (cpuis("STM32WB35*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "CRS (Clock Recovery System)"
|
|
base ad:0x40006000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,CRS control register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming"
|
|
bitfld.long 0x0 7. "SWSYNC,Automatic trimming enable" "0,1"
|
|
bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0,1"
|
|
bitfld.long 0x0 5. "CEN,Frequency error counter enable" "0,1"
|
|
bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt enable" "0,1"
|
|
line.long 0x4 "CFGR,CRS configuration register"
|
|
bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0,1"
|
|
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection" "0,1,2,3"
|
|
bitfld.long 0x4 24.--26. "SYNCDIV,SYNCDIV" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit"
|
|
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ISR,CRS interrupt and status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture"
|
|
bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0,1"
|
|
bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow" "0,1"
|
|
bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0,1"
|
|
bitfld.long 0x0 8. "SYNCERR,SYNC error" "0,1"
|
|
bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0,1"
|
|
bitfld.long 0x0 2. "ERRF,Error flag" "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "ICR,CRS interrupt flag clear register"
|
|
bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1"
|
|
bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNC,warning clear flag" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "DBGMCU (MCU Debug Component)"
|
|
base ad:0xE0042000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "IDCODE,MCU Device ID Code Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision Identifier"
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device Identifier"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CR,Debug MCU Configuration Register"
|
|
bitfld.long 0x0 28. "TRGOEN,External trigger output enable" "0,1"
|
|
bitfld.long 0x0 5. "TRACE_IOEN,Trace port and clock enable" "0,1"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby Mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
bitfld.long 0x0 0. "DBG_SLEEP,Debug Sleep Mode" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "APB1FZR1,APB1 Low Freeze Register CPU1"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,Debug LPTIM1 stopped when Core is halted" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,Debug I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,Debug I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,Debug I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,Debug I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,Debug I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,Debug I2C1 SMBUS timeout stopped when Core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 11. "DBG_WWDG_STOP,WWDG counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 0. "DBG_TIM2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2APB1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DBG_TIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2AP_B1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 0. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2AP_B1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 0. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2AP_B1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 0. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2AP_B1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 0. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "C2AP_B1FZR1,APB1 Low Freeze Register CPU2"
|
|
bitfld.long 0x0 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 12. "DBG_IWDG_STOP,IWDG stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 0. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "C2APB2FZR,APB2 Freeze Register CPU2"
|
|
bitfld.long 0x0 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x0 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
endif
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "APB1FZR2,APB1 High Freeze Register CPU1"
|
|
bitfld.long 0x0 5. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
line.long 0x4 "C2APB1FZR2,APB1 High Freeze Register CPU2"
|
|
bitfld.long 0x4 5. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
line.long 0x8 "APB2FZR,APB2 Freeze Register CPU1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
endif
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA1"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR1,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR1,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR2,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR2,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR3,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR3,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR4,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR4,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR5,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR5,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR6,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR6,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR7,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR7,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
tree.end
|
|
sif (cpuis("STM32WB35*"))
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR1,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR1,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR2,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR2,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR3,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR3,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR4,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR4,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR5,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR5,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR6,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR6,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR7,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR7,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CSELR,channel selection register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "C7S,DMA channel 7 selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "C6S,DMA channel 6 selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "C5S,DMA channel 5 selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "C4S,DMA channel 4 selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "C3S,DMA channel 3 selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C2S,DMA channel 2 selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "C1S,DMA channel 1 selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR1,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR1,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR2,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR2,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR3,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR3,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR4,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR4,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR5,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR5,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR6,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR6,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR7,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR7,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CSELR,channel selection register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "C7S,DMA channel 7 selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "C6S,DMA channel 6 selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "C5S,DMA channel 5 selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "C4S,DMA channel 4 selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "C3S,DMA channel 3 selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C2S,DMA channel 2 selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "C1S,DMA channel 1 selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR1,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR1,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR2,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR2,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR3,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR3,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR4,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR4,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR5,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR5,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR6,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR6,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR7,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR7,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CSELR,channel selection register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "C7S,DMA channel 7 selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "C6S,DMA channel 6 selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "C5S,DMA channel 5 selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "C4S,DMA channel 4 selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "C3S,DMA channel 3 selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C2S,DMA channel 2 selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "C1S,DMA channel 1 selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR1,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR1,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR2,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR2,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR3,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR3,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR4,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR4,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR5,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR5,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR6,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR6,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,channel x configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0,1"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0,1"
|
|
line.long 0x4 "CNDTR7,channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
|
|
line.long 0x8 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "CMAR7,channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CSELR,channel selection register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "C7S,DMA channel 7 selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "C6S,DMA channel 6 selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "C5S,DMA channel 5 selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "C4S,DMA channel 4 selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "C3S,DMA channel 3 selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C2S,DMA channel 2 selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "C1S,DMA channel 1 selection"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "DMAMUX (DMA Request Multiplexer)"
|
|
base ad:0x40020800
|
|
group.long 0x0++0x37
|
|
line.long 0x0 "C0CR,DMA Multiplexer Channel 0 Control register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x0 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x0 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x4 "C1CR,DMA Multiplexer Channel 1 Control register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x4 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x4 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x8 "C2CR,DMA Multiplexer Channel 2 Control register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x8 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x8 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0xC "C3CR,DMA Multiplexer Channel 3 Control register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0xC 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0xC 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x10 "C4CR,DMA Multiplexer Channel 4 Control register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x10 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x10 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x14 "C5CR,DMA Multiplexer Channel 5 Control register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x14 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x14 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x18 "C6CR,DMA Multiplexer Channel 6 Control register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x18 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x18 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x1C "C7CR,DMA Multiplexer Channel 7 Control register"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x1C 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x1C 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x1C 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x1C 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x20 "C8CR,DMA Multiplexer Channel 8 Control register"
|
|
hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x20 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x20 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x20 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x20 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x24 "C9CR,DMA Multiplexer Channel 9 Control register"
|
|
hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x24 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x24 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x24 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x24 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x28 "C10CR,DMA Multiplexer Channel 10 Control register"
|
|
hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x28 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x28 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x28 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x28 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x2C "C11CR,DMA Multiplexer Channel 11 Control register"
|
|
hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x2C 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x2C 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x2C 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x2C 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x30 "C12CR,DMA Multiplexer Channel 12 Control register"
|
|
hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x30 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x30 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x30 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x30 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
line.long 0x34 "C13CR,DMA Multiplexer Channel 13 Control register"
|
|
hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,SYNC_ID"
|
|
hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Nb request"
|
|
bitfld.long 0x34 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x34 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x34 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x34 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,DMA Request ID"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "CSR,DMA Multiplexer Channel Status register"
|
|
bitfld.long 0x0 13. "SOF13,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x0 12. "SOF12,Synchronization Overrun Flag 12" "0,1"
|
|
bitfld.long 0x0 11. "SOF11,Synchronization Overrun Flag 11" "0,1"
|
|
bitfld.long 0x0 10. "SOF10,Synchronization Overrun Flag 10" "0,1"
|
|
bitfld.long 0x0 9. "SOF9,Synchronization Overrun Flag 9" "0,1"
|
|
bitfld.long 0x0 8. "SOF8,Synchronization Overrun Flag 8" "0,1"
|
|
bitfld.long 0x0 7. "SOF7,Synchronization Overrun Flag 7" "0,1"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization Overrun Flag 6" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization Overrun Flag 5" "0,1"
|
|
bitfld.long 0x0 4. "SOF4,Synchronization Overrun Flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SOF3,Synchronization Overrun Flag 3" "0,1"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization Overrun Flag 2" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization Overrun Flag 1" "0,1"
|
|
bitfld.long 0x0 0. "SOF0,Synchronization Overrun Flag 0" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "CFR,DMA Channel Clear Flag Register"
|
|
bitfld.long 0x0 13. "CSOF13,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x0 12. "CSOF12,Synchronization Clear Overrun Flag 12" "0,1"
|
|
bitfld.long 0x0 11. "CSOF11,Synchronization Clear Overrun Flag 11" "0,1"
|
|
bitfld.long 0x0 10. "CSOF10,Synchronization Clear Overrun Flag 10" "0,1"
|
|
bitfld.long 0x0 9. "CSOF9,Synchronization Clear Overrun Flag 9" "0,1"
|
|
bitfld.long 0x0 8. "CSOF8,Synchronization Clear Overrun Flag 8" "0,1"
|
|
bitfld.long 0x0 7. "CSOF7,Synchronization Clear Overrun Flag 7" "0,1"
|
|
bitfld.long 0x0 6. "CSOF6,Synchronization Clear Overrun Flag 6" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Synchronization Clear Overrun Flag 5" "0,1"
|
|
bitfld.long 0x0 4. "CSOF4,Synchronization Clear Overrun Flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSOF3,Synchronization Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x0 2. "CSOF2,Synchronization Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Synchronization Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x0 0. "CSOF0,Synchronization Clear Overrun Flag 0" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "RG0CR,DMA Request Generator 0 Control Register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of Request"
|
|
bitfld.long 0x0 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x0 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal ID"
|
|
line.long 0x4 "RG1CR,DMA Request Generator 1 Control Register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of Request"
|
|
bitfld.long 0x4 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal ID"
|
|
line.long 0x8 "RG2CR,DMA Request Generator 2 Control Register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of Request"
|
|
bitfld.long 0x8 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x8 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal ID"
|
|
line.long 0xC "RG3CR,DMA Request Generator 3 Control Register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of Request"
|
|
bitfld.long 0xC 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0xC 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal ID"
|
|
rgroup.long 0x140++0x7
|
|
line.long 0x0 "RGSR,DMA Request Generator Status Register"
|
|
bitfld.long 0x0 3. "OF3,Generator Overrun Flag 3" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Generator Overrun Flag 2" "0,1"
|
|
bitfld.long 0x0 1. "OF1,Generator Overrun Flag 1" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Generator Overrun Flag 0" "0,1"
|
|
line.long 0x4 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 3. "CSOF3,Generator Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "CSOF2,Generator Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x4 1. "CSOF1,Generator Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "CSOF0,Generator Clear Overrun Flag 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 3. "COF3,Clear trigger Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "COF2,Clear trigger Overrun Flag 2" "0,1"
|
|
bitfld.long 0x4 1. "COF1,Clear trigger Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "COF0,Clear trigger Overrun Flag 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 3. "COF3,Clear trigger Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "COF2,Clear trigger Overrun Flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "COF1,Clear trigger Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "COF0,Clear trigger Overrun Flag 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 3. "COF3,Clear trigger Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "COF2,Clear trigger Overrun Flag 2" "0,1"
|
|
bitfld.long 0x4 1. "COF1,Clear trigger Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "COF0,Clear trigger Overrun Flag 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 3. "COF3,Clear trigger Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "COF2,Clear trigger Overrun Flag 2" "0,1"
|
|
bitfld.long 0x4 1. "COF1,Clear trigger Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "COF0,Clear trigger Overrun Flag 0" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 3. "COF3,Clear trigger Overrun Flag 3" "0,1"
|
|
bitfld.long 0x4 2. "COF2,Clear trigger Overrun Flag 2" "0,1"
|
|
bitfld.long 0x4 1. "COF1,Clear trigger Overrun Flag 1" "0,1"
|
|
bitfld.long 0x4 0. "COF0,Clear trigger Overrun Flag 0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
endif
|
|
tree.end
|
|
tree "EXTI (Extended Interrupt and Event Controller)"
|
|
base ad:0x58000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "RTSR1,rising trigger selection register"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 31. "RT_31,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 31. "RT_31,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 31. "RT_31,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 31. "RT_31,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 31. "RT_31,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RT,Rising trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
line.long 0x4 "FTSR1,falling trigger selection register"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 31. "FT_31,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 31. "FT_31,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 31. "FT_31,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 31. "FT_31,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 31. "FT_31,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0x4 0.--20. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FT,Falling trigger event configuration bit of Configurable Event input"
|
|
endif
|
|
line.long 0x8 "SWIER1,software interrupt event register"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 31. "SWI_31,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 31. "SWI_31,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 31. "SWI_31,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 31. "SWI_31,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 31. "SWI_31,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0x8 0.--20. 1. "SWI,Software interrupt on event"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "SWI,Software interrupt on event"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "SWI,Software interrupt on event"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "SWI,Software interrupt on event"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "SWI,Software interrupt on event"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "SWI,Software interrupt on event"
|
|
endif
|
|
line.long 0xC "PR1,EXTI pending register"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 31. "PIF_31,Configurable event inputs Pending bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 31. "PIF_31,Configurable event inputs Pending bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 31. "PIF_31,Configurable event inputs Pending bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 31. "PIF_31,Configurable event inputs Pending bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 31. "PIF_31,Configurable event inputs Pending bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0xC 0.--20. 1. "PIF,Configurable event inputs Pending bit"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0xC 0.--21. 1. "PIF,Configurable event inputs Pending bit"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0xC 0.--21. 1. "PIF,Configurable event inputs Pending bit"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0xC 0.--21. 1. "PIF,Configurable event inputs Pending bit"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0xC 0.--21. 1. "PIF,Configurable event inputs Pending bit"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0xC 0.--21. 1. "PIF,Configurable event inputs Pending bit"
|
|
endif
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "RTSR2,rising trigger selection register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 9. "RT41,Rising trigger event configuration bit of Configurable Event input 41" "0,1"
|
|
bitfld.long 0x0 8. "RT40,Rising trigger event configuration bit of Configurable Event input 40" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 8.--9. "RT40_41,Rising trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 8.--9. "RT40_41,Rising trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 8.--9. "RT40_41,Rising trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 8.--9. "RT40_41,Rising trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 8.--9. "RT40_41,Rising trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 1. "RT33,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x4 "FTSR2,falling trigger selection register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 9. "FT41,Falling trigger event configuration bit of configurable event input 41" "0,1"
|
|
bitfld.long 0x4 8. "FT40,Falling trigger event configuration bit of configurable event input 40" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 8.--9. "FT40_41,Falling trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 8.--9. "FT40_41,Falling trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 8.--9. "FT40_41,Falling trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 8.--9. "FT40_41,Falling trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 8.--9. "FT40_41,Falling trigger event configuration bit of Configurable Event input" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x4 1. "FT33,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x8 "SWIER2,software interrupt event register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x8 9. "SWI41,Software interrupt on event" "0,1"
|
|
bitfld.long 0x8 8. "SWI40,Software interrupt on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 8.--9. "SWI40_41,Software interrupt on event" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 8.--9. "SWI40_41,Software interrupt on event" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 8.--9. "SWI40_41,Software interrupt on event" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 8.--9. "SWI40_41,Software interrupt on event" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 8.--9. "SWI40_41,Software interrupt on event" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x8 1. "SWI33,Software interrupt on event" "0,1"
|
|
line.long 0xC "PR2,pending register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0xC 9. "PIF41,Configurable event inputs x+32 Pending bit." "0,1"
|
|
bitfld.long 0xC 8. "PIF40,Configurable event inputs x+32 Pending bit." "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 8.--9. "PIF40_41,Configurable event inputs x+32 Pending bit." "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 8.--9. "PIF40_41,Configurable event inputs x+32 Pending bit." "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 8.--9. "PIF40_41,Configurable event inputs x+32 Pending bit." "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 8.--9. "PIF40_41,Configurable event inputs x+32 Pending bit." "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 8.--9. "PIF40_41,Configurable event inputs x+32 Pending bit." "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 1. "PIF33,Configurable event inputs x+32 Pending bit." "0,1"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--20. 1. "EM17_20,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 1.--17. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "C1IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "C1IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
rgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HWCFGR6,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x0 "HWCFGR3,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "C1IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "C1IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "HWCFGR5,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x0 "HWCFGR3,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "C1IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "C1IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "HWCFGR5,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x0 "HWCFGR3,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "C1IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "C1IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "HWCFGR5,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x0 "HWCFGR3,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "C1IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR1,CPUm wakeup with event mask register"
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "C1IMR2,CPUm wakeup with interrupt mask register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C1EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "HWCFGR5,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x0 "HWCFGR3,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "C2IMR1,CPUm wakeup with interrupt mask register"
|
|
hexmask.long 0x0 0.--31. 1. "IM,CPU(m) wakeup with interrupt Mask on Event input"
|
|
line.long 0x4 "C2EMR1,CPUm wakeup with event mask register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.byte 0x4 17.--20. 1. "EM17_20,CPU(m) Wakeup with event generation Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x4 17.--21. 1. "EM17_21,CPU(m) Wakeup with event generation Mask on Event input"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x4 0.--15. 1. "EM0_15,CPU(m) Wakeup with event generation Mask on Event input"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "C2IMR2,CPUm wakeup with interrupt mask register"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0x0 1.--17. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0x0 0.--16. 1. "IM,CPUm Wakeup with interrupt Mask on Event input"
|
|
endif
|
|
line.long 0x4 "C2EMR2,CPUm wakeup with event mask register"
|
|
bitfld.long 0x4 8.--9. "EM,CPU(m) Wakeup with event generation Mask on Event input" "0,1,2,3"
|
|
sif (cpuis("STM32WB30*"))
|
|
rgroup.long 0x3E0++0x7
|
|
line.long 0x0 "HWCFGR5,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
line.long 0x4 "HWCFGR4,Hardware configuration registers"
|
|
hexmask.long 0x4 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
rgroup.long 0x3D8++0x3
|
|
line.long 0x0 "HWCFGR7,EXTI Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
line.long 0x4 "HWCFGR1,Hardware configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CPUEVTEN,HW configuration of CPU(m) event output enable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBCPUS,HW configuration number of CPUs"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBEVENTS,HW configuration number of event"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
rgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HWCFGR6,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E4++0x3
|
|
line.long 0x0 "HWCFGR4,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
rgroup.long 0x3D8++0x3
|
|
line.long 0x0 "HWCFGR7,EXTI Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
line.long 0x4 "HWCFGR1,Hardware configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CPUEVTEN,HW configuration of CPU(m) event output enable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBCPUS,HW configuration number of CPUs"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBEVENTS,HW configuration number of event"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
rgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HWCFGR6,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E4++0x3
|
|
line.long 0x0 "HWCFGR4,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
rgroup.long 0x3D8++0x3
|
|
line.long 0x0 "HWCFGR7,EXTI Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
line.long 0x4 "HWCFGR1,Hardware configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CPUEVTEN,HW configuration of CPU(m) event output enable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBCPUS,HW configuration number of CPUs"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBEVENTS,HW configuration number of event"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
rgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HWCFGR6,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E4++0x3
|
|
line.long 0x0 "HWCFGR4,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
rgroup.long 0x3D8++0x3
|
|
line.long 0x0 "HWCFGR7,EXTI Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
line.long 0x4 "HWCFGR1,Hardware configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CPUEVTEN,HW configuration of CPU(m) event output enable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBCPUS,HW configuration number of CPUs"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBEVENTS,HW configuration number of event"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
rgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HWCFGR6,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3E4++0x3
|
|
line.long 0x0 "HWCFGR4,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
rgroup.long 0x3D8++0x3
|
|
line.long 0x0 "HWCFGR7,EXTI Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event generation"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Hardware configuration registers"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_TRG,HW configuration event trigger type"
|
|
line.long 0x4 "HWCFGR1,Hardware configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CPUEVTEN,HW configuration of CPU(m) event output enable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBCPUS,HW configuration number of CPUs"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBEVENTS,HW configuration number of event"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
tree.end
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x58004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ACR,Access control register"
|
|
bitfld.long 0x0 16. "EMPTY,Flash User area empty" "0,1"
|
|
bitfld.long 0x0 15. "PES,CPU1 CortexM4 program erase suspend request" "0,1"
|
|
bitfld.long 0x0 12. "DCRST,Data cache reset" "0,1"
|
|
bitfld.long 0x0 11. "ICRST,Instruction cache reset" "0,1"
|
|
bitfld.long 0x0 10. "DCEN,Data cache enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ICEN,Instruction cache enable" "0,1"
|
|
bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "LATENCY,Latency" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "KEYR,Flash key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYR,KEYR"
|
|
line.long 0x4 "OPTKEYR,Option byte key register"
|
|
hexmask.long 0x4 0.--31. 1. "OPTKEYR,Option byte key"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SR,Status register"
|
|
rbitfld.long 0x0 19. "PESD,Programming or erase operation suspended" "0,1"
|
|
rbitfld.long 0x0 18. "CFGBSY,Programming or erase configuration busy" "0,1"
|
|
rbitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
bitfld.long 0x0 15. "OPTVERR,Option validity error" "0,1"
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 13. "OPTNV,User Option OPTVAL indication" "0,1"
|
|
bitfld.long 0x0 9. "FASTERR,Fast programming error" "0,1"
|
|
bitfld.long 0x0 8. "MISERR,Fast programming data miss error" "0,1"
|
|
bitfld.long 0x0 7. "PGSERR,Programming sequence error" "0,1"
|
|
bitfld.long 0x0 6. "SIZERR,Size error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PGAERR,Programming alignment error" "0,1"
|
|
bitfld.long 0x0 4. "WRPERR,Write protected error" "0,1"
|
|
bitfld.long 0x0 3. "PROGERR,Programming error" "0,1"
|
|
bitfld.long 0x0 1. "OPERR,Operation error" "0,1"
|
|
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
|
|
line.long 0x4 "CR,Flash control register"
|
|
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
|
|
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,Force the option byte loading" "0,1"
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt enable" "0,1"
|
|
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "EOPIE,End of operation interrupt enable" "0,1"
|
|
bitfld.long 0x4 18. "FSTPG,Fast programming" "0,1"
|
|
bitfld.long 0x4 17. "OPTSTRT,Options modification start" "0,1"
|
|
bitfld.long 0x4 16. "STRT,Start" "0,1"
|
|
hexmask.long.byte 0x4 3.--10. 1. "PNB,Page number selection"
|
|
newline
|
|
bitfld.long 0x4 2. "MER,This bit triggers the mass erase (all user pages) when set" "0,1"
|
|
bitfld.long 0x4 1. "PER,Page erase" "0,1"
|
|
bitfld.long 0x4 0. "PG,Programming" "0,1"
|
|
line.long 0x8 "ECCR,Flash ECC register"
|
|
bitfld.long 0x8 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x8 30. "ECCC,ECC correction" "0,1"
|
|
rbitfld.long 0x8 26.--28. "CPUID,CPU identification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "ECCCIE,ECC correction interrupt enable" "0,1"
|
|
rbitfld.long 0x8 20. "SYSF_ECC,System Flash ECC fail" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "ADDR_ECC,ECC fail address"
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "OPTR,Flash option register"
|
|
bitfld.long 0x0 29.--31. "AGC_TRIM,Radio Automatic Gain Control Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 27. "nBOOT0,nBoot0 option bit" "0,1"
|
|
bitfld.long 0x0 26. "nSWBOOT0,Software Boot0" "0,1"
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
bitfld.long 0x0 24. "SRAM2_PE,SRAM2 parity check enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "nBOOT1,Boot configuration" "0,1"
|
|
bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0,1"
|
|
bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0,1"
|
|
bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0,1"
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "nRST_SHDW,nRST_SHDW" "0,1"
|
|
bitfld.long 0x0 13. "nRST_STDBY,nRST_STDBY" "0,1"
|
|
bitfld.long 0x0 12. "nRST_STOP,nRST_STOP" "0,1"
|
|
bitfld.long 0x0 9.--11. "BOR_LEV,BOR reset Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8. "ESE,Security enabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDP,Read protection level"
|
|
line.long 0x4 "PCROP1ASR,Flash Bank 1 PCROP Start address zone A register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP1A_STRT,Bank 1 PCROPQ area start offset"
|
|
line.long 0x8 "PCROP1AER,Flash Bank 1 PCROP End address zone A register"
|
|
bitfld.long 0x8 31. "PCROP_RDP,PCROP area preserved when RDP level decreased" "0,1"
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP1A_END,Bank 1 PCROP area end offset"
|
|
line.long 0xC "WRP1AR,Flash Bank 1 WRP area A address register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "WRP1A_END,Bank 1 WRP first area A end offset"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WRP1A_STRT,Bank 1 WRP first area A start offset"
|
|
line.long 0x10 "WRP1BR,Flash Bank 1 WRP area B address register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "WRP1B_STRT,Bank 1 WRP second area B end offset"
|
|
hexmask.long.byte 0x10 0.--7. 1. "WRP1B_END,Bank 1 WRP second area B start offset"
|
|
line.long 0x14 "PCROP1BSR,Flash Bank 1 PCROP Start address area B register"
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP1B_STRT,Bank 1 PCROP area B start offset"
|
|
line.long 0x18 "PCROP1BER,Flash Bank 1 PCROP End address area B register"
|
|
hexmask.long.word 0x18 0.--8. 1. "PCROP1B_END,Bank 1 PCROP area end area B offset"
|
|
line.long 0x1C "IPCCBR,IPCC mailbox data buffer address register"
|
|
hexmask.long.word 0x1C 0.--13. 1. "IPCCDBA,PCC mailbox data buffer base address"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "C2ACR,CPU2 cortex M0 access control register"
|
|
bitfld.long 0x0 15. "PES,CPU2 cortex M0 program erase suspend request" "0,1"
|
|
bitfld.long 0x0 11. "ICRST,CPU2 cortex M0 instruction cache reset" "0,1"
|
|
bitfld.long 0x0 9. "ICEN,CPU2 cortex M0 instruction cache enable" "0,1"
|
|
bitfld.long 0x0 8. "PRFTEN,CPU2 cortex M0 prefetch enable" "0,1"
|
|
line.long 0x4 "C2SR,CPU2 cortex M0 status register"
|
|
bitfld.long 0x4 19. "PESD,Programming or erase operation suspended" "0,1"
|
|
bitfld.long 0x4 18. "CFGBSY,Programming or erase configuration busy" "0,1"
|
|
bitfld.long 0x4 16. "BSY,Busy" "0,1"
|
|
bitfld.long 0x4 14. "RDERR,PCROP read error" "0,1"
|
|
bitfld.long 0x4 9. "FASTERR,Fast programming error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MISSERR,Fast programming data miss error" "0,1"
|
|
bitfld.long 0x4 7. "PGSERR,Programming sequence error" "0,1"
|
|
bitfld.long 0x4 6. "SIZERR,Size error" "0,1"
|
|
bitfld.long 0x4 5. "PGAERR,Programming alignment error" "0,1"
|
|
bitfld.long 0x4 4. "WRPERR,write protection error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PROGERR,Programming error" "0,1"
|
|
bitfld.long 0x4 1. "OPERR,Operation error" "0,1"
|
|
bitfld.long 0x4 0. "EOP,End of operation" "0,1"
|
|
line.long 0x8 "C2CR,CPU2 cortex M0 control register"
|
|
bitfld.long 0x8 26. "RDERRIE,PCROP read error interrupt enable" "0,1"
|
|
bitfld.long 0x8 25. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x8 24. "EOPIE,End of operation interrupt enable" "0,1"
|
|
bitfld.long 0x8 18. "FSTPG,Fast programming" "0,1"
|
|
bitfld.long 0x8 16. "STRT,Start" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 3.--10. 1. "PNB,Page Number selection"
|
|
bitfld.long 0x8 2. "MER,Masse erase" "0,1"
|
|
bitfld.long 0x8 1. "PER,Page erase" "0,1"
|
|
bitfld.long 0x8 0. "PG,Programming" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "SFR,Secure flash start address register"
|
|
bitfld.long 0x0 12. "DDS,Disable Cortex M0 debug access" "0,1"
|
|
bitfld.long 0x0 8. "FSD,Flash security disable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SFSA,Secure flash start address"
|
|
line.long 0x4 "SRRVR,Secure SRAM2 start address and cortex M0 reset vector register"
|
|
bitfld.long 0x4 31. "C2OPT,CPU2 cortex M0 boot reset vector memory selection" "0,1"
|
|
bitfld.long 0x4 30. "NBRSD,non-backup SRAM2b security disable" "0,1"
|
|
hexmask.long.byte 0x4 25.--29. 1. "SNBRSA,Secure non backup SRAM2a start address"
|
|
bitfld.long 0x4 23. "BRSD,backup SRAM2a security disable" "0,1"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SBRSA,Secure backup SRAM2a start address"
|
|
newline
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "SBRV,cortex M0 access control register"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "SBRV,cortex M0 access control register"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "SBRV,cortex M0 access control register"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "SBRV,cortex M0 access control register"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "SBRV,cortex M0 access control register"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "SBRV,cortex M0 access control register"
|
|
endif
|
|
tree.end
|
|
tree "GPIO (General-Purpose I/Os)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x48000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x48000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x48000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "GPIOD"
|
|
base ad:0x48000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "GPIOD"
|
|
base ad:0x48000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "GPIOE"
|
|
base ad:0x48001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOH"
|
|
base ad:0x48001C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "HSEM (Hardware Semaphore)"
|
|
base ad:0x58001400
|
|
group.long 0x0++0x7F
|
|
line.long 0x0 "R0,Semaphore 0 register"
|
|
bitfld.long 0x0 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x4 "R1,Semaphore 1 register"
|
|
bitfld.long 0x4 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x8 "R2,Semaphore 2 register"
|
|
bitfld.long 0x8 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0xC "R3,Semaphore 3 register"
|
|
bitfld.long 0xC 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x10 "R4,Semaphore 4 register"
|
|
bitfld.long 0x10 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x14 "R5,Semaphore 5 register"
|
|
bitfld.long 0x14 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x18 "R6,Semaphore 6 register"
|
|
bitfld.long 0x18 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x1C "R7,Semaphore 7 register"
|
|
bitfld.long 0x1C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x20 "R8,Semaphore 8 register"
|
|
bitfld.long 0x20 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x24 "R9,Semaphore 9 register"
|
|
bitfld.long 0x24 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x28 "R10,Semaphore 10 register"
|
|
bitfld.long 0x28 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x2C "R11,Semaphore 11 register"
|
|
bitfld.long 0x2C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x30 "R12,Semaphore 12 register"
|
|
bitfld.long 0x30 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x34 "R13,Semaphore 13 register"
|
|
bitfld.long 0x34 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x38 "R14,Semaphore 14 register"
|
|
bitfld.long 0x38 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x3C "R15,Semaphore 15 register"
|
|
bitfld.long 0x3C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x40 "R16,Semaphore 16 register"
|
|
bitfld.long 0x40 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x44 "R17,Semaphore 17 register"
|
|
bitfld.long 0x44 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x48 "R18,Semaphore 18 register"
|
|
bitfld.long 0x48 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x4C "R19,Semaphore 19 register"
|
|
bitfld.long 0x4C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x50 "R20,Semaphore 20 register"
|
|
bitfld.long 0x50 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x54 "R21,Semaphore 21 register"
|
|
bitfld.long 0x54 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x58 "R22,Semaphore 22 register"
|
|
bitfld.long 0x58 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x5C "R23,Semaphore 23 register"
|
|
bitfld.long 0x5C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x60 "R24,Semaphore 24 register"
|
|
bitfld.long 0x60 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x64 "R25,Semaphore 25 register"
|
|
bitfld.long 0x64 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x68 "R26,Semaphore 26 register"
|
|
bitfld.long 0x68 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x6C "R27,Semaphore 27 register"
|
|
bitfld.long 0x6C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x70 "R28,Semaphore 28 register"
|
|
bitfld.long 0x70 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x74 "R29,Semaphore 29 register"
|
|
bitfld.long 0x74 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x78 "R30,Semaphore 30 register"
|
|
bitfld.long 0x78 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x7C "R31,Semaphore 31 register"
|
|
bitfld.long 0x7C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
rgroup.long 0x80++0x7F
|
|
line.long 0x0 "RLR0,Semaphore 0 read lock register"
|
|
bitfld.long 0x0 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x4 "RLR1,Semaphore 1 read lock register"
|
|
bitfld.long 0x4 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x8 "RLR2,Semaphore 2 read lock register"
|
|
bitfld.long 0x8 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0xC "RLR3,Semaphore 3 read lock register"
|
|
bitfld.long 0xC 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x10 "RLR4,Semaphore 4 read lock read lock register"
|
|
bitfld.long 0x10 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x14 "RLR5,Semaphore 5 read lock register"
|
|
bitfld.long 0x14 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x18 "RLR6,Semaphore 6 read lock register"
|
|
bitfld.long 0x18 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x1C "RLR7,Semaphore 7 read lock register"
|
|
bitfld.long 0x1C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x20 "RLR8,Semaphore 8 read lock register"
|
|
bitfld.long 0x20 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x24 "RLR9,Semaphore 9 read lock register"
|
|
bitfld.long 0x24 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x28 "RLR10,Semaphore 10 read lock register"
|
|
bitfld.long 0x28 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x2C "RLR11,Semaphore 11 read lock register"
|
|
bitfld.long 0x2C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x30 "RLR12,Semaphore 12 read lock register"
|
|
bitfld.long 0x30 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x34 "RLR13,Semaphore 13 read lock register"
|
|
bitfld.long 0x34 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x38 "RLR14,Semaphore 14 read lock register"
|
|
bitfld.long 0x38 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x3C "RLR15,Semaphore 15 read lock register"
|
|
bitfld.long 0x3C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x40 "RLR16,Semaphore 16 read lock register"
|
|
bitfld.long 0x40 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x44 "RLR17,Semaphore 17 read lock register"
|
|
bitfld.long 0x44 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x48 "RLR18,Semaphore 18 read lock register"
|
|
bitfld.long 0x48 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x4C "RLR19,Semaphore 19 read lock register"
|
|
bitfld.long 0x4C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x50 "RLR20,Semaphore 20 read lock register"
|
|
bitfld.long 0x50 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x54 "RLR21,Semaphore 21 read lock register"
|
|
bitfld.long 0x54 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x58 "RLR22,Semaphore 22 read lock register"
|
|
bitfld.long 0x58 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x5C "RLR23,Semaphore 23 read lock register"
|
|
bitfld.long 0x5C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x60 "RLR24,Semaphore 24 read lock register"
|
|
bitfld.long 0x60 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x64 "RLR25,Semaphore 25 read lock register"
|
|
bitfld.long 0x64 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x68 "RLR26,Semaphore 26 read lock register"
|
|
bitfld.long 0x68 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x6C "RLR27,Semaphore 27 read lock register"
|
|
bitfld.long 0x6C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x70 "RLR28,Semaphore 28 read lock register"
|
|
bitfld.long 0x70 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x74 "RLR29,Semaphore 29 read lock register"
|
|
bitfld.long 0x74 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x78 "RLR30,Semaphore 30 read lock register"
|
|
bitfld.long 0x78 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
line.long 0x7C "RLR31,Semaphore 31 read lock register"
|
|
bitfld.long 0x7C 31. "LOCK,lock indication" "0,1"
|
|
hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore CoreID"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID"
|
|
group.long 0x140++0x7
|
|
line.long 0x0 "CR,Semaphore Clear register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key"
|
|
hexmask.long.byte 0x0 8.--11. 1. "COREID,CoreID of semaphore to be cleared"
|
|
line.long 0x4 "KEYR,Interrupt clear register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Semaphore Clear Key"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,Semaphore hardware configuration register 2"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MASTERID4,Hardware Configuration valid bus masters ID4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MASTERID3,Hardware Configuration valid bus masters ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MASTERID2,Hardware Configuration valid bus masters ID2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MASTERID1,Hardware Configuration valid bus masters ID1"
|
|
line.long 0x4 "HWCFGR1,Semaphore hardware configuration register 1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "NBINT,Hardware Configuration number of interrupts supported number of master IDs"
|
|
hexmask.long.byte 0x4 0.--7. 1. "NBSEM,Hardware Configuration number of semaphores"
|
|
line.long 0x8 "VERR,HSEM version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0xC "IPIDR,HSEM indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Identification Code"
|
|
line.long 0x10 "SIDR,HSEM size indentification register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification Code"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "C1IER0,HSEM Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "ISEm,CPU(n) semaphore m enable bit"
|
|
line.long 0x4 "C1ICR,HSEM Interrupt clear register"
|
|
hexmask.long 0x4 0.--31. 1. "ISCm,CPU(n) semaphore m clear bit"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x0 "C1ISR,HSEM Interrupt status register"
|
|
hexmask.long 0x0 0.--31. 1. "ISFm,CPU(n) semaphore m status bit before enable (mask)"
|
|
line.long 0x4 "C1MISR,HSEM Masked interrupt status register"
|
|
hexmask.long 0x4 0.--31. 1. "MISFm,masked CPU(n) semaphore m status bit after enable (mask)."
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "C2IER0,HSEM Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "ISEm,CPU(2) semaphore m enable bit."
|
|
line.long 0x4 "C2ICR,HSEM Interrupt clear register"
|
|
hexmask.long 0x4 0.--31. 1. "ISCm,CPU(2) semaphore m clear bit"
|
|
rgroup.long 0x118++0x7
|
|
line.long 0x0 "C2ISR,HSEM Interrupt status register"
|
|
hexmask.long 0x0 0.--31. 1. "ISFm,CPU(2) semaphore m status bit before enable (mask)."
|
|
line.long 0x4 "C2MISR,HSEM Masked interrupt status register"
|
|
hexmask.long 0x4 0.--31. 1. "MISFm,masked CPU(2) semaphore m status bit after enable (mask)."
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
sif (cpuis("STM32WB35*"))
|
|
tree "I2C3"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "I2C3"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "I2C3"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IPCC (Inter-Processor Communication Controller)"
|
|
base ad:0x58000C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "C1CR,Control register CPU1"
|
|
bitfld.long 0x0 16. "TXFIE,processor 1 Transmit channel free interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "RXOIE,processor 1 Receive channel occupied interrupt enable" "0,1"
|
|
line.long 0x4 "C1MR,Mask register CPU1"
|
|
bitfld.long 0x4 21. "CH6FM,processor 1 Transmit channel 6 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "CH5FM,processor 1 Transmit channel 5 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 19. "CH4FM,processor 1 Transmit channel 4 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "CH3FM,processor 1 Transmit channel 3 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 17. "CH2FM,processor 1 Transmit channel 2 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "CH1FM,processor 1 Transmit channel 1 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 5. "CH6OM,processor 1 Receive channel 6 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "CH5OM,processor 1 Receive channel 5 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "CH4OM,processor 1 Receive channel 4 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 2. "CH3OM,processor 1 Receive channel 3 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "CH2OM,processor 1 Receive channel 2 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 0. "CH1OM,processor 1 Receive channel 1 occupied interrupt enable" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "C1SCR,Status Set or Clear register CPU1"
|
|
bitfld.long 0x0 21. "CH6S,processor 1 Transmit channel 6 status set" "0,1"
|
|
bitfld.long 0x0 20. "CH5S,processor 1 Transmit channel 5 status set" "0,1"
|
|
bitfld.long 0x0 19. "CH4S,processor 1 Transmit channel 4 status set" "0,1"
|
|
bitfld.long 0x0 18. "CH3S,processor 1 Transmit channel 3 status set" "0,1"
|
|
bitfld.long 0x0 17. "CH2S,processor 1 Transmit channel 2 status set" "0,1"
|
|
bitfld.long 0x0 16. "CH1S,processor 1 Transmit channel 1 status set" "0,1"
|
|
bitfld.long 0x0 5. "CH6C,processor 1 Receive channel 6 status clear" "0,1"
|
|
bitfld.long 0x0 4. "CH5C,processor 1 Receive channel 5 status clear" "0,1"
|
|
bitfld.long 0x0 3. "CH4C,processor 1 Receive channel 4 status clear" "0,1"
|
|
bitfld.long 0x0 2. "CH3C,processor 1 Receive channel 3 status clear" "0,1"
|
|
bitfld.long 0x0 1. "CH2C,processor 1 Receive channel 2 status clear" "0,1"
|
|
bitfld.long 0x0 0. "CH1C,processor 1 Receive channel 1 status clear" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "C1TO2SR,CPU1 to CPU2 status register"
|
|
bitfld.long 0x0 5. "CH6F,processor 1 transmit to process 2 Receive channel 6 status flag" "0,1"
|
|
bitfld.long 0x0 4. "CH5F,processor 1 transmit to process 2 Receive channel 5 status flag" "0,1"
|
|
bitfld.long 0x0 3. "CH4F,processor 1 transmit to process 2 Receive channel 4 status flag" "0,1"
|
|
bitfld.long 0x0 2. "CH3F,processor 1 transmit to process 2 Receive channel 3 status flag" "0,1"
|
|
bitfld.long 0x0 1. "CH2F,processor 1 transmit to process 2 Receive channel 2 status flag" "0,1"
|
|
bitfld.long 0x0 0. "CH1F,processor 1 transmit to process 2 Receive channel 1 status flag" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "C2CR,Control register CPU2"
|
|
bitfld.long 0x0 16. "TXFIE,processor 2 Transmit channel free interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "RXOIE,processor 2 Receive channel occupied interrupt enable" "0,1"
|
|
line.long 0x4 "C2MR,Mask register CPU2"
|
|
bitfld.long 0x4 21. "CH6FM,processor 2 Transmit channel 6 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "CH5FM,processor 2 Transmit channel 5 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 19. "CH4FM,processor 2 Transmit channel 4 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "CH3FM,processor 2 Transmit channel 3 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 17. "CH2FM,processor 2 Transmit channel 2 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "CH1FM,processor 2 Transmit channel 1 free interrupt mask" "0,1"
|
|
bitfld.long 0x4 5. "CH6OM,processor 2 Receive channel 6 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "CH5OM,processor 2 Receive channel 5 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "CH4OM,processor 2 Receive channel 4 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 2. "CH3OM,processor 2 Receive channel 3 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "CH2OM,processor 2 Receive channel 2 occupied interrupt enable" "0,1"
|
|
bitfld.long 0x4 0. "CH1OM,processor 2 Receive channel 1 occupied interrupt enable" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "C2SCR,Status Set or Clear register CPU2"
|
|
bitfld.long 0x0 21. "CH6S,processor 2 Transmit channel 6 status set" "0,1"
|
|
bitfld.long 0x0 20. "CH5S,processor 2 Transmit channel 5 status set" "0,1"
|
|
bitfld.long 0x0 19. "CH4S,processor 2 Transmit channel 4 status set" "0,1"
|
|
bitfld.long 0x0 18. "CH3S,processor 2 Transmit channel 3 status set" "0,1"
|
|
bitfld.long 0x0 17. "CH2S,processor 2 Transmit channel 2 status set" "0,1"
|
|
bitfld.long 0x0 16. "CH1S,processor 2 Transmit channel 1 status set" "0,1"
|
|
bitfld.long 0x0 5. "CH6C,processor 2 Receive channel 6 status clear" "0,1"
|
|
bitfld.long 0x0 4. "CH5C,processor 2 Receive channel 5 status clear" "0,1"
|
|
bitfld.long 0x0 3. "CH4C,processor 2 Receive channel 4 status clear" "0,1"
|
|
bitfld.long 0x0 2. "CH3C,processor 2 Receive channel 3 status clear" "0,1"
|
|
bitfld.long 0x0 1. "CH2C,processor 2 Receive channel 2 status clear" "0,1"
|
|
bitfld.long 0x0 0. "CH1C,processor 2 Receive channel 1 status clear" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "C2TOC1SR,CPU2 to CPU1 status register"
|
|
bitfld.long 0x0 5. "CH6F,processor 2 transmit to process 1 Receive channel 6 status flag" "0,1"
|
|
bitfld.long 0x0 4. "CH5F,processor 2 transmit to process 1 Receive channel 5 status flag" "0,1"
|
|
bitfld.long 0x0 3. "CH4F,processor 2 transmit to process 1 Receive channel 4 status flag" "0,1"
|
|
bitfld.long 0x0 2. "CH3F,processor 2 transmit to process 1 Receive channel 3 status flag" "0,1"
|
|
bitfld.long 0x0 1. "CH2F,processor 2 transmit to process 1 Receive channel 2 status flag" "0,1"
|
|
bitfld.long 0x0 0. "CH1F,processor 2 transmit to process 1 Receive channel 1 status flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,IPCC Hardware configuration register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Number of channels per CPU supported by the IP range 1 to 16"
|
|
line.long 0x4 "VERR,IPCC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0x8 "IPIDR,IPCC indentification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,Identification Code"
|
|
line.long 0xC "SIDR,IPCC size indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,IPCC Hardware configuration register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Number of channels per CPU supported by the IP range 1 to 16"
|
|
line.long 0x4 "VERR,IPCC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0x8 "IPIDR,IPCC indentification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,Identification Code"
|
|
line.long 0xC "SIDR,IPCC size indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,IPCC Hardware configuration register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Number of channels per CPU supported by the IP range 1 to 16"
|
|
line.long 0x4 "VERR,IPCC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0x8 "IPIDR,IPCC indentification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,Identification Code"
|
|
line.long 0xC "SIDR,IPCC size indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,IPCC Hardware configuration register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Number of channels per CPU supported by the IP range 1 to 16"
|
|
line.long 0x4 "VERR,IPCC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0x8 "IPIDR,IPCC indentification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,Identification Code"
|
|
line.long 0xC "SIDR,IPCC size indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,IPCC Hardware configuration register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,Number of channels per CPU supported by the IP range 1 to 16"
|
|
line.long 0x4 "VERR,IPCC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision"
|
|
line.long 0x8 "IPIDR,IPCC indentification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,Identification Code"
|
|
line.long 0xC "SIDR,IPCC size indentification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code"
|
|
endif
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value"
|
|
tree.end
|
|
sif (cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "LCD (Liquid Crystal Display Controller)"
|
|
base ad:0x40002400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,control register"
|
|
bitfld.long 0x0 8. "BUFEN,Voltage output buffer enable" "0,1"
|
|
bitfld.long 0x0 7. "MUX_SEG,Mux segment enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "BIAS,Bias selector" "0,1,2,3"
|
|
bitfld.long 0x0 2.--4. "DUTY,Duty selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 1. "VSEL,Voltage source selection" "0,1"
|
|
bitfld.long 0x0 0. "LCDEN,LCD controller enable" "0,1"
|
|
line.long 0x4 "FCR,frame control register"
|
|
hexmask.long.byte 0x4 22.--25. 1. "PS,PS 16-bit prescaler"
|
|
hexmask.long.byte 0x4 18.--21. 1. "DIV,DIV clock divider"
|
|
bitfld.long 0x4 16.--17. "BLINK,Blink mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "BLINKF,Blink frequency selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 10.--12. "CC,Contrast control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7.--9. "DEAD,Dead time duration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "PON,Pulse ON duration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "UDDIE,Update display done interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "SOFIE,Start of frame interrupt enable" "0,1"
|
|
bitfld.long 0x4 0. "HD,High drive enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 5. "FCRSF,LCD Frame Control Register Synchronization flag" "0,1"
|
|
rbitfld.long 0x8 4. "RDY,Ready flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDD,Update Display Done" "0,1"
|
|
bitfld.long 0x8 2. "UDR,Update display request" "0,1"
|
|
rbitfld.long 0x8 1. "SOF,Start of frame flag" "0,1"
|
|
rbitfld.long 0x8 0. "ENS,ENS" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "CLR,clear register"
|
|
bitfld.long 0x0 3. "UDDC,Update display done clear" "0,1"
|
|
bitfld.long 0x0 1. "SOFC,Start of frame flag clear" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "RAM_COM0,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "RAM_COM1,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "RAM_COM2,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "RAM_COM3,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "RAM_COM4,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "RAM_COM5,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "RAM_COM6,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "RAM_COM7,display memory"
|
|
bitfld.long 0x0 31. "S31,S31" "0,1"
|
|
bitfld.long 0x0 30. "S30,S30" "0,1"
|
|
bitfld.long 0x0 29. "S29,S29" "0,1"
|
|
bitfld.long 0x0 28. "S28,S28" "0,1"
|
|
bitfld.long 0x0 27. "S27,S27" "0,1"
|
|
bitfld.long 0x0 26. "S26,S26" "0,1"
|
|
bitfld.long 0x0 25. "S25,S25" "0,1"
|
|
bitfld.long 0x0 24. "S24,S24" "0,1"
|
|
bitfld.long 0x0 23. "S23,S23" "0,1"
|
|
bitfld.long 0x0 22. "S22,S22" "0,1"
|
|
bitfld.long 0x0 21. "S21,S21" "0,1"
|
|
bitfld.long 0x0 20. "S20,S20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "S19,S19" "0,1"
|
|
bitfld.long 0x0 18. "S18,S18" "0,1"
|
|
bitfld.long 0x0 17. "S17,S17" "0,1"
|
|
bitfld.long 0x0 16. "S16,S16" "0,1"
|
|
bitfld.long 0x0 15. "S15,S15" "0,1"
|
|
bitfld.long 0x0 14. "S14,S14" "0,1"
|
|
bitfld.long 0x0 13. "S13,S13" "0,1"
|
|
bitfld.long 0x0 12. "S12,S12" "0,1"
|
|
bitfld.long 0x0 11. "S11,S11" "0,1"
|
|
bitfld.long 0x0 10. "S10,S10" "0,1"
|
|
bitfld.long 0x0 9. "S09,S09" "0,1"
|
|
bitfld.long 0x0 8. "S08,S08" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "S07,S07" "0,1"
|
|
bitfld.long 0x0 6. "S06,S06" "0,1"
|
|
bitfld.long 0x0 5. "S05,S05" "0,1"
|
|
bitfld.long 0x0 4. "S04,S04" "0,1"
|
|
bitfld.long 0x0 3. "S03,S03" "0,1"
|
|
bitfld.long 0x0 2. "S02,S02" "0,1"
|
|
bitfld.long 0x0 1. "S01,S01" "0,1"
|
|
bitfld.long 0x0 0. "S00,S00" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "LPTIM (Low-Power Timer)"
|
|
base ad:0x0
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear Flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear Flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear Flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "OR,Option Register"
|
|
bitfld.long 0x0 1. "OR2,Option register bit 2" "0,1"
|
|
bitfld.long 0x0 0. "OR1,Option register bit 1" "0,1"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear Flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear Flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear Flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "OR,Option Register"
|
|
bitfld.long 0x0 1. "OR2,Option register bit 2" "0,1"
|
|
bitfld.long 0x0 0. "OR1,Option register bit 1" "0,1"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("STM32WB10*"))
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0xE000ED90
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "MPU_TYPER,MPU type register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "IREGION,Number of MPU instruction regions"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DREGION,Number of MPU data regions"
|
|
bitfld.long 0x0 0. "SEPARATE,Separate flag" "0,1"
|
|
line.long 0x4 "MPU_CTRL,MPU control register"
|
|
bitfld.long 0x4 2. "PRIVDEFENA,Enable priviliged software access to default memory map" "0,1"
|
|
bitfld.long 0x4 1. "HFNMIENA,Enables the operation of MPU during hard fault" "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Enables the MPU" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "MPU_RNR,MPU region number register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "REGION,MPU region"
|
|
line.long 0x4 "MPU_RBAR,MPU region base address register"
|
|
hexmask.long 0x4 5.--31. 1. "ADDR,Region base address field"
|
|
bitfld.long 0x4 4. "VALID,MPU region number valid" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "REGION,MPU region field"
|
|
line.long 0x8 "MPU_RASR,MPU region attribute and size register"
|
|
bitfld.long 0x8 28. "XN,Instruction access disable bit" "0,1"
|
|
bitfld.long 0x8 24.--26. "AP,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 19.--21. "TEX,memory attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 18. "S,Shareable memory attribute" "0,1"
|
|
bitfld.long 0x8 17. "C,memory attribute" "0,1"
|
|
bitfld.long 0x8 16. "B,memory attribute" "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "SRD,Subregion disable bits"
|
|
hexmask.long.byte 0x8 1.--5. 1. "SIZE,Size of the MPU protection region"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,Region enable bit." "0,1"
|
|
tree.end
|
|
endif
|
|
tree "PKA (Private Key Acceleration)"
|
|
base ad:0x58002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0,1"
|
|
bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA Operation Mode"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 2. "SECLVL,Security Enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "SECLVL,Security Enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "SECLVL,Security Enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 2. "SECLVL,Security Enable" "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "START,Start the operation" "0,1"
|
|
bitfld.long 0x0 0. "EN,Peripheral Enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,PKA status register"
|
|
bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0,1"
|
|
bitfld.long 0x0 19. "RAMERRF,RAM error flag" "0,1"
|
|
bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,PKA Operation in progress" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CLRFR,PKA clear flag register"
|
|
bitfld.long 0x0 20. "ADDRERRFC,Clear Address error flag" "0,1"
|
|
bitfld.long 0x0 19. "RAMERRFC,Clear RAM error flag" "0,1"
|
|
bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
rgroup.long 0x1FF4++0xB
|
|
line.long 0x0 "VERR,PKA version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x4 "IPIDR,PKA identification register"
|
|
hexmask.long 0x4 0.--31. 1. "ID,Identification Code"
|
|
line.long 0x8 "SIDR,PKA size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Side Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
rgroup.long 0x1FF4++0xB
|
|
line.long 0x0 "VERR,PKA version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x4 "IPIDR,PKA identification register"
|
|
hexmask.long 0x4 0.--31. 1. "ID,Identification Code"
|
|
line.long 0x8 "SIDR,PKA size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Side Identification Code"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
rgroup.long 0x1FF4++0xB
|
|
line.long 0x0 "VERR,PKA version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x4 "IPIDR,PKA identification register"
|
|
hexmask.long 0x4 0.--31. 1. "ID,Identification Code"
|
|
line.long 0x8 "SIDR,PKA size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Side Identification Code"
|
|
endif
|
|
tree.end
|
|
tree "PWR (Power Control)"
|
|
base ad:0x58000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Power control register 1"
|
|
bitfld.long 0x0 14. "LPR,Low-power run" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1"
|
|
bitfld.long 0x0 5. "FPDS,Flash power down mode during LPsSleep for CPU1" "0,1"
|
|
bitfld.long 0x0 4. "FPDR,Flash power down mode during LPRun for CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection for CPU1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CR2,Power control register 2"
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
endif
|
|
bitfld.long 0x4 6. "PVME3,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "0,1"
|
|
endif
|
|
bitfld.long 0x4 1.--3. "PLS,Power voltage detector level selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector enable" "0,1"
|
|
line.long 0x8 "CR3,Power control register 3"
|
|
bitfld.long 0x8 15. "EIWUL,Enable internal wakeup line for CPU1" "0,1"
|
|
bitfld.long 0x8 14. "EC2H,Enable CPU2 Hold interrupt for CPU1" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x8 13. "E802A,Enable end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x8 12. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 12. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
bitfld.long 0x8 11. "EBLEA,Enable BLE end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x8 11. "ECRPE,Enable critical radio phase end of activity interrupt for CPU1" "0,1"
|
|
endif
|
|
bitfld.long 0x8 10. "APC,Apply pull-up and pull-down configuration" "0,1"
|
|
bitfld.long 0x8 9. "RRS,SRAM2a retention in Standby mode" "0,1"
|
|
bitfld.long 0x8 8. "EBORHSDFB,Enable BORH and Step Down counverter forced in Bypass interrups for CPU1" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
endif
|
|
bitfld.long 0x8 3. "EWUP4,Enable Wakeup pin WKUP4" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
endif
|
|
bitfld.long 0x8 0. "EWUP1,Enable Wakeup pin WKUP1" "0,1"
|
|
line.long 0xC "CR4,Power control register 4"
|
|
bitfld.long 0xC 15. "C2BOOT,BOOT CPU2 after reset or wakeup from Stop or Standby modes" "0,1"
|
|
bitfld.long 0xC 9. "VBRS,VBAT battery charging resistor selection" "0,1"
|
|
bitfld.long 0xC 8. "VBE,VBAT battery charging enable" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
endif
|
|
bitfld.long 0xC 3. "WP4,Wakeup pin WKUP4 polarity" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
endif
|
|
bitfld.long 0xC 0. "WP1,Wakeup pin WKUP1 polarity" "0,1"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "SR1,Power status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Internal Wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x0 14. "C2HF,CPU2 Hold interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 13. "AF802,802.15.4 end of activity interrupt flag" "0,1"
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
bitfld.long 0x0 12. "BLEAF,BLE end of activity interrupt flag" "0,1"
|
|
bitfld.long 0x0 11. "CRPEF,Enable critical radio phase end of activity interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10. "WUF802,802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 9. "BLEWUF,BLE wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x0 8. "BORHF,BORH interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 7. "SMPSFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 7. "SDFBF,Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 4. "CWUF5,Wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 3. "CWUF4,Wakeup flag 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "CWUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "CWUF2,Wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "CWUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
line.long 0x4 "SR2,Power status register 2"
|
|
bitfld.long 0x4 14. "PVMO3,Peripheral voltage monitoring output: VDDA vs. 1.62 V" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "0,1"
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "VOSF,Voltage scaling flag" "0,1"
|
|
bitfld.long 0x4 9. "REGLPF,Low-power regulator flag" "0,1"
|
|
bitfld.long 0x4 8. "REGLPS,Low-power regulator started" "0,1"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 1. "SMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 1. "SDSMPSF,Step Down converter SMPS mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "SMPSBF,Step Down converter Bypass mode flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "SDBF,Step Down converter Bypass mode flag" "0,1"
|
|
endif
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SCR,Power status clear register"
|
|
bitfld.long 0x0 14. "CC2HF,Clear CPU2 Hold interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 13. "C802AF,Clear 802.15.4 end of activity interrupt flag" "0,1"
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
bitfld.long 0x0 12. "CBLEAF,Clear BLE end of activity interrupt flag" "0,1"
|
|
bitfld.long 0x0 11. "CCRPEF,Clear critical radio phase end of activity interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10. "C802WUF,Clear 802.15.4 wakeup interrupt flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 9. "CBLEWUF,Clear BLE wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x0 8. "CBORHF,Clear BORH interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CSMPSFBF,Clear SMPS Step Down converter forced in Bypass interrupt flag" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
endif
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
endif
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x1C++0x1B
|
|
line.long 0x0 "CR5,Power control register 5"
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 15. "SDEB,Enable Step Down converter SMPS mode enabled" "0,1"
|
|
bitfld.long 0x0 14. "SDBEN,Enable Step Down converter Bypass mode enabled" "0,1"
|
|
bitfld.long 0x0 9. "SMPSCFG,VOS configuration selection (non user)" "0,1"
|
|
bitfld.long 0x0 4.--6. "SDSC,Step Down converter supplt startup current selection" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SDVOS,Step Down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 15. "SMPSEN,Enable Step Down converter SMPS mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 15. "SDEB,Enable Step Down converter SMPS mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 15. "SMPSEN,Enable SMPS step-down converter SMPS mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 15. "SDEB,Enable Step Down converter SMPS mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 15. "SMPSEN,Enable SMPS step-down converter SMPS mode enabled" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 15. "SMPSEN,Enable SMPS step-down converter SMPS mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 14. "SDBEN,Enable Step Down converter Bypass mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 14. "SDBEN,Enable Step Down converter Bypass mode enabled" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 9. "SMPSCFG,VOS configuration selection (non user)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 9. "SMPSCFG,VOS configuration selection (non user)" "0,1"
|
|
endif
|
|
bitfld.long 0x0 8. "BORHC,BORH configuration selection" "0,1"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 4.--6. "SMPSSC,Step Down converter supplt startup current selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 4.--6. "SDSC,Step Down converter supplt startup current selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 4.--6. "SMPSSC,SMPS step-down converter supply startup current selection current selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 4.--6. "SDSC,Step Down converter supplt startup current selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 4.--6. "SMPSSC,SMPS step-down converter supply startup current selection current selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 4.--6. "SMPSSC,SMPS step-down converter supply startup current selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32WB15*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SMPSVOS,Step Down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SDVOS,Step Down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SMPSVOS,SMPS step-down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SDVOS,Step Down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SMPSVOS,SMPS step-down converter voltage output scaling"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "SMPSVOS,SMPS step-down converter voltage output scaling"
|
|
endif
|
|
line.long 0x4 "PUCRA,Power Port A pull-up control register"
|
|
bitfld.long 0x4 15. "PU15,Port A pull-up bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 14. "PU14,Port A pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
bitfld.long 0x4 13. "PU13,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PU12,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 11. "PU11,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PU10,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 9. "PU9,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PU8,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 7. "PU7,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PU6,Port A pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PU5,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PU4,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 3. "PU3,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PU2,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 1. "PU1,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PU0,Port A pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x8 "PDCRA,Power Port A pull-down control register"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x8 15. "PD15,Port A pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
bitfld.long 0x8 14. "PD14,Port A pull-down bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB15*"))
|
|
bitfld.long 0x8 13. "PD13,Port A pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
bitfld.long 0x8 12. "PD12,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 11. "PD11,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 10. "PD10,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 9. "PD9,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 8. "PD8,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 7. "PD7,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 6. "PD6,Port A pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PD5,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 4. "PD4,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 3. "PD3,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 2. "PD2,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 1. "PD1,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x8 0. "PD0,Port A pull-down bit y (y=0..15)" "0,1"
|
|
line.long 0xC "PUCRB,Power Port B pull-up control register"
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
bitfld.long 0xC 11. "PU11,Port B pull-up bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0xC 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 9. "PU9,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 8. "PU8,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 7. "PU7,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 6. "PU6,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 5. "PU5,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 4. "PU4,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PU3,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 2. "PU2,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 1. "PU1,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0xC 0. "PU0,Port B pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x10 "PDCRB,Power Port B pull-down control register"
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x10 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x10 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x10 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x10 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
bitfld.long 0x10 11. "PD11,Port B pull-down bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x10 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 9. "PD9,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 8. "PD8,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 7. "PD7,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 6. "PD6,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 5. "PD5,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 3. "PD3,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "PD2,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 1. "PD1,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x10 0. "PD0,Port B pull-down bit y (y=0..15)" "0,1"
|
|
line.long 0x14 "PUCRC,Power Port C pull-up control register"
|
|
bitfld.long 0x14 15. "PU15,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 14. "PU14,Port C pull-up bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x14 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x14 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
line.long 0x18 "PDCRC,Power Port C pull-down control register"
|
|
bitfld.long 0x18 15. "PD15,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 14. "PD14,Port C pull-down bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x18 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x18 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x4 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PUCRE,Power Port E pull-up control register"
|
|
bitfld.long 0x0 4. "PU4,Port E pull-up bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
endif
|
|
line.long 0x4 "PDCRE,Power Port E pull-down control register"
|
|
bitfld.long 0x4 4. "PD4,Port E pull-down bit y (y=0..15)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x4 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
endif
|
|
group.long 0x58++0x7
|
|
line.long 0x0 "PUCRH,Power Port H pull-up control register"
|
|
bitfld.long 0x0 3. "PU3,Port H pull-up bit y (y=0..1)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 1. "PU1,Port H pull-up bit y (y=0..1)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "PU0,Port H pull-up bit y (y=0..1)" "0,1"
|
|
endif
|
|
line.long 0x4 "PDCRH,Power Port H pull-down control register"
|
|
bitfld.long 0x4 3. "PD3,Port H pull-down bit y (y=0..1)" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x4 1. "PD1,Port H pull-down bit y (y=0..1)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "PD0,Port H pull-down bit y (y=0..1)" "0,1"
|
|
endif
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "C2CR1,CPU2 Power control register 1"
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 15. "EWKUP802,802.15.4 external wakeup signal" "0,1"
|
|
endif
|
|
bitfld.long 0x0 14. "BLEEWKUP,BLE external wakeup signal" "0,1"
|
|
bitfld.long 0x0 5. "FPDS,Flash power down mode during LPSleep for CPU2" "0,1"
|
|
bitfld.long 0x0 4. "FPDR,Flash power down mode during LPRun for CPU2" "0,1"
|
|
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection for CPU2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "C2CR3,CPU2 Power control register 3"
|
|
bitfld.long 0x4 15. "EIWUL,Enable internal wakeup line for CPU2" "0,1"
|
|
bitfld.long 0x4 12. "APC,Apply pull-up and pull-down configuration for CPU2" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*"))
|
|
bitfld.long 0x4 10. "E802WUP,Enable 802.15.4 host wakeup interrupt for CPU2" "0,1"
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
bitfld.long 0x4 9. "EBLEWUP,Enable BLE host wakeup interrupt for CPU2" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 4. "EWUP5,Enable Wakeup pin WKUP5 for CPU2" "0,1"
|
|
endif
|
|
bitfld.long 0x4 3. "EWUP4,Enable Wakeup pin WKUP4 for CPU2" "0,1"
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 2. "EWUP3,Enable Wakeup pin WKUP3 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 1. "EWUP2,Enable Wakeup pin WKUP2 for CPU2" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0. "EWUP1,Enable Wakeup pin WKUP1 for CPU2" "0,1"
|
|
line.long 0x8 "EXTSCR,Power status clear register"
|
|
rbitfld.long 0x8 15. "C2DS,CPU2 deepsleep mode" "0,1"
|
|
rbitfld.long 0x8 14. "C1DS,CPU1 deepsleep mode" "0,1"
|
|
rbitfld.long 0x8 13. "CRPF,Critical Radio system phase" "0,1"
|
|
rbitfld.long 0x8 11. "C2STOPF,System Stop flag for CPU2" "0,1"
|
|
rbitfld.long 0x8 10. "C2SBF,System Standby flag for CPU2" "0,1"
|
|
rbitfld.long 0x8 9. "C1STOPF,System Stop flag for CPU1" "0,1"
|
|
rbitfld.long 0x8 8. "C1SBF,System Standby flag for CPU1" "0,1"
|
|
bitfld.long 0x8 2. "CCRPF,Clear Critical Radio system phase" "0,1"
|
|
bitfld.long 0x8 1. "C2CSSF,Clear CPU2 Stop Standby flags" "0,1"
|
|
bitfld.long 0x8 0. "C1CSSF,Clear CPU1 Stop Standby flags" "0,1"
|
|
tree.end
|
|
sif (cpuis("STM32WB35*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "QUADSPI (Quad-SPI Memory Interface)"
|
|
base ad:0xA0001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,Clock prescaler"
|
|
bitfld.long 0x0 23. "PMM,Polling match mode" "0,1"
|
|
bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1"
|
|
bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1"
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level"
|
|
bitfld.long 0x0 4. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 1. "ABORT,Abort request" "0,1"
|
|
bitfld.long 0x0 0. "EN,Enable" "0,1"
|
|
line.long 0x4 "DCR,device configuration register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "FSIZE,FLASH memory size"
|
|
bitfld.long 0x4 8.--10. "CSHT,Chip select high time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "CKMODE,Mode 0 / mode 3" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,status register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
bitfld.long 0x0 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "SMF,Status match flag" "0,1"
|
|
bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1"
|
|
group.long 0xC++0x27
|
|
line.long 0x0 "FCR,flag clear register"
|
|
bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1"
|
|
bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1"
|
|
line.long 0x4 "DLR,data length register"
|
|
hexmask.long 0x4 0.--31. 1. "DL,Data length"
|
|
line.long 0x8 "CCR,communication configuration register"
|
|
bitfld.long 0x8 31. "DDRM,Double data rate mode" "0,1"
|
|
bitfld.long 0x8 28. "SIOO,Send instruction only once mode" "0,1"
|
|
bitfld.long 0x8 26.--27. "FMODE,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "DMODE,Data mode" "0,1,2,3"
|
|
hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles"
|
|
bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "ADMODE,Address mode" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "IMODE,Instruction mode" "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction"
|
|
line.long 0xC "AR,address register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Address"
|
|
line.long 0x10 "ABR,ABR"
|
|
hexmask.long 0x10 0.--31. 1. "ALTERNATE,ALTERNATE"
|
|
line.long 0x14 "DR,data register"
|
|
hexmask.long 0x14 0.--31. 1. "DATA,Data"
|
|
line.long 0x18 "PSMKR,polling status mask register"
|
|
hexmask.long 0x18 0.--31. 1. "MASK,Status mask"
|
|
line.long 0x1C "PSMAR,polling status match register"
|
|
hexmask.long 0x1C 0.--31. 1. "MATCH,Status match"
|
|
line.long 0x20 "PIR,polling interval register"
|
|
hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval"
|
|
line.long 0x24 "LPTR,low-power timeout register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period"
|
|
tree.end
|
|
endif
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x58000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR,Clock control register"
|
|
rbitfld.long 0x0 27. "PLLSAI1RDY,SAI1 PLL clock ready flag" "0,1"
|
|
bitfld.long 0x0 26. "PLLSAI1ON,SAI1 PLL enable" "0,1"
|
|
rbitfld.long 0x0 25. "PLLRDY,Main PLL clock ready flag" "0,1"
|
|
bitfld.long 0x0 24. "PLLON,Main PLL enable" "0,1"
|
|
bitfld.long 0x0 20. "HSEPRE,HSE sysclk and PLL M divider prescaler" "0,1"
|
|
bitfld.long 0x0 19. "CSSON,HSE Clock security system enable" "0,1"
|
|
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0,1"
|
|
bitfld.long 0x0 16. "HSEON,HSE clock enabled" "0,1"
|
|
rbitfld.long 0x0 12. "HSIKERDY,HSI kernel clock ready flag for peripherals requests" "0,1"
|
|
bitfld.long 0x0 11. "HSIASFS,HSI automatic start from Stop" "0,1"
|
|
rbitfld.long 0x0 10. "HSIRDY,HSI clock ready flag" "0,1"
|
|
bitfld.long 0x0 9. "HSIKERON,HSI always enable for peripheral kernels" "0,1"
|
|
bitfld.long 0x0 8. "HSION,HSI clock enabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "MSIRANGE,MSI clock ranges"
|
|
bitfld.long 0x0 2. "MSIPLLEN,MSI clock PLL enable" "0,1"
|
|
rbitfld.long 0x0 1. "MSIRDY,MSI clock ready flag" "0,1"
|
|
bitfld.long 0x0 0. "MSION,MSI clock enable" "0,1"
|
|
line.long 0x4 "ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI clock trimming"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HSICAL,HSI clock calibration"
|
|
hexmask.long.byte 0x4 8.--15. 1. "MSITRIM,MSI clock trimming"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MSICAL,MSI clock calibration"
|
|
line.long 0x8 "CFGR,Clock configuration register"
|
|
bitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output"
|
|
rbitfld.long 0x8 18. "PPRE2F,APB2 prescaler flag" "0,1"
|
|
rbitfld.long 0x8 17. "PPRE1F,APB1 prescaler flag" "0,1"
|
|
rbitfld.long 0x8 16. "HPREF,AHB prescaler flag" "0,1"
|
|
bitfld.long 0x8 15. "STOPWUCK,Wakeup from Stop and CSS backup clock selection" "0,1"
|
|
bitfld.long 0x8 11.--13. "PPRE2,APB high-speed prescaler (APB2)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "PPRE1,PB low-speed prescaler (APB1)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 4.--7. 1. "HPRE,AHB prescaler"
|
|
rbitfld.long 0x8 2.--3. "SWS,System clock switch status" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "SW,System clock switch" "0,1,2,3"
|
|
line.long 0xC "PLLCFGR,PLLSYS configuration register"
|
|
bitfld.long 0xC 29.--31. "PLLR,Main PLLSYS division factor R for SYSCLK (system clock)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 28. "PLLREN,Main PLLSYSR PLLCLK output enable" "0,1"
|
|
bitfld.long 0xC 25.--27. "PLLQ,Main PLLSYS division factor Q for PLLSYSUSBCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 24. "PLLQEN,Main PLLSYSQ output enable" "0,1"
|
|
hexmask.long.byte 0xC 17.--21. 1. "PLLP,Main PLL division factor P for PPLSYSSAICLK"
|
|
bitfld.long 0xC 16. "PLLPEN,Main PLLSYSP output enable" "0,1"
|
|
hexmask.long.byte 0xC 8.--14. 1. "PLLN,Main PLLSYS multiplication factor N"
|
|
newline
|
|
bitfld.long 0xC 4.--6. "PLLM,Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--1. "PLLSRC,Main PLL PLLSAI1 and PLLSAI2 entry clock source" "0,1,2,3"
|
|
line.long 0x10 "PLLSAI1CFGR,PLLSAI1 configuration register"
|
|
bitfld.long 0x10 29.--31. "PLLR,PLLSAI division factor R for PLLADC1CLK (ADC clock)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 28. "PLLREN,PLLSAI PLLADC1CLK output enable" "0,1"
|
|
bitfld.long 0x10 25.--27. "PLLQ,SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 24. "PLLQEN,SAIPLL PLLSAIUSBCLK output enable" "0,1"
|
|
hexmask.long.byte 0x10 17.--21. 1. "PLLP,SAI1PLL division factor P for PLLSAICLK (SAI1clock)"
|
|
bitfld.long 0x10 16. "PLLPEN,SAIPLL PLLSAI1CLK output enable" "0,1"
|
|
hexmask.long.byte 0x10 8.--14. 1. "PLLN,SAIPLL multiplication factor for VCO"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CIER,Clock interrupt enable register"
|
|
bitfld.long 0x0 11. "LSI2RDYIE,LSI2 ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 10. "HSI48RDYIE,HSI48 ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "PLLSAI1RDYIE,PLLSAI1 ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "PLLRDYIE,PLLSYS ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSIRDYIE,MSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "LSI1RDYIE,LSI1 ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x0 11. "LSI2RDYF,LSI2 ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 10. "HSI48RDYF,HSI48 ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x0 8. "HSECSSF,HSE Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x0 6. "PLLSAI1RDYF,PLLSAI1 ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 5. "PLLRDYF,PLL ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "MSIRDYF,MSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "LSI1RDYF,LSI1 ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x0 11. "LSI2RDYC,LSI2 ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 10. "HSI48RDYC,HSI48 ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x0 8. "HSECSSC,HSE Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x0 6. "PLLSAI1RDYC,PLLSAI1 ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "PLLRDYC,PLL ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "MSIRDYC,MSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "LSI1RDYC,LSI1 ready interrupt clear" "0,1"
|
|
group.long 0x24++0xF
|
|
line.long 0x0 "SMPSCR,Step Down converter control register"
|
|
rbitfld.long 0x0 8.--9. "SMPSSWS,Step Down converter clock switch status" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "SMPSDIV,Step Down converter clock prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SMPSSEL,Step Down converter clock selection" "0,1,2,3"
|
|
line.long 0x4 "AHB1RSTR,AHB1 peripheral reset register"
|
|
bitfld.long 0x4 16. "TSCRST,Touch Sensing Controller reset" "0,1"
|
|
bitfld.long 0x4 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x4 2. "DMAMUXRST,DMAMUX reset" "0,1"
|
|
bitfld.long 0x4 1. "DMA2RST,DMA2 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
line.long 0x8 "AHB2RSTR,AHB2 peripheral reset register"
|
|
bitfld.long 0x8 16. "AES1RST,AES1 hardware accelerator reset" "0,1"
|
|
bitfld.long 0x8 13. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0x8 7. "GPIOHRST,IO port H reset" "0,1"
|
|
bitfld.long 0x8 4. "GPIOERST,IO port E reset" "0,1"
|
|
bitfld.long 0x8 3. "GPIODRST,IO port D reset" "0,1"
|
|
bitfld.long 0x8 2. "GPIOCRST,IO port C reset" "0,1"
|
|
bitfld.long 0x8 1. "GPIOBRST,IO port B reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "GPIOARST,IO port A reset" "0,1"
|
|
line.long 0xC "AHB3RSTR,AHB3 peripheral reset register"
|
|
bitfld.long 0xC 25. "FLASHRST,Flash interface reset" "0,1"
|
|
bitfld.long 0xC 20. "IPCCRST,IPCC interface reset" "0,1"
|
|
bitfld.long 0xC 19. "HSEMRST,HSEM interface reset" "0,1"
|
|
bitfld.long 0xC 18. "RNGRST,RNG interface reset" "0,1"
|
|
bitfld.long 0xC 17. "AES2RST,AES2 interface reset" "0,1"
|
|
bitfld.long 0xC 16. "PKARST,PKA interface reset" "0,1"
|
|
bitfld.long 0xC 8. "QSPIRST,Quad SPI memory interface reset" "0,1"
|
|
group.long 0x38++0x1B
|
|
line.long 0x0 "APB1RSTR1,APB1 peripheral reset register 1"
|
|
bitfld.long 0x0 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x0 26. "USBFSRST,USB FS reset" "0,1"
|
|
bitfld.long 0x0 24. "CRSRST,CRS reset" "0,1"
|
|
bitfld.long 0x0 23. "I2C3RST,I2C3 reset" "0,1"
|
|
bitfld.long 0x0 21. "I2C1RST,I2C1 reset" "0,1"
|
|
bitfld.long 0x0 14. "SPI2RST,SPI2 reset" "0,1"
|
|
bitfld.long 0x0 9. "LCDRST,LCD interface reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
line.long 0x4 "APB1RSTR2,APB1 peripheral reset register 2"
|
|
bitfld.long 0x4 5. "LPTIM2RST,Low-power timer 2 reset" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
endif
|
|
line.long 0x8 "APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x8 21. "SAI1RST,Serial audio interface 1 (SAI1) reset" "0,1"
|
|
bitfld.long 0x8 18. "TIM17RST,TIM17 timer reset" "0,1"
|
|
bitfld.long 0x8 17. "TIM16RST,TIM16 timer reset" "0,1"
|
|
bitfld.long 0x8 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0x8 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0x8 11. "TIM1RST,TIM1 timer reset" "0,1"
|
|
line.long 0xC "APB3RSTR,APB3 peripheral reset register"
|
|
bitfld.long 0xC 0. "RFRST,Radio system BLE reset" "0,1"
|
|
line.long 0x10 "AHB1ENR,AHB1 peripheral clock enable register"
|
|
bitfld.long 0x10 16. "TSCEN,Touch Sensing Controller clock enable" "0,1"
|
|
bitfld.long 0x10 12. "CRCEN,CPU1 CRC clock enable" "0,1"
|
|
bitfld.long 0x10 2. "DMAMUXEN,DMAMUX clock enable" "0,1"
|
|
bitfld.long 0x10 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x10 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
line.long 0x14 "AHB2ENR,AHB2 peripheral clock enable register"
|
|
bitfld.long 0x14 16. "AES1EN,AES1 accelerator clock enable" "0,1"
|
|
bitfld.long 0x14 13. "ADCEN,ADC clock enable" "0,1"
|
|
bitfld.long 0x14 7. "GPIOHEN,IO port H clock enable" "0,1"
|
|
bitfld.long 0x14 4. "GPIOEEN,IO port E clock enable" "0,1"
|
|
bitfld.long 0x14 3. "GPIODEN,IO port D clock enable" "0,1"
|
|
bitfld.long 0x14 2. "GPIOCEN,IO port C clock enable" "0,1"
|
|
bitfld.long 0x14 1. "GPIOBEN,IO port B clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GPIOAEN,IO port A clock enable" "0,1"
|
|
line.long 0x18 "AHB3ENR,AHB3 peripheral clock enable register"
|
|
bitfld.long 0x18 25. "FLASHEN,FLASHEN" "0,1"
|
|
bitfld.long 0x18 20. "IPCCEN,IPCCEN" "0,1"
|
|
bitfld.long 0x18 19. "HSEMEN,HSEMEN" "0,1"
|
|
bitfld.long 0x18 18. "RNGEN,RNGEN" "0,1"
|
|
bitfld.long 0x18 17. "AES2EN,AES2EN" "0,1"
|
|
bitfld.long 0x18 16. "PKAEN,PKAEN" "0,1"
|
|
bitfld.long 0x18 8. "QSPIEN,QSPIEN" "0,1"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "APB1ENR1,APB1ENR1"
|
|
bitfld.long 0x0 31. "LPTIM1EN,CPU1 Low power timer 1 clock enable" "0,1"
|
|
bitfld.long 0x0 26. "USBEN,CPU1 USB clock enable" "0,1"
|
|
bitfld.long 0x0 24. "CRSEN,CPU1 CRS clock enable" "0,1"
|
|
bitfld.long 0x0 23. "I2C3EN,CPU1 I2C3 clock enable" "0,1"
|
|
bitfld.long 0x0 21. "I2C1EN,CPU1 I2C1 clock enable" "0,1"
|
|
bitfld.long 0x0 14. "SPI2EN,CPU1 SPI2 clock enable" "0,1"
|
|
bitfld.long 0x0 11. "WWDGEN,CPU1 Window watchdog clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RTCAPBEN,CPU1 RTC APB clock enable" "0,1"
|
|
bitfld.long 0x0 9. "LCDEN,CPU1 LCD clock enable" "0,1"
|
|
bitfld.long 0x0 0. "TIM2EN,CPU1 TIM2 timer clock enable" "0,1"
|
|
line.long 0x4 "APB1ENR2,APB1 peripheral clock enable register 2"
|
|
bitfld.long 0x4 5. "LPTIM2EN,CPU1 LPTIM2EN" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU1 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU1 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU1 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU1 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
line.long 0x8 "APB2ENR,APB2ENR"
|
|
bitfld.long 0x8 21. "SAI1EN,CPU1 SAI1 clock enable" "0,1"
|
|
bitfld.long 0x8 18. "TIM17EN,CPU1 TIM17 timer clock enable" "0,1"
|
|
bitfld.long 0x8 17. "TIM16EN,CPU1 TIM16 timer clock enable" "0,1"
|
|
bitfld.long 0x8 14. "USART1EN,CPU1 USART1clock enable" "0,1"
|
|
bitfld.long 0x8 12. "SPI1EN,CPU1 SPI1 clock enable" "0,1"
|
|
bitfld.long 0x8 11. "TIM1EN,CPU1 TIM1 timer clock enable" "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "AHB1SMENR,AHB1 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x0 16. "TSCSMEN,CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x0 12. "CRCSMEN,CPU1 CRCSMEN" "0,1"
|
|
bitfld.long 0x0 9. "SRAM1SMEN,CPU1 SRAM1 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x0 2. "DMAMUXSMEN,CPU1 DMAMUX clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x0 1. "DMA2SMEN,CPU1 DMA2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x0 0. "DMA1SMEN,CPU1 DMA1 clocks enable during Sleep and Stop modes" "0,1"
|
|
line.long 0x4 "AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x4 16. "AES1SMEN,CPU1 AES1 accelerator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 13. "ADCFSSMEN,CPU1 ADC clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 7. "GPIOHSMEN,CPU1 IO port H clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 4. "GPIOESMEN,CPU1 IO port E clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 3. "GPIODSMEN,CPU1 IO port D clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 2. "GPIOCSMEN,CPU1 IO port C clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x4 1. "GPIOBSMEN,CPU1 IO port B clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "GPIOASMEN,CPU1 IO port A clocks enable during Sleep and Stop modes" "0,1"
|
|
line.long 0x8 "AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x8 25. "FLASHSMEN,Flash interface clocks enable during CPU1 sleep mode" "0,1"
|
|
bitfld.long 0x8 24. "SRAM2SMEN,SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode" "0,1"
|
|
bitfld.long 0x8 18. "RNGSMEN,True RNG clocks enable during CPU1 sleep mode" "0,1"
|
|
bitfld.long 0x8 17. "AES2SMEN,AES2 accelerator clocks enable during CPU1 sleep mode" "0,1"
|
|
bitfld.long 0x8 16. "PKASMEN,PKA accelerator clocks enable during CPU1 sleep mode" "0,1"
|
|
bitfld.long 0x8 8. "QSPISMEN,QSPISMEN" "0,1"
|
|
group.long 0x78++0xB
|
|
line.long 0x0 "APB1SMENR1,APB1SMENR1"
|
|
bitfld.long 0x0 31. "LPTIM1SMEN,Low power timer 1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 26. "USBSMEN,USB FS clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 24. "CRSMEN,CRS clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 23. "I2C3SMEN,I2C3 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 21. "I2C1SMEN,I2C1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 14. "SPI2SMEN,SPI2 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 11. "WWDGSMEN,Window watchdog clocks enable during CPU1 Sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RTCAPBSMEN,RTC APB clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 9. "LCDSMEN,LCD clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "TIM2SMEN,TIM2 timer clocks enable during CPU1 Sleep mode" "0,1"
|
|
line.long 0x4 "APB1SMENR2,APB1 peripheral clocks enable in Sleep and Stop modes register 2"
|
|
bitfld.long 0x4 5. "LPTIM2SMEN,Low power timer 2 clocks enable during CPU1 Sleep mode" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
endif
|
|
line.long 0x8 "APB2SMENR,APB2SMENR"
|
|
bitfld.long 0x8 21. "SAI1SMEN,SAI1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x8 18. "TIM17SMEN,TIM17 timer clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x8 17. "TIM16SMEN,TIM16 timer clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x8 14. "USART1SMEN,USART1clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x8 12. "SPI1SMEN,SPI1 clocks enable during CPU1 Sleep mode" "0,1"
|
|
bitfld.long 0x8 11. "TIM1SMEN,TIM1 timer clocks enable during CPU1 Sleep mode" "0,1"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "CCIPR,CCIPR"
|
|
bitfld.long 0x0 30.--31. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "ADCSEL,ADCs clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CLK48SEL,48 MHz clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "SAI1SEL,SAI1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "LPTIM2SEL,Low power timer 2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "LPTIM1SEL,Low power timer 1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "I2C3SEL,I2C3 clock source selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0,1,2,3"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0,1,2,3"
|
|
group.long 0x90++0xF
|
|
line.long 0x0 "BDCR,BDCR"
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x0 25.--26. "LSCOSEL,Low speed clock output selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB30*"))
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
endif
|
|
bitfld.long 0x0 24. "LSCOEN,Low speed clock output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "BDRST,Backup domain software reset" "0,1"
|
|
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3"
|
|
rbitfld.long 0x0 6. "LSECSSD_,CSS on LSE failure detection" "0,1"
|
|
bitfld.long 0x0 5. "LSECSSON,LSECSSON" "0,1"
|
|
bitfld.long 0x0 3.--4. "LSEDRV,SE oscillator drive capability" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0,1"
|
|
line.long 0x4 "CSR,CSR"
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "BORRSTF,BOR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flag" "0,1"
|
|
rbitfld.long 0x4 16. "RFRSTS,Radio system BLE and 802.15.4 reset status" "0,1"
|
|
bitfld.long 0x4 14.--15. "RFWKPSEL,RF system wakeup clock source selection" "0,1,2,3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "LSI2BW,LSI2 oscillator bias configuration"
|
|
rbitfld.long 0x4 5. "LSI2TRIMOK,LSI2 oscillator trim OK" "0,1"
|
|
bitfld.long 0x4 4. "LSI2TRIMEN,LSI2 oscillator trimming enable" "0,1"
|
|
rbitfld.long 0x4 3. "LSI2RDY,LSI2 oscillator ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LSI2ON,LSI2 oscillator enabled" "0,1"
|
|
rbitfld.long 0x4 1. "LSI1RDY,LSI1 oscillator ready" "0,1"
|
|
bitfld.long 0x4 0. "LSI1ON,LSI1 oscillator enabled" "0,1"
|
|
line.long 0x8 "CRRCR,Clock recovery RC register"
|
|
hexmask.long.word 0x8 7.--15. 1. "HSI48CAL,HSI48 clock calibration"
|
|
rbitfld.long 0x8 1. "HSI48RDY,HSI48 clock ready" "0,1"
|
|
bitfld.long 0x8 0. "HSI48ON,HSI48 oscillator enabled" "0,1"
|
|
line.long 0xC "HSECR,Clock HSE register"
|
|
hexmask.long.byte 0xC 8.--13. 1. "HSETUNE,HSE capacitor tuning"
|
|
bitfld.long 0xC 4.--6. "HSEGMC,HSE current control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 3. "HSES,HSE Sense amplifier threshold" "0,1"
|
|
bitfld.long 0xC 0. "UNLOCKED,Register lock system" "0,1"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "EXTCFGR,Extended clock recovery register"
|
|
rbitfld.long 0x0 20. "RFCSS,RF clock source selected" "0,1"
|
|
rbitfld.long 0x0 17. "C2HPREF,CPU2 AHB prescaler flag" "0,1"
|
|
rbitfld.long 0x0 16. "SHDHPREF,Shared AHB prescaler flag" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C2HPRE,CPU2 AHB prescaler"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SHDHPRE,Shared AHB prescaler"
|
|
group.long 0x148++0xB
|
|
line.long 0x0 "C2AHB1ENR,CPU2 AHB1 peripheral clock enable register"
|
|
bitfld.long 0x0 16. "TSCEN,CPU2 Touch Sensing Controller clock enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCEN,CPU2 CRC clock enable" "0,1"
|
|
bitfld.long 0x0 9. "SRAM1EN,CPU2 SRAM1 clock enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAMUXEN,CPU2 DMAMUX clock enable" "0,1"
|
|
bitfld.long 0x0 1. "DMA2EN,CPU2 DMA2 clock enable" "0,1"
|
|
bitfld.long 0x0 0. "DMA1EN,CPU2 DMA1 clock enable" "0,1"
|
|
line.long 0x4 "C2AHB2ENR,CPU2 AHB2 peripheral clock enable register"
|
|
bitfld.long 0x4 16. "AES1EN,CPU2 AES1 accelerator clock enable" "0,1"
|
|
bitfld.long 0x4 13. "ADCEN,CPU2 ADC clock enable" "0,1"
|
|
bitfld.long 0x4 7. "GPIOHEN,CPU2 IO port H clock enable" "0,1"
|
|
bitfld.long 0x4 4. "GPIOEEN,CPU2 IO port E clock enable" "0,1"
|
|
bitfld.long 0x4 3. "GPIODEN,CPU2 IO port D clock enable" "0,1"
|
|
bitfld.long 0x4 2. "GPIOCEN,CPU2 IO port C clock enable" "0,1"
|
|
bitfld.long 0x4 1. "GPIOBEN,CPU2 IO port B clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "GPIOAEN,CPU2 IO port A clock enable" "0,1"
|
|
line.long 0x8 "C2AHB3ENR,CPU2 AHB3 peripheral clock enable register"
|
|
bitfld.long 0x8 25. "FLASHEN,CPU2 FLASHEN" "0,1"
|
|
bitfld.long 0x8 20. "IPCCEN,CPU2 IPCCEN" "0,1"
|
|
bitfld.long 0x8 19. "HSEMEN,CPU2 HSEMEN" "0,1"
|
|
bitfld.long 0x8 18. "RNGEN,CPU2 RNGEN" "0,1"
|
|
bitfld.long 0x8 17. "AES2EN,CPU2 AES2EN" "0,1"
|
|
bitfld.long 0x8 16. "PKAEN,CPU2 PKAEN" "0,1"
|
|
group.long 0x158++0x1B
|
|
line.long 0x0 "C2APB1ENR1,CPU2 APB1ENR1"
|
|
bitfld.long 0x0 31. "LPTIM1EN,CPU2 Low power timer 1 clock enable" "0,1"
|
|
bitfld.long 0x0 26. "USBEN,CPU2 USB clock enable" "0,1"
|
|
bitfld.long 0x0 24. "CRSEN,CPU2 CRS clock enable" "0,1"
|
|
bitfld.long 0x0 23. "I2C3EN,CPU2 I2C3 clock enable" "0,1"
|
|
bitfld.long 0x0 21. "I2C1EN,CPU2 I2C1 clock enable" "0,1"
|
|
bitfld.long 0x0 14. "SPI2EN,CPU2 SPI2 clock enable" "0,1"
|
|
bitfld.long 0x0 10. "RTCAPBEN,CPU2 RTC APB clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LCDEN,CPU2 LCD clock enable" "0,1"
|
|
bitfld.long 0x0 0. "TIM2EN,CPU2 TIM2 timer clock enable" "0,1"
|
|
line.long 0x4 "C2APB1ENR2,CPU2 APB1 peripheral clock enable register 2"
|
|
bitfld.long 0x4 5. "LPTIM2EN,CPU2 LPTIM2EN" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU2 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU2 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU2 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "LPUART1EN,CPU2 Low power UART 1 clock enable" "0,1"
|
|
endif
|
|
line.long 0x8 "C2APB2ENR,CPU2 APB2ENR"
|
|
bitfld.long 0x8 21. "SAI1EN,CPU2 SAI1 clock enable" "0,1"
|
|
bitfld.long 0x8 18. "TIM17EN,CPU2 TIM17 timer clock enable" "0,1"
|
|
bitfld.long 0x8 17. "TIM16EN,CPU2 TIM16 timer clock enable" "0,1"
|
|
bitfld.long 0x8 14. "USART1EN,CPU2 USART1clock enable" "0,1"
|
|
bitfld.long 0x8 12. "SPI1EN,CPU2 SPI1 clock enable" "0,1"
|
|
bitfld.long 0x8 11. "TIM1EN,CPU2 TIM1 timer clock enable" "0,1"
|
|
line.long 0xC "C2APB3ENR,CPU2 APB3ENR"
|
|
bitfld.long 0xC 1. "EN802,CPU2 802.15.4 interface clock enable" "0,1"
|
|
bitfld.long 0xC 0. "BLEEN,CPU2 BLE interface clock enable" "0,1"
|
|
line.long 0x10 "C2AHB1SMENR,CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x10 16. "TSCSMEN,CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x10 12. "CRCSMEN,CPU2 CRCSMEN" "0,1"
|
|
bitfld.long 0x10 9. "SRAM1SMEN,SRAM1 interface clock enable during CPU1 CSleep mode" "0,1"
|
|
bitfld.long 0x10 2. "DMAMUXSMEN,CPU2 DMAMUX clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x10 1. "DMA2SMEN,CPU2 DMA2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x10 0. "DMA1SMEN,CPU2 DMA1 clocks enable during Sleep and Stop modes" "0,1"
|
|
line.long 0x14 "C2AHB2SMENR,CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x14 16. "AES1SMEN,CPU2 AES1 accelerator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 13. "ADCFSSMEN,CPU2 ADC clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 7. "GPIOHSMEN,CPU2 IO port H clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 4. "GPIOESMEN,CPU2 IO port E clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 3. "GPIODSMEN,CPU2 IO port D clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 2. "GPIOCSMEN,CPU2 IO port C clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x14 1. "GPIOBSMEN,CPU2 IO port B clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GPIOASMEN,CPU2 IO port A clocks enable during Sleep and Stop modes" "0,1"
|
|
line.long 0x18 "C2AHB3SMENR,CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x18 25. "FLASHSMEN,Flash interface clocks enable during CPU2 sleep modes" "0,1"
|
|
bitfld.long 0x18 24. "SRAM2SMEN,SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes" "0,1"
|
|
bitfld.long 0x18 18. "RNGSMEN,True RNG clocks enable during CPU2 sleep modes" "0,1"
|
|
bitfld.long 0x18 17. "AES2SMEN,AES2 accelerator clocks enable during CPU2 sleep modes" "0,1"
|
|
bitfld.long 0x18 16. "PKASMEN,PKA accelerator clocks enable during CPU2 sleep modes" "0,1"
|
|
group.long 0x178++0xF
|
|
line.long 0x0 "C2APB1SMENR1,CPU2 APB1SMENR1"
|
|
bitfld.long 0x0 31. "LPTIM1SMEN,Low power timer 1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 26. "USBSMEN,USB FS clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 24. "CRSMEN,CRS clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 23. "I2C3SMEN,I2C3 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 21. "I2C1SMEN,I2C1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 14. "SPI2SMEN,SPI2 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 10. "RTCAPBSMEN,RTC APB clocks enable during CPU2 Sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LCDSMEN,LCD clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "TIM2SMEN,TIM2 timer clocks enable during CPU2 Sleep mode" "0,1"
|
|
line.long 0x4 "C2APB1SMENR2,CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2"
|
|
bitfld.long 0x4 5. "LPTIM2SMEN,Low power timer 2 clocks enable during CPU2 Sleep mode" "0,1"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*"))
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
endif
|
|
line.long 0x8 "C2APB2SMENR,CPU2 APB2SMENR"
|
|
bitfld.long 0x8 21. "SAI1SMEN,SAI1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x8 18. "TIM17SMEN,TIM17 timer clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x8 17. "TIM16SMEN,TIM16 timer clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x8 14. "USART1SMEN,USART1clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x8 12. "SPI1SMEN,SPI1 clocks enable during CPU2 Sleep mode" "0,1"
|
|
bitfld.long 0x8 11. "TIM1SMEN,TIM1 timer clocks enable during CPU2 Sleep mode" "0,1"
|
|
line.long 0xC "C2APB3SMENR,CPU2 APB3SMENR"
|
|
bitfld.long 0xC 1. "SMEN802,802.15.4 interface clocks enable during CPU2 Sleep modes" "0,1"
|
|
bitfld.long 0xC 0. "BLESMEN,BLE interface clocks enable during CPU2 Sleep mode" "0,1"
|
|
tree.end
|
|
tree "RNG (Random Number Generator)"
|
|
base ad:0x58001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
bitfld.long 0x0 6. "BYP,Bypass mode enable" "0,1"
|
|
bitfld.long 0x0 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "RNGEN,Random number generator enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0,1"
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0,1"
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
|
|
rbitfld.long 0x4 0. "DRDY,Data ready" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DR,data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 24. "ITSE,timestamp on internal event enable" "0,1"
|
|
bitfld.long 0x8 23. "COE,Calibration output enable" "0,1"
|
|
bitfld.long 0x8 21.--22. "OSEL,Output selection" "0,1,2,3"
|
|
bitfld.long 0x8 20. "POL,Output polarity" "0,1"
|
|
bitfld.long 0x8 19. "COSEL,Calibration output selection" "0,1"
|
|
bitfld.long 0x8 18. "BKP,Backup" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "SUB1H,Subtract 1 hour (winter time change)" "0,1"
|
|
bitfld.long 0x8 16. "ADD1H,Add 1 hour (summer time change)" "0,1"
|
|
bitfld.long 0x8 15. "TSIE,Time-stamp interrupt enable" "0,1"
|
|
bitfld.long 0x8 14. "WUTIE,Wakeup timer interrupt enable" "0,1"
|
|
bitfld.long 0x8 13. "ALRBIE,Alarm B interrupt enable" "0,1"
|
|
bitfld.long 0x8 12. "ALRAIE,Alarm A interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TSE,Time stamp enable" "0,1"
|
|
bitfld.long 0x8 10. "WUTE,Wakeup timer enable" "0,1"
|
|
bitfld.long 0x8 9. "ALRBE,Alarm B enable" "0,1"
|
|
bitfld.long 0x8 8. "ALRAE,Alarm A enable" "0,1"
|
|
bitfld.long 0x8 6. "FMT,Hour format" "0,1"
|
|
bitfld.long 0x8 5. "BYPSHAD,Bypass the shadow registers" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "REFCKON,Reference clock detection enable (50 or 60 Hz)" "0,1"
|
|
bitfld.long 0x8 3. "TSEDGE,Time-stamp event active edge" "0,1"
|
|
bitfld.long 0x8 0.--2. "WCKSEL,Wakeup clock selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "ISR,initialization and status register"
|
|
bitfld.long 0xC 17. "ITSF,INTERNAL TIME-STAMP FLAG" "0,1"
|
|
rbitfld.long 0xC 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0xC 15. "TAMP3F,RTC_TAMP3 detection flag" "0,1"
|
|
bitfld.long 0xC 14. "TAMP2F,RTC_TAMP2 detection flag" "0,1"
|
|
bitfld.long 0xC 13. "TAMP1F,Tamper detection flag" "0,1"
|
|
bitfld.long 0xC 12. "TSOVF,Time-stamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "TSF,Time-stamp flag" "0,1"
|
|
bitfld.long 0xC 10. "WUTF,Wakeup timer flag" "0,1"
|
|
bitfld.long 0xC 9. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0xC 8. "ALRAF,Alarm A flag" "0,1"
|
|
bitfld.long 0xC 7. "INIT,Initialization mode" "0,1"
|
|
rbitfld.long 0xC 6. "INITF,Initialization flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RSF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0xC 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0xC 3. "SHPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
rbitfld.long 0xC 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
rbitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x10 "PRER,prescaler register"
|
|
hexmask.long.byte 0x10 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x10 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x14 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x14 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMBR,alarm B register"
|
|
bitfld.long 0x4 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x4 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x4 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--27. 1. "DU,Date units or day in BCD format"
|
|
bitfld.long 0x4 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x4 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x4 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x4 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x4 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SU,Second units in BCD format"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x3C++0x63
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
line.long 0x4 "TAMPCR,tamper configuration register"
|
|
bitfld.long 0x4 24. "TAMP3MF,Tamper 3 mask flag" "0,1"
|
|
bitfld.long 0x4 23. "TAMP3NOERASE,Tamper 3 no erase" "0,1"
|
|
bitfld.long 0x4 22. "TAMP3IE,Tamper 3 interrupt enable" "0,1"
|
|
bitfld.long 0x4 21. "TAMP2MF,Tamper 2 mask flag" "0,1"
|
|
bitfld.long 0x4 20. "TAMP2NOERASE,Tamper 2 no erase" "0,1"
|
|
bitfld.long 0x4 19. "TAMP2IE,Tamper 2 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TAMP1MF,Tamper 1 mask flag" "0,1"
|
|
bitfld.long 0x4 17. "TAMP1NOERASE,Tamper 1 no erase" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1IE,Tamper 1 interrupt enable" "0,1"
|
|
bitfld.long 0x4 15. "TAMPPUDIS,TAMPER pull-up disable" "0,1"
|
|
bitfld.long 0x4 13.--14. "TAMPPRCH,Tamper precharge duration" "0,1,2,3"
|
|
bitfld.long 0x4 11.--12. "TAMPFLT,Tamper filter count" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "TAMPFREQ,Tamper sampling frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "TAMPTS,Activate timestamp on tamper detection event" "0,1"
|
|
bitfld.long 0x4 6. "TAMP3TRG,Active level for tamper 3" "0,1"
|
|
bitfld.long 0x4 5. "TAMP3E,Tamper 3 detection enable" "0,1"
|
|
bitfld.long 0x4 4. "TAMP2TRG,Active level for tamper 2" "0,1"
|
|
bitfld.long 0x4 3. "TAMP2E,Tamper 2 detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TAMPIE,Tamper interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "TAMP1TRG,Active level for tamper 1" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1E,Tamper 1 detection enable" "0,1"
|
|
line.long 0x8 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x8 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x10 "OR,option register"
|
|
bitfld.long 0x10 1. "RTC_OUT_RMP,RTC_OUT remap" "0,1"
|
|
bitfld.long 0x10 0. "RTC_ALARM_TYPE,RTC_ALARM on PC13 output type" "0,1"
|
|
line.long 0x14 "BKP0R,backup register"
|
|
hexmask.long 0x14 0.--31. 1. "BKP,BKP"
|
|
line.long 0x18 "BKP1R,backup register"
|
|
hexmask.long 0x18 0.--31. 1. "BKP,BKP"
|
|
line.long 0x1C "BKP2R,backup register"
|
|
hexmask.long 0x1C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x20 "BKP3R,backup register"
|
|
hexmask.long 0x20 0.--31. 1. "BKP,BKP"
|
|
line.long 0x24 "BKP4R,backup register"
|
|
hexmask.long 0x24 0.--31. 1. "BKP,BKP"
|
|
line.long 0x28 "BKP5R,backup register"
|
|
hexmask.long 0x28 0.--31. 1. "BKP,BKP"
|
|
line.long 0x2C "BKP6R,backup register"
|
|
hexmask.long 0x2C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x30 "BKP7R,backup register"
|
|
hexmask.long 0x30 0.--31. 1. "BKP,BKP"
|
|
line.long 0x34 "BKP8R,backup register"
|
|
hexmask.long 0x34 0.--31. 1. "BKP,BKP"
|
|
line.long 0x38 "BKP9R,backup register"
|
|
hexmask.long 0x38 0.--31. 1. "BKP,BKP"
|
|
line.long 0x3C "BKP10R,backup register"
|
|
hexmask.long 0x3C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x40 "BKP11R,backup register"
|
|
hexmask.long 0x40 0.--31. 1. "BKP,BKP"
|
|
line.long 0x44 "BKP12R,backup register"
|
|
hexmask.long 0x44 0.--31. 1. "BKP,BKP"
|
|
line.long 0x48 "BKP13R,backup register"
|
|
hexmask.long 0x48 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4C "BKP14R,backup register"
|
|
hexmask.long 0x4C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x50 "BKP15R,backup register"
|
|
hexmask.long 0x50 0.--31. 1. "BKP,BKP"
|
|
line.long 0x54 "BKP16R,backup register"
|
|
hexmask.long 0x54 0.--31. 1. "BKP,BKP"
|
|
line.long 0x58 "BKP17R,backup register"
|
|
hexmask.long 0x58 0.--31. 1. "BKP,BKP"
|
|
line.long 0x5C "BKP18R,backup register"
|
|
hexmask.long 0x5C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x60 "BKP19R,backup register"
|
|
hexmask.long 0x60 0.--31. 1. "BKP,BKP"
|
|
tree.end
|
|
sif (cpuis("STM32WB35*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "SAI (Serial Audio Interface)"
|
|
base ad:0x40015400
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "GCR,Global configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "GCR,Global configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
|
|
endif
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "BCR1,BConfiguration register 1"
|
|
bitfld.long 0x0 27. "MCKEN,Master clock generation enable" "0,1"
|
|
bitfld.long 0x0 26. "OSR,Oversampling ratio for master clock" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider"
|
|
bitfld.long 0x0 16. "SAIEN,Audio block B enable" "0,1"
|
|
bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1"
|
|
newline
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 16. "SAIBEN,Audio block B enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 16. "SAIBEN,Audio block B enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
endif
|
|
bitfld.long 0x0 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x0 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
line.long 0x4 "BCR2,BConfiguration register 2"
|
|
bitfld.long 0x4 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x4 13. "CPL,Complement bit" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECNT,Mute counter"
|
|
bitfld.long 0x4 3. "FFLUSH,FIFO flush" "0,1"
|
|
endif
|
|
bitfld.long 0x4 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x4 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x4 4. "TRIS,Tristate management on data line" "0,1"
|
|
newline
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "BFRCR,Bframe configuration register"
|
|
bitfld.long 0x8 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x8 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x8 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FRL,Frame length"
|
|
line.long 0xC "BSLOTR,BSlot register"
|
|
hexmask.long.word 0xC 16.--31. 1. "SLOTEN,Slot enable"
|
|
hexmask.long.byte 0xC 8.--11. 1. "NBSLOT,Number of slots in an audio frame"
|
|
bitfld.long 0xC 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x10 "BIM,BInterrupt mask register"
|
|
bitfld.long 0x10 6. "LFSDETIE,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x10 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "BSR,BStatus register"
|
|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "BCLRFR,BClear flag register"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "BDR,BData register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "ACR1,AConfiguration register 1"
|
|
bitfld.long 0x0 27. "MCKEN,Master clock generation enable" "0,1"
|
|
bitfld.long 0x0 26. "OSR,Oversampling ratio for master clock" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCKDIV,Master clock divider"
|
|
bitfld.long 0x0 16. "SAIEN,Audio block B enable" "0,1"
|
|
bitfld.long 0x0 13. "OUTDRIV,Output drive" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1"
|
|
newline
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 16. "SAIBEN,Audio block B enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 16. "SAIBEN,Audio block B enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
endif
|
|
bitfld.long 0x0 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x0 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
line.long 0x4 "ACR2,AConfiguration register 2"
|
|
bitfld.long 0x4 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x4 13. "CPL,Complement bit" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECNT,Mute counter"
|
|
bitfld.long 0x4 3. "FFLUSH,FIFO flush" "0,1"
|
|
endif
|
|
bitfld.long 0x4 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x4 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x4 4. "TRIS,Tristate management on data line" "0,1"
|
|
newline
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "AFRCR,Aframe configuration register"
|
|
bitfld.long 0x8 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x8 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x8 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FRL,Frame length"
|
|
line.long 0xC "ASLOTR,ASlot register"
|
|
hexmask.long.word 0xC 16.--31. 1. "SLOTEN,Slot enable"
|
|
hexmask.long.byte 0xC 8.--11. 1. "NBSLOT,Number of slots in an audio frame"
|
|
bitfld.long 0xC 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x10 "AIM,AInterrupt mask register"
|
|
bitfld.long 0x10 6. "LFSDET,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x10 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "ASR,AStatus register"
|
|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ACLRFR,AClear flag register"
|
|
sif (cpuis("STM32WB35*"))
|
|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x0 4. "CCNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "CMUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ADR,AData register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PDMCR,PDM control register"
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 11. "CKEN4,Clock enable of bitstream clock number 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 11. "CKEN4,Clock enable of bitstream clock number 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
bitfld.long 0x0 10. "CKEN3,Clock enable of bitstream clock number 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
bitfld.long 0x0 10. "CKEN3,Clock enable of bitstream clock number 3" "0,1"
|
|
endif
|
|
bitfld.long 0x0 9. "CKEN2,Clock enable of bitstream clock number 2" "0,1"
|
|
bitfld.long 0x0 8. "CKEN1,Clock enable of bitstream clock number 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "MICNBR,Number of microphones" "0,1,2,3"
|
|
bitfld.long 0x0 0. "PDMEN,PDM enable" "0,1"
|
|
line.long 0x4 "PDMDLY,PDM delay register"
|
|
bitfld.long 0x4 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "DLYM1R,Delay line for second microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "DLYM1L,Delay line for first microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
tree "SPI (Serial Peripheral Interface/Inter-IC Sound)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
tree.end
|
|
endif
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*")||cpuis("STM32WB30*")||cpuis("STM32WB35*")||cpuis("STM32WB50*"))
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "MEMRMP,memory remap register"
|
|
bitfld.long 0x0 0.--2. "MEM_MODE,Memory mapping selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CFGR1,configuration register 1"
|
|
hexmask.long.byte 0x4 26.--31. 1. "FPU_IE,Floating Point Unit interrupts enable bits"
|
|
bitfld.long 0x4 22. "I2C3_FMP,I2C3 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x4 20. "I2C1_FMP,I2C1 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x4 19. "I2C_PB9_FMP,Fast-mode Plus (Fm+) driving capability activation on PB9" "0,1"
|
|
bitfld.long 0x4 18. "I2C_PB8_FMP,Fast-mode Plus (Fm+) driving capability activation on PB8" "0,1"
|
|
bitfld.long 0x4 17. "I2C_PB7_FMP,Fast-mode Plus (Fm+) driving capability activation on PB7" "0,1"
|
|
bitfld.long 0x4 16. "I2C_PB6_FMP,Fast-mode Plus (Fm+) driving capability activation on PB6" "0,1"
|
|
bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster enable" "0,1"
|
|
line.long 0x8 "EXTICR1,external interrupt configuration register 1"
|
|
bitfld.long 0x8 12.--14. "EXTI3,EXTI 3 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 8.--10. "EXTI2,EXTI 2 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "EXTI1,EXTI 1 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "EXTI0,EXTI 0 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "EXTICR2,external interrupt configuration register 2"
|
|
bitfld.long 0xC 12.--14. "EXTI7,EXTI 7 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "EXTI6,EXTI 6 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "EXTI5,EXTI 5 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "EXTI4,EXTI 4 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "EXTICR3,external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--14. "EXTI11,EXTI 11 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "EXTI10,EXTI 10 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4.--6. "EXTI9,EXTI 9 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "EXTI8,EXTI 8 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "EXTICR4,external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--14. "EXTI15,EXTI15 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "EXTI14,EXTI14 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 4.--6. "EXTI13,EXTI13 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "EXTI12,EXTI12 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SCSR,SCSR"
|
|
bitfld.long 0x18 31. "C2RFD,CPU2 SRAM fetch (execution) disable." "0,1"
|
|
rbitfld.long 0x18 1. "SRAM2BSY,SRAM2 busy by erase operation" "0,1"
|
|
bitfld.long 0x18 0. "SRAM2ER,SRAM2 Erase" "0,1"
|
|
line.long 0x1C "CFGR2,CFGR2"
|
|
bitfld.long 0x1C 8. "SPF,SRAM2 parity error flag" "0,1"
|
|
bitfld.long 0x1C 3. "ECCL,ECC Lock" "0,1"
|
|
bitfld.long 0x1C 2. "PVDL,PVD lock enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "SPL,SRAM2 parity lock bit" "0,1"
|
|
bitfld.long 0x1C 0. "CLL,Cortex-M4 LOCKUP (Hardfault) output enable bit" "0,1"
|
|
wgroup.long 0x20++0xB
|
|
line.long 0x0 "SWPR,SRAM2 write protection register"
|
|
bitfld.long 0x0 31. "P31WP,SRAM2 page 31 write protection" "0,1"
|
|
bitfld.long 0x0 30. "P30WP,P30WP" "0,1"
|
|
bitfld.long 0x0 29. "P29WP,P29WP" "0,1"
|
|
bitfld.long 0x0 28. "P28WP,P28WP" "0,1"
|
|
bitfld.long 0x0 27. "P27WP,P27WP" "0,1"
|
|
bitfld.long 0x0 26. "P26WP,P26WP" "0,1"
|
|
bitfld.long 0x0 25. "P25WP,P25WP" "0,1"
|
|
bitfld.long 0x0 24. "P24WP,P24WP" "0,1"
|
|
bitfld.long 0x0 23. "P23WP,P23WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "P22WP,P22WP" "0,1"
|
|
bitfld.long 0x0 21. "P21WP,P21WP" "0,1"
|
|
bitfld.long 0x0 20. "P20WP,P20WP" "0,1"
|
|
bitfld.long 0x0 19. "P19WP,P19WP" "0,1"
|
|
bitfld.long 0x0 18. "P18WP,P18WP" "0,1"
|
|
bitfld.long 0x0 17. "P17WP,P17WP" "0,1"
|
|
bitfld.long 0x0 16. "P16WP,P16WP" "0,1"
|
|
bitfld.long 0x0 15. "P15WP,P15WP" "0,1"
|
|
bitfld.long 0x0 14. "P14WP,P14WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13WP,P13WP" "0,1"
|
|
bitfld.long 0x0 12. "P12WP,P12WP" "0,1"
|
|
bitfld.long 0x0 11. "P11WP,P11WP" "0,1"
|
|
bitfld.long 0x0 10. "P10WP,P10WP" "0,1"
|
|
bitfld.long 0x0 9. "P9WP,P9WP" "0,1"
|
|
bitfld.long 0x0 8. "P8WP,P8WP" "0,1"
|
|
bitfld.long 0x0 7. "P7WP,P7WP" "0,1"
|
|
bitfld.long 0x0 6. "P6WP,P6WP" "0,1"
|
|
bitfld.long 0x0 5. "P5WP,P5WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "P4WP,P4WP" "0,1"
|
|
bitfld.long 0x0 3. "P3WP,P3WP" "0,1"
|
|
bitfld.long 0x0 2. "P2WP,P2WP" "0,1"
|
|
bitfld.long 0x0 1. "P1WP,P1WP" "0,1"
|
|
bitfld.long 0x0 0. "P0WP,P0WP" "0,1"
|
|
line.long 0x4 "SKR,SKR"
|
|
hexmask.long.byte 0x4 0.--7. 1. "KEY,SRAM2 write protection key for software erase"
|
|
line.long 0x8 "SWPR2,SRAM2 write protection register 2"
|
|
bitfld.long 0x8 31. "P63WP,SRAM2 page 63 write protection" "0,1"
|
|
bitfld.long 0x8 30. "P62WP,P62WP" "0,1"
|
|
bitfld.long 0x8 29. "P61WP,P61WP" "0,1"
|
|
bitfld.long 0x8 28. "P60WP,P60WP" "0,1"
|
|
bitfld.long 0x8 27. "P59WP,P59WP" "0,1"
|
|
bitfld.long 0x8 26. "P58WP,P58WP" "0,1"
|
|
bitfld.long 0x8 25. "P57WP,P57WP" "0,1"
|
|
bitfld.long 0x8 24. "P56WP,P56WP" "0,1"
|
|
bitfld.long 0x8 23. "P55WP,P55WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "P54WP,P54WP" "0,1"
|
|
bitfld.long 0x8 21. "P53WP,P53WP" "0,1"
|
|
bitfld.long 0x8 20. "P52WP,P52WP" "0,1"
|
|
bitfld.long 0x8 19. "P51WP,P51WP" "0,1"
|
|
bitfld.long 0x8 18. "P50WP,P50WP" "0,1"
|
|
bitfld.long 0x8 17. "P49WP,P49WP" "0,1"
|
|
bitfld.long 0x8 16. "P48WP,P48WP" "0,1"
|
|
bitfld.long 0x8 15. "P47WP,P47WP" "0,1"
|
|
bitfld.long 0x8 14. "P46WP,P46WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "P45WP,P45WP" "0,1"
|
|
bitfld.long 0x8 12. "P44WP,P44WP" "0,1"
|
|
bitfld.long 0x8 11. "P43WP,P43WP" "0,1"
|
|
bitfld.long 0x8 10. "P42WP,P42WP" "0,1"
|
|
bitfld.long 0x8 9. "P41WP,P41WP" "0,1"
|
|
bitfld.long 0x8 8. "P40WP,P40WP" "0,1"
|
|
bitfld.long 0x8 7. "P39WP,P39WP" "0,1"
|
|
bitfld.long 0x8 6. "P38WP,P38WP" "0,1"
|
|
bitfld.long 0x8 5. "P37WP,P37WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "P36WP,P36WP" "0,1"
|
|
bitfld.long 0x8 3. "P35WP,P35WP" "0,1"
|
|
bitfld.long 0x8 2. "P34WP,P34WP" "0,1"
|
|
bitfld.long 0x8 1. "P33WP,P33WP" "0,1"
|
|
bitfld.long 0x8 0. "P32WP,P32WP" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "IMR1,CPU1 interrupt mask register 1"
|
|
bitfld.long 0x0 31. "EXIT15IM,Peripheral EXIT15 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 30. "EXIT14IM,Peripheral EXIT14 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 29. "EXIT13IM,Peripheral EXIT13 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 28. "EXIT12IM,Peripheral EXIT12 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 27. "EXIT11IM,Peripheral EXIT11 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 26. "EXIT10IM,Peripheral EXIT10 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 25. "EXIT9IM,Peripheral EXIT9 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 24. "EXIT8IM,Peripheral EXIT8 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 23. "EXIT7IM,Peripheral EXIT7 interrupt mask to CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "EXIT6IM,Peripheral EXIT6 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 21. "EXIT5IM,Peripheral EXIT5 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 15. "TIM17IM,Peripheral TIM17 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 14. "TIM16IM,Peripheral TIM16 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 13. "TIM1IM,Peripheral TIM1 interrupt mask to CPU1" "0,1"
|
|
line.long 0x4 "IMR2,CPU1 interrupt mask register 2"
|
|
bitfld.long 0x4 20. "PVDIM,Peripheral PVD interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x4 18. "PVM3IM,Peripheral PVM3 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x4 16. "PVM1IM,Peripheral PVM1 interrupt mask to CPU1" "0,1"
|
|
line.long 0x8 "C2IMR1,CPU2 interrupt mask register 1"
|
|
bitfld.long 0x8 12. "ADC,Peripheral ADC interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 11. "COMP,Peripheral COMP interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 10. "AES1,Peripheral AES1 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 9. "RNG,Peripheral RNG interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 8. "PKA,Peripheral PKA interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 6. "FLASH,Peripheral FLASH interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 5. "RCC,Peripheral RCC interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 4. "RTCALARM,Peripheral RTCALARM interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 3. "RTCWKUP,Peripheral RTCWKUP interrupt mask to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RTCSTAMP,Peripheral RTCSTAMP interrupt mask to CPU2" "0,1"
|
|
line.long 0xC "C2IMR2,CPU2 interrupt mask register 1"
|
|
bitfld.long 0xC 22. "LCDIM,Peripheral LCDIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 21. "TSCIM,Peripheral TSCIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 20. "PVDIM,Peripheral PVDIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 18. "PVM3IM,Peripheral PVM3IM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 16. "PVM1IM,Peripheral PVM1IM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 15. "DMAM_UX1_IM,Peripheral DMAM UX1 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 14. "DMA2_CH7_IM,Peripheral DMA2 CH7 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 13. "DMA2_CH6_IM,Peripheral DMA2 CH6 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 12. "DMA2_CH5_IM,Peripheral DMA2 CH5 interrupt mask to CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DMA2_CH4_IM,Peripheral DMA2 CH4 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 10. "DMA2_CH3_IM,Peripheral DMA2 CH3 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 9. "DMA2_CH2_IM,Peripheral DMA2 CH2 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 8. "DMA2_CH1_IM,Peripheral DMA2 CH1 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 6. "DMA1_CH7_IM,Peripheral DMA1 CH7 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 5. "DMA1_CH6_IM,Peripheral DMA1 CH6 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 4. "DMA1_CH5_IM,Peripheral DMA1 CH5 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 3. "DMA1_CH4_IM,Peripheral DMA1 CH4 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 2. "DMA1_CH3_IM,Peripheral DMA1 CH3 interrupt mask to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DMA1_CH2_IM,Peripheral DMA1 CH2 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 0. "DMA1_CH1_IM,Peripheral DMA1 CH1 interrupt mask to CPU2" "0,1"
|
|
line.long 0x10 "SIPCR,secure IP control register"
|
|
bitfld.long 0x10 3. "SRNG,Enable True RNG security" "0,1"
|
|
bitfld.long 0x10 2. "SPKA,Enable PKA security" "0,1"
|
|
bitfld.long 0x10 1. "SAES2,Enable AES2 security." "0,1"
|
|
bitfld.long 0x10 0. "SAES1,Enable AES1 KEY[7:0] security." "0,1"
|
|
tree.end
|
|
endif
|
|
tree "TIM (Timers)"
|
|
base ad:0x0
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "C1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "C3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x30 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x34 "OR,DMA address for full transfer"
|
|
bitfld.long 0x34 4. "TI1_RMP,Input Capture 1 remap" "0,1"
|
|
bitfld.long 0x34 0.--1. "TIM1_ETR_ADC1_RMP,TIM1_ETR_ADC1 remapping capability" "0,1,2,3"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1"
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x3C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x40 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "AF1,DMA address for full transfer"
|
|
bitfld.long 0x44 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM2 (General Purpose Timer)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,Value depends on IUFREMAP in TIM2_CR1." "0,1"
|
|
hexmask.long.word 0x8 16.--30. 1. "CNT_H,High counter value (TIM2 only)"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x8 "OR,TIM2 option register"
|
|
bitfld.long 0x8 2.--3. "TI4_RMP,Input capture 4 remap" "0,1,2,3"
|
|
bitfld.long 0x8 1. "ETR_RMP,External trigger remap" "0,1"
|
|
bitfld.long 0x8 0. "ITR_RMP,Internal trigger remap" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF,TIM2 alternate function option register 1"
|
|
bitfld.long 0x0 14.--16. "ETRSEL,External trigger source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
sif (cpuis("STM32WB30*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR,TIM16 option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x8 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x8 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x8 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x8 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x8 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x8 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0xC "SR,status register"
|
|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0xC 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0xC 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x14++0x33
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x4 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x8 "CCER,capture/compare enable register"
|
|
bitfld.long 0x8 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x8 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0xC "CNT,counter"
|
|
rbitfld.long 0xC 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,counter value"
|
|
line.long 0x10 "PSC,prescaler"
|
|
hexmask.long.word 0x10 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "ARR,auto-reload register"
|
|
hexmask.long.word 0x14 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x18 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x1C "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x20 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x20 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x20 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x20 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x20 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x20 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x20 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x20 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x20 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x24 "DCR,DMA control register"
|
|
hexmask.long.byte 0x24 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x24 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x28 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x28 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x2C "OR,TIM16 option register 1"
|
|
bitfld.long 0x2C 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
line.long 0x30 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x30 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x30 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x30 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x30 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x30 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x30 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR,TIM16 option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x8 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x8 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x8 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x8 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x8 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x8 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0xC "SR,status register"
|
|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0xC 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0xC 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x14++0x33
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x4 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x8 "CCER,capture/compare enable register"
|
|
bitfld.long 0x8 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x8 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0xC "CNT,counter"
|
|
rbitfld.long 0xC 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,counter value"
|
|
line.long 0x10 "PSC,prescaler"
|
|
hexmask.long.word 0x10 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "ARR,auto-reload register"
|
|
hexmask.long.word 0x14 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x18 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x1C "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x20 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x20 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x20 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x20 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x20 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x20 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x20 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x20 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x20 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x24 "DCR,DMA control register"
|
|
hexmask.long.byte 0x24 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x24 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x28 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x28 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x2C "OR,TIM16 option register 1"
|
|
bitfld.long 0x2C 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
line.long 0x30 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x30 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x30 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x30 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x30 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x30 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x30 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB50*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR,TIM16 option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x8 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x8 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x8 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x8 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x8 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x8 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0xC "SR,status register"
|
|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0xC 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0xC 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x14++0x33
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x4 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x8 "CCER,capture/compare enable register"
|
|
bitfld.long 0x8 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x8 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x8 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0xC "CNT,counter"
|
|
rbitfld.long 0xC 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,counter value"
|
|
line.long 0x10 "PSC,prescaler"
|
|
hexmask.long.word 0x10 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "ARR,auto-reload register"
|
|
hexmask.long.word 0x14 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x18 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x1C "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x20 "BDTR,break and dead-time register"
|
|
hexmask.long.byte 0x20 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x20 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x20 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x20 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x20 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x20 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x20 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x20 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x24 "DCR,DMA control register"
|
|
hexmask.long.byte 0x24 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x24 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x28 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x28 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x2C "OR,TIM16 option register 1"
|
|
bitfld.long 0x2C 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
line.long 0x30 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x30 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x30 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x30 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x30 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x30 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x30 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,alternate function register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,alternate function register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,alternate function register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,alternate function register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32WB10*")||cpuis("STM32WB15*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "TSC (Touch Sensing Controller)"
|
|
base ad:0x40024000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CTPH,Charge transfer pulse high"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CTPL,Charge transfer pulse low"
|
|
hexmask.long.byte 0x0 17.--23. 1. "SSD,Spread spectrum deviation"
|
|
bitfld.long 0x0 16. "SSE,Spread spectrum enable" "0,1"
|
|
bitfld.long 0x0 15. "SSPSC,Spread spectrum prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "PGPSC,pulse generator prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5.--7. "MCV,Max count value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. "IODEF,I/O Default mode" "0,1"
|
|
bitfld.long 0x0 3. "SYNCPOL,Synchronization pin polarity" "0,1"
|
|
bitfld.long 0x0 2. "AM,Acquisition mode" "0,1"
|
|
bitfld.long 0x0 1. "START,Start a new acquisition" "0,1"
|
|
bitfld.long 0x0 0. "TSCE,Touch sensing controller enable" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 1. "MCEIE,Max count error interrupt enable" "0,1"
|
|
bitfld.long 0x4 0. "EOAIE,End of acquisition interrupt enable" "0,1"
|
|
line.long 0x8 "ICR,interrupt clear register"
|
|
bitfld.long 0x8 1. "MCEIC,Max count error interrupt clear" "0,1"
|
|
bitfld.long 0x8 0. "EOAIC,End of acquisition interrupt clear" "0,1"
|
|
line.long 0xC "ISR,interrupt status register"
|
|
bitfld.long 0xC 1. "MCEF,Max count error flag" "0,1"
|
|
bitfld.long 0xC 0. "EOAF,End of acquisition flag" "0,1"
|
|
line.long 0x10 "IOHCR,I/O hysteresis control register"
|
|
bitfld.long 0x10 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x10 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x10 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x10 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x10 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x10 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x10 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x10 20. "G6_IO1,G6_IO1" "0,1"
|
|
bitfld.long 0x10 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x10 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x10 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x10 16. "G5_IO1,G5_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x10 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x10 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x10 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x10 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x10 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x10 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x10 8. "G3_IO1,G3_IO1" "0,1"
|
|
bitfld.long 0x10 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x10 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x10 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x10 4. "G2_IO1,G2_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x10 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x10 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x10 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "IOASCR,I/O analog switch control register"
|
|
bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1"
|
|
bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1"
|
|
bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "IOSCR,I/O sampling control register"
|
|
bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1"
|
|
bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1"
|
|
bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "IOCCR,I/O channel control register"
|
|
bitfld.long 0x0 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x0 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x0 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x0 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x0 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x0 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x0 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x0 20. "G6_IO1,G6_IO1" "0,1"
|
|
bitfld.long 0x0 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x0 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x0 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x0 16. "G5_IO1,G5_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x0 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x0 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x0 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x0 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x0 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x0 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x0 8. "G3_IO1,G3_IO1" "0,1"
|
|
bitfld.long 0x0 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x0 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x0 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x0 4. "G2_IO1,G2_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x0 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x0 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x0 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IOGCSR,I/O group control status register"
|
|
rbitfld.long 0x0 22. "G7S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 21. "G6S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 20. "G5S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 19. "G4S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 18. "G3S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 17. "G2S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x0 16. "G1S,Analog I/O group x status" "0,1"
|
|
bitfld.long 0x0 6. "G7E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x0 5. "G6E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x0 4. "G5E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x0 3. "G4E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x0 2. "G3E,Analog I/O group x enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "G2E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x0 0. "G1E,Analog I/O group x enable" "0,1"
|
|
rgroup.long 0x34++0x1B
|
|
line.long 0x0 "IOG1CR,I/O group x counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. "CNT,Counter value"
|
|
line.long 0x4 "IOG2CR,I/O group x counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. "CNT,Counter value"
|
|
line.long 0x8 "IOG3CR,I/O group x counter register"
|
|
hexmask.long.word 0x8 0.--13. 1. "CNT,Counter value"
|
|
line.long 0xC "IOG4CR,I/O group x counter register"
|
|
hexmask.long.word 0xC 0.--13. 1. "CNT,Counter value"
|
|
line.long 0x10 "IOG5CR,I/O group x counter register"
|
|
hexmask.long.word 0x10 0.--13. 1. "CNT,Counter value"
|
|
line.long 0x14 "IOG6CR,I/O group x counter register"
|
|
hexmask.long.word 0x14 0.--13. 1. "CNT,Counter value"
|
|
line.long 0x18 "IOG7CR,I/O group x counter register"
|
|
hexmask.long.word 0x18 0.--13. 1. "CNT,Counter value"
|
|
tree.end
|
|
endif
|
|
tree "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32WB15*"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR_4_15"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB35*"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR_4_15"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR_4_15"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM4"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR_4_15"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR_4_15"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("STM32WB35*")||cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "USB (Universal Serial Bus Full-Speed Device Interface)"
|
|
base ad:0x40006800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "EP0R,endpoint 0 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "EP1R,endpoint 1 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "EP2R,endpoint 2 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "EP3R,endpoint 3 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "EP4R,endpoint 4 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "EP5R,endpoint 5 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "EP6R,endpoint 6 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "EP7R,endpoint 7 register"
|
|
bitfld.word 0x0 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x0 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x0 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x0 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x0 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x0 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x0 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x0 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "EA,Endpoint address"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "CNTR,control register"
|
|
bitfld.word 0x0 15. "CTRM,Correct transfer interrupt mask" "0,1"
|
|
bitfld.word 0x0 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0,1"
|
|
bitfld.word 0x0 13. "ERRM,Error interrupt mask" "0,1"
|
|
bitfld.word 0x0 12. "WKUPM,Wakeup interrupt mask" "0,1"
|
|
bitfld.word 0x0 11. "SUSPM,Suspend mode interrupt mask" "0,1"
|
|
bitfld.word 0x0 10. "RESETM,USB reset interrupt mask" "0,1"
|
|
bitfld.word 0x0 9. "SOFM,Start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x0 8. "ESOFM,Expected start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x0 7. "L1REQM,LPM L1 state request interrupt mask" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "L1RESUME,LPM L1 Resume request" "0,1"
|
|
bitfld.word 0x0 4. "RESUME,Resume request" "0,1"
|
|
bitfld.word 0x0 3. "FSUSP,Force suspend" "0,1"
|
|
bitfld.word 0x0 2. "LPMODE,Low-power mode" "0,1"
|
|
bitfld.word 0x0 1. "PDWN,Power down" "0,1"
|
|
bitfld.word 0x0 0. "FRES,Force USB Reset" "0,1"
|
|
group.word 0x44++0x1
|
|
line.word 0x0 "ISTR,interrupt status register"
|
|
rbitfld.word 0x0 15. "CTR,Correct transfer" "0,1"
|
|
bitfld.word 0x0 14. "PMAOVR,Packet memory area over / underrun" "0,1"
|
|
bitfld.word 0x0 13. "ERR,Error" "0,1"
|
|
bitfld.word 0x0 12. "WKUP,Wakeup" "0,1"
|
|
bitfld.word 0x0 11. "SUSP,Suspend mode request" "0,1"
|
|
bitfld.word 0x0 10. "RESET,reset request" "0,1"
|
|
bitfld.word 0x0 9. "SOF,start of frame" "0,1"
|
|
bitfld.word 0x0 8. "ESOF,Expected start frame" "0,1"
|
|
bitfld.word 0x0 7. "L1REQ,LPM L1 state request" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 4. "DIR,Direction of transaction" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "EP_ID,Endpoint Identifier"
|
|
rgroup.word 0x48++0x1
|
|
line.word 0x0 "FNR,frame number register"
|
|
bitfld.word 0x0 15. "RXDP,Receive data + line status" "0,1"
|
|
bitfld.word 0x0 14. "RXDM,Receive data - line status" "0,1"
|
|
bitfld.word 0x0 13. "LCK,Locked" "0,1"
|
|
bitfld.word 0x0 11.--12. "LSOF,Lost SOF" "0,1,2,3"
|
|
hexmask.word 0x0 0.--10. 1. "FN,Frame number"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "DADDR,device address"
|
|
bitfld.word 0x0 7. "EF,Enable function" "0,1"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ADD,Device address"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "BTABLE,Buffer table address"
|
|
hexmask.word 0x0 3.--15. 1. "BTABLE,Buffer table"
|
|
line.word 0x2 "COUNT0_TX,Transmission byte count 0"
|
|
hexmask.word 0x2 0.--9. 1. "COUNT0_TX,Transmission byte count"
|
|
group.word 0x5A++0x1
|
|
line.word 0x0 "COUNT1_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT1_TX,Transmission byte count"
|
|
group.word 0x62++0x1
|
|
line.word 0x0 "COUNT2_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT2_TX,Transmission byte count"
|
|
group.word 0x6A++0x1
|
|
line.word 0x0 "COUNT3_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT3_TX,Transmission byte count"
|
|
group.word 0x72++0x1
|
|
line.word 0x0 "COUNT4_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT4_TX,Transmission byte count"
|
|
group.word 0x7A++0x1
|
|
line.word 0x0 "COUNT5_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT5_TX,Transmission byte count"
|
|
group.word 0x82++0x1
|
|
line.word 0x0 "COUNT6_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT6_TX,Transmission byte count"
|
|
group.word 0x8A++0x1
|
|
line.word 0x0 "COUNT7_TX,Transmission byte count 0"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT7_TX,Transmission byte count"
|
|
group.word 0x54++0x1
|
|
line.word 0x0 "ADDR0_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR0_RX,Reception buffer address"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "ADDR1_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR1_RX,Reception buffer address"
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "ADDR2_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR2_RX,Reception buffer address"
|
|
group.word 0x6C++0x1
|
|
line.word 0x0 "ADDR3_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR3_RX,Reception buffer address"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "ADDR4_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR4_RX,Reception buffer address"
|
|
group.word 0x7C++0x1
|
|
line.word 0x0 "ADDR5_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR5_RX,Reception buffer address"
|
|
group.word 0x84++0x1
|
|
line.word 0x0 "ADDR6_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR6_RX,Reception buffer address"
|
|
group.word 0x8C++0x1
|
|
line.word 0x0 "ADDR7_RX,Reception buffer address 0"
|
|
hexmask.word 0x0 1.--15. 1. "ADDR7_RX,Reception buffer address"
|
|
group.word 0x56++0x1
|
|
line.word 0x0 "COUNT0_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT0_RX,Reception byte count"
|
|
group.word 0x5E++0x1
|
|
line.word 0x0 "COUNT1_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT1_RX,Reception byte count"
|
|
group.word 0x66++0x1
|
|
line.word 0x0 "COUNT2_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT2_RX,Reception byte count"
|
|
group.word 0x6E++0x1
|
|
line.word 0x0 "COUNT3_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT3_RX,Reception byte count"
|
|
group.word 0x76++0x1
|
|
line.word 0x0 "COUNT4_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT4_RX,Reception byte count"
|
|
group.word 0x7E++0x1
|
|
line.word 0x0 "COUNT5_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT5_RX,Reception byte count"
|
|
group.word 0x86++0x1
|
|
line.word 0x0 "COUNT6_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT6_RX,Reception byte count"
|
|
group.word 0x8E++0x1
|
|
line.word 0x0 "COUNT7_RX,Reception byte count 0"
|
|
bitfld.word 0x0 15. "BL_SIZE,Block size" "0,1"
|
|
hexmask.word.byte 0x0 10.--14. 1. "NUM_BLOCK,Number of blocks"
|
|
hexmask.word 0x0 0.--9. 1. "COUNT7_RX,Reception byte count"
|
|
group.word 0x54++0x1
|
|
line.word 0x0 "LPMCSR,control and status register"
|
|
hexmask.word.byte 0x0 4.--7. 1. "BESL,BESL value"
|
|
bitfld.word 0x0 3. "REMWAKE,RemoteWake value" "0,1"
|
|
bitfld.word 0x0 1. "LPMACK,LPM Token acknowledge enable" "0,1"
|
|
bitfld.word 0x0 0. "LPMEN,LPM support enable" "0,1"
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "BCDR,Battery charging detector("
|
|
bitfld.word 0x0 15. "DPPU,DP pull-up control" "0,1"
|
|
rbitfld.word 0x0 7. "PS2DET,DM pull-up detection status" "0,1"
|
|
rbitfld.word 0x0 6. "SDET,Secondary detection (SD) status" "0,1"
|
|
rbitfld.word 0x0 5. "PDET,Primary detection (PD) status" "0,1"
|
|
rbitfld.word 0x0 4. "DCDET,Data contact detection (DCD) status" "0,1"
|
|
bitfld.word 0x0 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
|
|
bitfld.word 0x0 2. "PDEN,Primary detection (PD) mode enable" "0,1"
|
|
bitfld.word 0x0 1. "DCDEN,Data contact detection (DCD) mode enable" "0,1"
|
|
bitfld.word 0x0 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32WB55??-CM0+")||cpuis("STM32WB55??-CM4"))
|
|
tree "VREFBUF (Voltage Reference Buffer)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "SYSCFG_MEMRMP,memory remap register"
|
|
bitfld.long 0x0 0.--2. "MEM_MODE,Memory mapping selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SYSCFG_CFGR1,configuration register 1"
|
|
hexmask.long.byte 0x4 26.--31. 1. "FPU_IE,Floating Point Unit interrupts enable bits"
|
|
bitfld.long 0x4 22. "I2C3_FMP,I2C3 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x4 20. "I2C1_FMP,I2C1 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x4 19. "I2C_PB9_FMP,Fast-mode Plus (Fm+) driving capability activation on PB9" "0,1"
|
|
bitfld.long 0x4 18. "I2C_PB8_FMP,Fast-mode Plus (Fm+) driving capability activation on PB8" "0,1"
|
|
bitfld.long 0x4 17. "I2C_PB7_FMP,Fast-mode Plus (Fm+) driving capability activation on PB7" "0,1"
|
|
bitfld.long 0x4 16. "I2C_PB6_FMP,Fast-mode Plus (Fm+) driving capability activation on PB6" "0,1"
|
|
bitfld.long 0x4 8. "BOOSTEN,I/O analog switch voltage booster enable" "0,1"
|
|
line.long 0x8 "SYSCFG_EXTICR1,external interrupt configuration register 1"
|
|
bitfld.long 0x8 12.--14. "EXTI3,EXTI 3 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 8.--10. "EXTI2,EXTI 2 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "EXTI1,EXTI 1 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "EXTI0,EXTI 0 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "SYSCFG_EXTICR2,external interrupt configuration register 2"
|
|
bitfld.long 0xC 12.--14. "EXTI7,EXTI 7 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "EXTI6,EXTI 6 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "EXTI5,EXTI 5 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "EXTI4,EXTI 4 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SYSCFG_EXTICR3,external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--14. "EXTI11,EXTI 11 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "EXTI10,EXTI 10 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4.--6. "EXTI9,EXTI 9 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "EXTI8,EXTI 8 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SYSCFG_EXTICR4,external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--14. "EXTI15,EXTI15 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "EXTI14,EXTI14 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 4.--6. "EXTI13,EXTI13 configuration bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "EXTI12,EXTI12 configuration bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SYSCFG_SCSR,SCSR"
|
|
bitfld.long 0x18 31. "C2RFD,CPU2 SRAM fetch (execution) disable." "0,1"
|
|
rbitfld.long 0x18 1. "SRAM2BSY,SRAM2 busy by erase operation" "0,1"
|
|
bitfld.long 0x18 0. "SRAM2ER,SRAM2 Erase" "0,1"
|
|
line.long 0x1C "SYSCFG_CFGR2,CFGR2"
|
|
bitfld.long 0x1C 8. "SPF,SRAM2 parity error flag" "0,1"
|
|
bitfld.long 0x1C 3. "ECCL,ECC Lock" "0,1"
|
|
bitfld.long 0x1C 2. "PVDL,PVD lock enable bit" "0,1"
|
|
bitfld.long 0x1C 1. "SPL,SRAM2 parity lock bit" "0,1"
|
|
bitfld.long 0x1C 0. "CLL,Cortex-M4 LOCKUP (Hardfault) output enable bit" "0,1"
|
|
wgroup.long 0x20++0xB
|
|
line.long 0x0 "SYSCFG_SWPR,SRAM2 write protection register"
|
|
bitfld.long 0x0 31. "P31WP,SRAM2 page 31 write protection" "0,1"
|
|
bitfld.long 0x0 30. "P30WP,P30WP" "0,1"
|
|
bitfld.long 0x0 29. "P29WP,P29WP" "0,1"
|
|
bitfld.long 0x0 28. "P28WP,P28WP" "0,1"
|
|
bitfld.long 0x0 27. "P27WP,P27WP" "0,1"
|
|
bitfld.long 0x0 26. "P26WP,P26WP" "0,1"
|
|
bitfld.long 0x0 25. "P25WP,P25WP" "0,1"
|
|
bitfld.long 0x0 24. "P24WP,P24WP" "0,1"
|
|
bitfld.long 0x0 23. "P23WP,P23WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "P22WP,P22WP" "0,1"
|
|
bitfld.long 0x0 21. "P21WP,P21WP" "0,1"
|
|
bitfld.long 0x0 20. "P20WP,P20WP" "0,1"
|
|
bitfld.long 0x0 19. "P19WP,P19WP" "0,1"
|
|
bitfld.long 0x0 18. "P18WP,P18WP" "0,1"
|
|
bitfld.long 0x0 17. "P17WP,P17WP" "0,1"
|
|
bitfld.long 0x0 16. "P16WP,P16WP" "0,1"
|
|
bitfld.long 0x0 15. "P15WP,P15WP" "0,1"
|
|
bitfld.long 0x0 14. "P14WP,P14WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13WP,P13WP" "0,1"
|
|
bitfld.long 0x0 12. "P12WP,P12WP" "0,1"
|
|
bitfld.long 0x0 11. "P11WP,P11WP" "0,1"
|
|
bitfld.long 0x0 10. "P10WP,P10WP" "0,1"
|
|
bitfld.long 0x0 9. "P9WP,P9WP" "0,1"
|
|
bitfld.long 0x0 8. "P8WP,P8WP" "0,1"
|
|
bitfld.long 0x0 7. "P7WP,P7WP" "0,1"
|
|
bitfld.long 0x0 6. "P6WP,P6WP" "0,1"
|
|
bitfld.long 0x0 5. "P5WP,P5WP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "P4WP,P4WP" "0,1"
|
|
bitfld.long 0x0 3. "P3WP,P3WP" "0,1"
|
|
bitfld.long 0x0 2. "P2WP,P2WP" "0,1"
|
|
bitfld.long 0x0 1. "P1WP,P1WP" "0,1"
|
|
bitfld.long 0x0 0. "P0WP,P0WP" "0,1"
|
|
line.long 0x4 "SYSCFG_SKR,SKR"
|
|
hexmask.long.byte 0x4 0.--7. 1. "KEY,SRAM2 write protection key for software erase"
|
|
line.long 0x8 "SYSCFG_SWPR2,SRAM2 write protection register 2"
|
|
bitfld.long 0x8 31. "P63WP,SRAM2 page 63 write protection" "0,1"
|
|
bitfld.long 0x8 30. "P62WP,P62WP" "0,1"
|
|
bitfld.long 0x8 29. "P61WP,P61WP" "0,1"
|
|
bitfld.long 0x8 28. "P60WP,P60WP" "0,1"
|
|
bitfld.long 0x8 27. "P59WP,P59WP" "0,1"
|
|
bitfld.long 0x8 26. "P58WP,P58WP" "0,1"
|
|
bitfld.long 0x8 25. "P57WP,P57WP" "0,1"
|
|
bitfld.long 0x8 24. "P56WP,P56WP" "0,1"
|
|
bitfld.long 0x8 23. "P55WP,P55WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "P54WP,P54WP" "0,1"
|
|
bitfld.long 0x8 21. "P53WP,P53WP" "0,1"
|
|
bitfld.long 0x8 20. "P52WP,P52WP" "0,1"
|
|
bitfld.long 0x8 19. "P51WP,P51WP" "0,1"
|
|
bitfld.long 0x8 18. "P50WP,P50WP" "0,1"
|
|
bitfld.long 0x8 17. "P49WP,P49WP" "0,1"
|
|
bitfld.long 0x8 16. "P48WP,P48WP" "0,1"
|
|
bitfld.long 0x8 15. "P47WP,P47WP" "0,1"
|
|
bitfld.long 0x8 14. "P46WP,P46WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "P45WP,P45WP" "0,1"
|
|
bitfld.long 0x8 12. "P44WP,P44WP" "0,1"
|
|
bitfld.long 0x8 11. "P43WP,P43WP" "0,1"
|
|
bitfld.long 0x8 10. "P42WP,P42WP" "0,1"
|
|
bitfld.long 0x8 9. "P41WP,P41WP" "0,1"
|
|
bitfld.long 0x8 8. "P40WP,P40WP" "0,1"
|
|
bitfld.long 0x8 7. "P39WP,P39WP" "0,1"
|
|
bitfld.long 0x8 6. "P38WP,P38WP" "0,1"
|
|
bitfld.long 0x8 5. "P37WP,P37WP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "P36WP,P36WP" "0,1"
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bitfld.long 0x8 3. "P35WP,P35WP" "0,1"
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bitfld.long 0x8 2. "P34WP,P34WP" "0,1"
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bitfld.long 0x8 1. "P33WP,P33WP" "0,1"
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bitfld.long 0x8 0. "P32WP,P32WP" "0,1"
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group.long 0x30++0x7
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line.long 0x0 "VREFBUF_CSR,VREF control and status register"
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rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0,1"
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bitfld.long 0x0 2. "VRS,Voltage reference scale" "0,1"
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bitfld.long 0x0 1. "HIZ,High impedance mode" "0,1"
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bitfld.long 0x0 0. "ENVR,Voltage reference buffer enable" "0,1"
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line.long 0x4 "VREFBUF_CCR,calibration control register"
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hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
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group.long 0x100++0x13
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line.long 0x0 "SYSCFG_IMR1,CPU1 interrupt mask register 1"
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bitfld.long 0x0 31. "EXIT15IM,Peripheral EXIT15 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 30. "EXIT14IM,Peripheral EXIT14 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 29. "EXIT13IM,Peripheral EXIT13 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 28. "EXIT12IM,Peripheral EXIT12 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 27. "EXIT11IM,Peripheral EXIT11 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 26. "EXIT10IM,Peripheral EXIT10 interrupt mask to CPU1" "0,1"
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bitfld.long 0x0 25. "EXIT9IM,Peripheral EXIT9 interrupt mask to CPU1" "0,1"
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|
bitfld.long 0x0 24. "EXIT8IM,Peripheral EXIT8 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 23. "EXIT7IM,Peripheral EXIT7 interrupt mask to CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "EXIT6IM,Peripheral EXIT6 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 21. "EXIT5IM,Peripheral EXIT5 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x0 15. "TIM17IM,Peripheral TIM17 interrupt mask to CPU1" "0,1"
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|
bitfld.long 0x0 14. "TIM16IM,Peripheral TIM16 interrupt mask to CPU1" "0,1"
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|
bitfld.long 0x0 13. "TIM1IM,Peripheral TIM1 interrupt mask to CPU1" "0,1"
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|
line.long 0x4 "SYSCFG_IMR2,CPU1 interrupt mask register 2"
|
|
bitfld.long 0x4 20. "PVDIM,Peripheral PVD interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x4 18. "PVM3IM,Peripheral PVM3 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0x4 16. "PVM1IM,Peripheral PVM1 interrupt mask to CPU1" "0,1"
|
|
line.long 0x8 "SYSCFG_C2IMR1,CPU2 interrupt mask register 1"
|
|
bitfld.long 0x8 12. "ADC,Peripheral ADC interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 11. "COMP,Peripheral COMP interrupt mask to CPU2" "0,1"
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|
bitfld.long 0x8 10. "AES1,Peripheral AES1 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 9. "RNG,Peripheral RNG interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 8. "PKA,Peripheral PKA interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 6. "FLASH,Peripheral FLASH interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 5. "RCC,Peripheral RCC interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 4. "RTCALARM,Peripheral RTCALARM interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0x8 3. "RTCWKUP,Peripheral RTCWKUP interrupt mask to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RTCSTAMP,Peripheral RTCSTAMP interrupt mask to CPU2" "0,1"
|
|
line.long 0xC "SYSCFG_C2IMR2,CPU2 interrupt mask register 1"
|
|
bitfld.long 0xC 22. "LCDIM,Peripheral LCDIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 21. "TSCIM,Peripheral TSCIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 20. "PVDIM,Peripheral PVDIM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 18. "PVM3IM,Peripheral PVM3IM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 16. "PVM1IM,Peripheral PVM1IM interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 15. "DMAM_UX1_IM,Peripheral DMAM UX1 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 14. "DMA2_CH7_IM,Peripheral DMA2 CH7 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 13. "DMA2_CH6_IM,Peripheral DMA2 CH6 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 12. "DMA2_CH5_IM,Peripheral DMA2 CH5 interrupt mask to CPU1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DMA2_CH4_IM,Peripheral DMA2 CH4 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 10. "DMA2_CH3_IM,Peripheral DMA2 CH3 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 9. "DMA2_CH2_IM,Peripheral DMA2 CH2 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 8. "DMA2_CH1_IM,Peripheral DMA2 CH1 interrupt mask to CPU1" "0,1"
|
|
bitfld.long 0xC 6. "DMA1_CH7_IM,Peripheral DMA1 CH7 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 5. "DMA1_CH6_IM,Peripheral DMA1 CH6 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 4. "DMA1_CH5_IM,Peripheral DMA1 CH5 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 3. "DMA1_CH4_IM,Peripheral DMA1 CH4 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 2. "DMA1_CH3_IM,Peripheral DMA1 CH3 interrupt mask to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DMA1_CH2_IM,Peripheral DMA1 CH2 interrupt mask to CPU2" "0,1"
|
|
bitfld.long 0xC 0. "DMA1_CH1_IM,Peripheral DMA1 CH1 interrupt mask to CPU2" "0,1"
|
|
line.long 0x10 "SYSCFG_SIPCR,secure IP control register"
|
|
bitfld.long 0x10 3. "SRNG,Enable True RNG security" "0,1"
|
|
bitfld.long 0x10 2. "SPKA,Enable PKA security" "0,1"
|
|
bitfld.long 0x10 1. "SAES2,Enable AES2 security." "0,1"
|
|
bitfld.long 0x10 0. "SAES1,Enable AES1 KEY[7:0] security." "0,1"
|
|
tree.end
|
|
endif
|
|
tree "WWDG (System Window Watchdog)"
|
|
base ad:0x40002C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1"
|
|
tree.end
|
|
AUTOINDENT.OFF
|